AC574

SN54AC574 TI | Alldatasheet

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V CC CLK SN54AC574 ...J O R W PACKAGE SN74AC574 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 3 2 1 20 19 91 0 1 1 1 2 1 3 OE 7Q 1Q G ND CLK VCC SN54AC574 . . . FK PACKAGE (TOP VIEW) /C0083/C0078/C0053/C0052/C0065/C0067/C0053/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0053/C0055/C0052 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00682-V to 6-V VCC Operation /C0068Inputs Accept Voltages to 6 V /C0068Max tpd of 8.5 ns at 5 V /C00683-State Outputs Drive Bus Lines Directly description/ordering information These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ′AC574 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE ) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube SN74AC574N SN74AC574N SOIC − DW Tube SN74AC574DW AC574SOIC − DW Tape and reel SN74AC574DWR AC574 −40°C to 85°C SOP − NS Tape and reel SN74AC574NSR AC574−40 C to 85C SSOP − DB Tape and reel SN74AC574DBR AC574 TSSOP − PW Tube SN74AC574PW AC574TSSOP − PW Tape and reel SN74AC574PWR AC574 CDIP − J Tube SNJ54AC574J SNJ54AC574J −55°C to 125°C CFP − W Tube SNJ54AC574W SNJ54AC574W−55 C to 125C LCCC − FK Tube SNJ54AC574FK SNJ54AC574FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0078/C0053/C0052/C0065/C0067/C0053/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0053/C0055/C0052 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D OUTPUT Q L ↑ H H L ↑ LL L H or L X Q 0 H X X Z logic diagram (positive logic) OE CLK To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

/C0083/C0078/C0053/C0052/C0065/C0067/C0053/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0053/C0055/C0052 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) SN54AC574 SN74AC574 UNITMIN MAX MIN MAX UNIT VCC Supply voltage 2 6 2 6 V VCC = 3 V 2.1 2.1 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 VVIH High-level input voltage VCC = 5.5 V 3.85 3.85 V VCC = 3 V 0.9 0.9 VIL Low-level input voltage VCC = 4.5V 1.35 1.35 VVIL Low-level input voltage VCC = 5.5 V 1.65 1.65 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 3 V −12 −12 IOH High-level output current VCC = 4.5 V −24 −24 mAIOH High-level output current VCC = 5.5 V −24 −24 mA VCC = 3 V 12 12 IOL Low-level output current VCC = 4.5 V 24 24 mAIOL Low-level output current VCC = 5.5 V 24 24 mA ∆t/∆v Input transition rise or fall rate 8 8 ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54AC574 SN74AC574 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 3 V 2.9 2.9 2.9 IOH = −50 µA 4.5 V 4.4 4.4 4.4 VOH IOH = −50 µA 5.5 V 5.4 5.4 5.4 VVOH IOH = −12 mA 3 V 2.56 2.4 2.46 V IOH = −24 mA 4.5 V 3.94 3.7 3.76 IOH = −24 mA 5.5 V 4.94 4.7 4.76 3 V 0.1 0.1 0.1 IOL = 50 µA 4.5 V 0.1 0.1 0.1 VOL IOL = 50 µA 5.5 V 0.1 0.1 0.1 VVOL IOL = 12 mA 3 V 0.36 0.5 0.44 V IOL = 24 mA 4.5 V 0.36 0.5 0.44 IOL = 24 mA 5.5 V 0.36 0.5 0.44 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA IOZ VO = VCC or GND 5.5 V ±0.5 ±5 ±2.5 µA ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA C i VI = VCC or GND 5 V 4.5 pF

/C0083/C0078/C0053/C0052/C0065/C0067/C0053/C0055/C0052/C0044 /C0083/C0078/C0055/C0052/C0065/C0067/C0053/C0055/C0052 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C SN54AC574 SN74AC574 UNITMIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 75 55 60 MHz tw Pulse duration, CLK high or low 6 7.5 7 ns tsu Setup time, data before CLK↑ 2.5 6.5 3 ns th Hold time, data after CLK↑ 1.5 2.5 1.5 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C SN54AC574 SN74AC574 UNITMIN MAX MIN MAX MIN MAX UNIT fclock Clock frequency 95 85 85 MHz tw Pulse duration, CLK high or low 4 5 5 ns tsu Setup time, data before CLK↑ 1.5 3.5 2 ns th Hold time, data after CLK↑ 1.5 2.5 1.5 ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER TO TO TA = 25°C SN54AC574 SN74AC574 UNITPARAMETER TO (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT fmax 75 112 55 60 MHz tPLH CLK Q nstPHL CLK Q 3.5 7.5 12 1 15 3.5 13.5 ns tPZH OE Q 2.5 7 11 1 13 2.5 12 nstPZL OE Q 3 6.5 10.5 1 12.5 3 11.5 ns tPHZ OE Q 3.5 7.5 12 1 14 2.5 13 ns tPLZ OE Q 2 5.5 9 1 10.5 1.5 10 ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER TO TO TA = 25°C SN54AC574 SN74AC574 UNITPARAMETER TO (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT fmax 95 153 85 85 MHz tPLH CLK Q 2 6 9.5 1.5 11.5 2 11 nstPHL tPZH OE Q 2 5 8.5 1.5 9.5 2 9 nstPZL OE Q 2 5 8 1.5 9.5 1.5 9 ns tPHZ OE Q ns tPLZ OE Q 1 4.5 7.5 1.5 9 1 8.5 ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance C L = 50 pF, f = 1 MHz 40 pF

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9677301Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-9677301QRA ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type 5962-9677301QSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type SN74AC574DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI SN74AC574DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AC574NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AC574NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI SN74AC574PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AC574PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54AC574FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54AC574J ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SNJ54AC574W ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 2

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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