A918CY-4R7M

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REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781/329-4700 www.analog.com Fax: © Analog Devices, Inc. All rights reserved. ADN8830 Thermoelectric Cooler Controller

FEATURES

Small Size: 5 mm /H11547 5 mm LFCSP Low Noise: <0.5% TEC Current Ripple Long-Term Temperature Stability: /H115500.01/H11543C Temperature Lock Indication Temperature Monitoring Output Oscillator Synchronization with an External Signal Clock Phase Adjustment for Multiple Controllers Programmable Switching Frequency up to 1 MHz Thermistor Failure Alarm Maximum TEC Voltage Programmability

APPLICATIONS

Thermoelectric Cooler (TEC) Temperature Control Resistive Heating Element Control Temperature Stabilization Substrate (TSS) Control FUNCTIONAL BLOCK DIAGRAM PID COMPENSA TION NETWORK TEMPERA TURE MEASUREMENT AMPLIFIER PWM CONTROLLER FROM THERMISTOR TEMPERA TURE SET INPUT VO LTAG E REFERENCEVREF OSCILLA TOR FREQUENCY/PHASE CONTROL P-CHANNEL (UPPER MOSFET) N-CHANNEL MOSFET DRIVERS P-CHANNEL (LOWER MOSFET) N-CHANNEL GENERAL DESCRIPTION The ADN8830 is a monolithic controller that drives a thermo- electric cooler (TEC) to stabilize the temperature of a laser diode or a passive component used in telecommunications equipment. This device relies on a negative temperature coefficient (NTC) thermistor to sense the temperature of the object attached to the TEC. The target temperature is set with an analog input voltage either from a DAC or an external resistor divider. The loop is stabilized by a PID compensation amplifier with high stability and low noise. The compensation network can be adjusted by the user to optimize temperature settling time. The component values for this network can be calculated based on the thermal transfer function of the laser diode or obtained from the lookup table given in the Application Notes section. Voltage outputs are provided to monitor both the temperature of the object and the voltage across the TEC. A voltage reference of 2.5 V is also provided. 2012 D 781/461-3113

REV. –2– ADN8830–SPECIFICATIONS (@ VDD = 3.3 V to 5.0 V, VGND = 0 V, TA = 25/H11543C, TSET = 25/H11543C, using typical application configuration as shown in Figure 1, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit TEMPERATURE STABILITY Long-Term Stability Using 10 k Ω thermistor with PWM OUTPUT DRIVERS Output Transition Time t R, tF CL = 3,300 pF 20 ns Nonoverlapping Clock Delay 50 65 ns Output Resistance R O (N1, P1) I L = 50 mA 6 Ω Output Voltage Swing OUT A V LIM = 0 V 0 V DD V Output Voltage Ripple /H9004OUT A f CLK = 1 MHz 0.2 % Output Current Ripple /H9004ITEC fCLK = 1 MHz 0.2 % LINEAR OUTPUT AMPLIFIER Output Resistance R O, P2 IOUT = 2 mA 85 Ω RO, N2 IOUT = 2 mA 178 Ω Output Voltage Swing OUT B 0 V DD V POWER SUPPLY Power Supply Voltage V DD 3.0 5.5 V Power Supply Rejection Ratio PSRR V DD = 3.3 V to 5 V, VTEC = 0 V 80 92 dB –40°C ≤ TA ≤ +85°C6 0 d B Supply Current I SY PWM not switching 8 12 mA –40°C ≤ TA ≤ +85°C1 5 m A Shutdown Current I SD Pin 10 = 0 V 5 μA Soft-Start Charging Current I SS 15 μA Undervoltage Lockout V OLOCK Low-to-high threshold 2.0 2.7 V ERROR AMPLIFIER Input Offset Voltage V OS VCM = 1.5 V 50 250 μV Gain A V, IN 20 V/V Input Voltage Range V CM 0.2 2.0 V Common-Mode Rejection Ratio CMRR 0.2 V < V CM < 2.0 V 58 68 dB –40°C ≤ TA ≤ +85°C5 5 d B Open-Loop Input Impedance R IN 1G Ω Gain-Bandwidth Product GBW 2 MHz REFERENCE VOLTAGE Reference Voltage V REF IREF < 2 mA 2.37 2.47 2.57 V OSCILLATOR Synchronization Range f CLK Pin 25 connected to external clock 200 1,000 kHz Oscillator Frequency f CLK Pin 24 = VDD; (R = 150 kΩ; 800 1,000 1,250 kHz Pin 25 = GND) LOGIC CONTROL* Logic Low Input Threshold 0.2 V Logic High Input Threshold 3 V Logic Low Output Level 0.2 V Logic High Output Threshold V DD – 0.2 V *Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 μA). Specifications subject to change without notice. D

REV. ADN8830 –3– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN8830 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS * ESD RATINGS *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION PIN 1 INDICATOR TOP VIEW

24 COMPOSC

23 PGND

20 PVDD

19 OUT A

18 COMPSWIN

17 COMPSWOUT

31 TEMPOUT

30 AGND

29 PHASE

28 SYNCOUT

27 SOFTSTART

26 FREQ

25 SYNCIN

NC = NO CONNECT Package Type /H9258JA* /H9258JC Unit 32-Lead LFCSP (ACP) 35 10 °C/W */H9258JA is specified for worst-case conditions, i.e., /H9258JA is specified for a device soldered in a 4-layer circuit board for surface-mount packages. D THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO VCC OR THE GND PLANE.

REV. –4– ADN8830 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description 1 THERMFAULT Digital Output Indicates an Open or Short-Circuit Condition from Thermistor. 2 THERMIN Analog Input Thermistor Feedback Input. 3 SD Digital Input Puts Device into Low Current Shutdown Mode. Active low. 4 TEMPSET Analog Input Target Temperature Input. 5 TEMPLOCK Digital Output Indicates when Thermistor Temperature is within ±0.1°C of Target Tem- perature as Set by TEMPSET Voltage. 6 NC No Connection, except as Noted in the Application Notes Section. 7 VREF Analog Output 2.5 V Reference Voltage. 8 AVDD Power Power for Nondriver Sections. 3.0 V min; 5.5 V max. 9 OUT B Analog Input Linear Output Feedback. Will typically connect to TEC+ pin of TEC. 10 N2 Analog Output Drives Linear Output External NMOS Gate. 11 P2 Analog Output Drives Linear Output External PMOS Gate. 12 TEMPCTL Analog Output Output of Error Amplifier. Connects to COMPFB through feedforward section of compensation network. 13 COMPFB Analog Input Feedback Summing Node of Compensation Amplifier. Connects to TEMPCTL and COMPOUT through compensation network. 14 COMPOUT Analog Output Output of Compensation Amplifier. Connects to COMPFB through feed- back section of compensation network. 15 VLIM Analog Input Sets Maximum Voltage across TEC. 16 VTEC Analog Output Indicates Relative Voltage across the TEC. The 1.5 V corresponds to 0 V across TEC. The 3.0 V indicates maximum output voltage, maximum heat transfer through TEC. 17 COMPSWOUT Analog Output Compensation for Switching Amplifier. 18 COMPSWIN Analog Input Compensation for Switching Amplifier. Capacitor connected between COMPSWIN and COMPSWOUT. 19 OUT A Analog Input PWM Output Feedback. Will typically connect to TEC– pin of TEC. 20 PVDD Power Power for Output Driver Sections. 3.0 V min; 5.5 V max. 21 P1 Digital Output Drives PWM Output External PMOS Gate. 22 N1 Digital Output Drives PWM Output External NMOS Gate. 23 PGND Ground Power Ground. External NMOS devices connect to PGND. Can be connected to digital ground as noise sensitivity at this node is not critical. 24 COMPOSC Analog Input Connect as Indicated in the Application Notes Section. 25 SYNCIN Digital Input Optional Clock Input. If not connected, clock frequency set by FREQ pin. 26 FREQ Analog Input Sets Switching Frequency. 27 SOFTSTART Analog Input Controls Initialization Time for ADN8830 with Capacitor to Ground. 28 SYNCOUT Digital Output Phase Adjusted Clock Output. Phase set from PHASE pin. Can be used to drive SYNCIN of other ADN8830 devices. 29 PHASE Analog Input Sets Switching and SYNCOUT Clock Phase Relative to SYNCIN Clock. 30 AGND Ground Analog Ground. Should be low noise for highest accuracy. 31 TEMPOUT Analog Output Indication of Thermistor Temperature. 32 NC No Connection. D EP Exposed Pad The exposed pad on the bottom of the package must be connected to VCC or the GND plane.

REV. Typical Performance Characteristics–ADN8830 –5– TIME (20ns/DIV) 00 0 VOL T AGE (1V/DIV) 00000000 VDD = 5V TA = 25/H11543C TPC 1. N1 and P1 Rise Time TIME (20ns/DIV) 00 0 VOL T AGE (1V/DIV) 00000000 VDD = 5V TA = 25/H11543C TPC 2. N1 and P1 Fall Time 360 320 PHASE SHIFT (Degrees) 160 120 240 200 280 VPHASE (V) SYNC IN = 1MHz TA = 25/H11543C TPC 3. Clock Phase Shift vs. Phase Voltage 320 PHASE SHIFT (Degrees) 160 120 240 200 280 VPHASE (V) SYNC IN = 200kHz TA = 25/H11543C 360 TPC 4. Clock Phase Shift vs. Phase Voltage TEMPERA TURE (/H11543C) 2.480 2.475 2.455 –40 85 –15 VREF ( V) 10 35 60 2.470 2.465 2.460 TPC 5. V REF vs. Temperature RFREQ (k/H9024) 1,000 800 0 1,500 250 500 750 1,000 1,250 600 400 200 VDD = 5V TA = 25/H11543C SWITCHING FREQUENCY (kHz) TPC 6. Switching Frequency vs. R FREQ D

REV. –6– ADN8830 TEMPERA TURE (/H11543C) 1,000 920 –40 85 –15 SWITCHING FREQUENCY (kHz) 10 35 60 980 960 940 930 990 970 950 VDD = 5V RFREQ = 150k/H9024 TPC 7. Switching Frequency vs. Temperature TEMPERA TURE (/H11543C) –40 85 –15 OFFSET VOL T AGE (/H9262V) 10 35 60 TPC 8. Offset Voltage vs. Temperature COMMON-MODE VOL T AGE (V) 200 –100 –400 0 2.0 0.2 OFFSET VOL T AGE (/H9262V) 100 –200 –300 TPC 9. Offset Voltage vs. Common-Mode Voltage SWITCHING FREQUENCY (kHz) 200 1,000300 400 500 600 700 800 900 SUPPL Y CURRENT (mA) VDD = 5V TA = 25/H11543C USING CIRCUIT SHOWN IN FIGURE 1 TPC 10. Supply Current vs. Switching Frequency TEMPERA TURE (/H11543C) 2.06 2.02 –40 85 –15 THERM FAUL T UPPER THRESHOLD (V) 10 35 60 2.04 2.03 2.05 TPC 11. Open Thermistor Fault Threshold vs. Temperature TEMPERA TURE (/H11543C) 0.26 0.23 –40 85 –15 THERM FAUL T LOWER THRESHOLD (V) 10 35 60 0.25 0.24 TPC 12. Short Thermistor Fault Threshold vs. Temperature D

are used to regulate the temperature of the laser diode.

• A precision input amplifier stage to accurately measure the difference between the target and object temperatures.
• A compensation amplifier to optimize the stability and temperature settling time.
• A high output current stage. Because of the high output currents involved, a TEC controller should operate with high efficiency to minimize the heat generated from power dissipation. In addition, an effective controller should operate down to 3.3 V and have an indication of when the target temperature has been reached. The ADN8830 accomplishes all of these requirements with a minimum of external components. Figure 1 shows a reference design for a typical application. Temperature is monitored by connecting the measurement thermistor to a precision amplifier, called the error amplifier, with a simple resistor divider. This voltage is compared against the temperature set input voltage, creating an error voltage that is proportional to their difference. To maintain accurate wave- length and power from the laser diode, this difference voltage must be as accurate as possible. For this reason, self-correction auto-zero amplifiers are used in the input stage of the ADN8830, providing a maximum offset voltage of 250 μV over time and temperature. This results in final temperature accuracy within ±0.01°C in typical applications, eliminating the ADN8830 as an error source in the temperature control loop. A logic output is provided at TEMPLOCK to indicate when the target temperature has been reached. The output of the error amplifier is then fed into a compensa- tion amplifier. An external network consisting of a few resistors and capacitors is connected around the compensation amplifier. This network can be adjusted by the user to optimize the step THERMFAUL T THERMIN RTH 10k/H9024 @25/H11543C 7.68k/H9024 0.1% VREF 10/H9262F 3.3V VREF TEMPLOCK TEMPSET R3 10k/H9024 0.1% 7.68k/H9024 0.1% VTEC 9 10 11 12 13 14 15 16 10/H9262F 100k/H9024 205k/H9024 C11 1/H9262F R7 1M/H9024 3.3V ADN8830 10nF 3.3V TEC+ 10/H9262F FDW2520C-A FDW2520C-B 22/H9262F CDE ESRD 3.3V FDW2520C-A TEC– 10/H9262F 4.7/H9262H COILCRAFT DO3316-472 FDW2520C-B 32 31 30 29 28 27 26 25 0.1/H9262F 150k/H9024 SYNCOUT TEMPOUT 3.3V 2.2nF C10 330pF 3.3V C12 3.3nF 22/H9262F CDE ESRD

Figure 1. Typical Application Schematic

eliminates errors from slight variances of VREF. outputs are CMOS compatible outputs that are active high. most laser diode applications, 2.5 mV is equivalent to ±0.1°C. greater than 2.5 mV, then TEMPLOCK will output a logic low. 250 μV, which for most applications is within ±0.01°C. single resistor connected from FREQ (Pin 26) to ground. FREQ for some common switching frequencies.

1 MHz 150 k Ω

where fSWITCH is the switching frequency in Hz. detail in the Calculating Power Dissipation and Efficiency section. FREQ should be set to 1.5 M Ω. Figure 6. Using an R-C Network on Pin 24 with vides a 1.5 V reference voltage.

pendent of power supply voltage. Figure 12. VLIM Voltage vs. Maximum TEC Voltage

1.5 V can be used to deactivate the TEC current without

this would cause unpredictable output behavior. set to 1 V. The maximum output voltage is then set to ± 2V . constant voltage and high current, their operation is different. 0 V and an upper limit of the power supply. which is defined as OUT B – OUT A. little or no current through the TEC. data sheet for its typical gate-to-drain capacitance values. nant source of power dissipation at high output currents.

inductor current is shown in Figure 13. Figure 13. Current Waveform Through Inductor duty cycle calculated from Equation 22 with OUT A = VTEC, MAX. 3.3 V supply voltage with a 200 kHz clock and a 4.7 μH inductor. DIL equals 1.33 A with a 200 kHz clock, and I L, MAX is 2.83 A. reason to operate the ADN8830 from a 3 .3 V supply instead. maximum current at which the inductor is rated to remain linear. efficiency and ripple voltage will be dramatically degraded. between inductor height, maximum current, and series resistance. equivalent circuit for the PWM side is given in Figure 14. *Recommend inductor in typical application circuit Figure 1.

Figure 14. Equivalent Circuit for PWM Amplifier and Filter cutoff frequency for a given damping factor. with their equivalent series resistances. yield a worst-case ripple voltage at OUT A of about 6 mV. slightly different for the PWM and linear outputs.

REV. –16– ADN8830 The gate drive outputs for the PWM amplifier at P1 (Pin 21) and N1 (Pin 22) have a typical nonoverlap delay of 65 ns. This is done to ensure that one FET is completely off before the other FET is turned on, preventing current from shooting through both simultaneously. The input capacitance (CISS) of the FET should not exceed 5 nF. The P1 and N1 outputs from the ADN8830 have a typical output impedance of 6 Ω. This creates a time constant in combination with CISS of the external FETs equal to 6 Ω /H11003 CISS. To ensure shoot-through does not occur through these FETs, this time constant should remain less than 30 ns. The linear output from the ADN8830 uses N2 (Pin 10) and P2 (Pin 11) to drive the gates of the linear side FETs, shown as Q3 and Q4 in Figure 1. Local compensation for the linear ampli- fier is achieved through the gate-to-drain capacitances (C GD) of Q3 and Q4. The value of CGD, which can be determined from the data sheet, is usually referred to as C RSS, the reverse transfer capacitance. The exact CRSS value should be determined from a graph that shows capacitance versus drain-to-source voltage, using the power supply voltage as the appropriate V DS. To ensure stability of the linear amplifier, the total C GD of the PMOS device, Q3, should be greater than 2.5 nF and the total CGD of the NMOS should be greater than 150 pF. External capacitance can be added around the FET to increase the effective CGD of the transistor. This is the function of C6 in the typical application schematic shown in Figure 1. If external capaci tance must be added, it will generally only be required around the PMOS transistor. In the event of zero output current through the TEC, there will be no current flowing through Q3 and Q4. In this condition, these FETs will not provide any small signal gain and thus no negative feedback for the linear amplifier. This leaves only a feedforward signal path through C GD, which could cause a settling problem at OUT B. This is often seen as a small signal oscillation at OUT B, but only when the TEC is at or very near zero current. The remedy for this potential minor instability is to add capacitance from OUT B to ground. This may need to be deter- mined empirically, but a good starting point is 1.5 times the total C GD. This is the function of C12 in Figure 1. Note that while adding more CGD around Q3 and Q4 will help to ensure stability, it could potentially increase instability in the zero current dead band region, requiring additional capacitance from OUT B to ground. Bear in mind that the addition of these capacitors is only for local stabilization. The stability of the entire TEC appli- cation may need adjustment, which should be done around the compensation amplifier. This is covered in the Compensation Loop section. There is one additional consideration for selecting both the linear output FETs; they must have a minimum threshold voltage (V T) of 0.6 V. Lower threshold voltages could cause shoot-through current in the linear output transistors. Table V shows the recommended FETs that can be used for the linear output in the ADN8830 application. Table V includes the appropriate external gate-to-drain capacitance (external C GD) and snubber capacitor value (C SNUB) connected from OUT B to ground that should be added to ensure local stability. Table VI shows the recommended PWM output FETs. Although other transistors can be used, these combinations have been tested and are proved stable and reliable for typical applications. Data sheets for these devices can be found at their respective websites: Fairchild – www.fairchildsemi.com Vishay Siliconix – www.vishay.com International Rectifier – www.irf.com Calculating Power Dissipation and Efficiency The total efficiency of the ADN8830 application circuit is simply the ratio of the output power to the TEC divided by the total power delivered from the supply. The idea in minimizing power dissipation is to avoid both drawing additional power and reduc- ing heat generated from the circuit. The dominant sources of power dissipation will include resistive losses, gate charge loss, core loss from the inductor, and the current used by the ADN8830 itself. The on-channel resistance of both the linear and PWM output FETs will affect efficiency primarily at high output currents. Because the linear amplifier operates in a high gain configuration, it will be at either ground or V DD when significant current is flowing through the TEC. In this condition, the power dissipation through the linear output FET will be Pr IFET LIN DS ON TEC,, =× 2 (34) using either the rDS, ON for the NMOS or the PMOS depending on the direction of the current flow. In the typical application setup in Figure 2, if the TEC is cooling the target object, the PMOS is sourcing the current. If the TEC is heating the object, the NMOS will be sinking current. Table IV. Partial List of Capacitors and Key Specifications Value (/H9262F) ESR (m /H9024) Voltage Rating (V) Part Number Manufacturer Website 10 60 6.3 NSP100M6.3D2TR NIC Components www.niccomp.com 22* 35 8 ESRD220M08B Cornell Dubilier www.cornell-dubilier.com 22 35 8 NSP220M8D5TR NIC Components www.niccomp.com 22 35 8 EEFFD0K220R Panasonic www.maco.panasonic.co.jp 47 25 6.3 NSP470M6.3D2TR NIC Components www.niccomp.com 68 18 8 ESRD680M08B Cornell Dubilier www.cornell-dubilier.com 100 95 10 594D107X_010C2T Vishay www.vishay.com *Recommend capacitor in typical application circuit Figure 1. D

dissipated from the circuit. current used by the device multiplied by the supply voltage. power dissipated with the required output power to the load. cuit should be set up as shown in Figure 15. Figure 15. Measuring Efficiency of the ADN8830 Circuit *Recommend transistors in typical application circuit Figure 1. *Recommend transistors in typical application circuit Figure 1.

–22– REV. D OUTLINE DIMENSIONS Figure 26. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

REVISION HISTORY

3/12—Rev. C to Rev. D 11/03—Rev. B to Rev. C 8/03—Rev. A to Rev. B 2/03—Rev. 0 to Rev. A COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A 0.50 BSC BOT TOM VIEWTOP VIEW PIN 1 INDICATOR 916 EXPOSED PAD PIN 1 INDICATOR 3.25 3.10 SQ 2.95 SEATING PLANE

0.05 MAX

0.02 NOM

0.20 REF

0.08 0.30 0.25 0.18 5.10 5.00 SQ 4.90 0.80 0.75 0.70 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.50 0.40 0.30

0.25 MIN

©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02793-0-3/12(B)