TMPA8701CHN TOSHIBA | Alldatasheet
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@ 8 bit single chip microcomputer TLCS-870 Series @ Instruction execution time : 0.5 us (At 8 MHz) @ 412 basic instructions @ Multiplication and Division (8 bits x 8 bits, 16 bits + 8 bits) : Instruction execution time 3.5 us (At 8 MHz) © Bit manipulations (Set / Clear / Complement / Move / Test / Exclusive Or) © 16 bit data operations © 1 byte jump /subroutine-call (Short relative jump / Vector call) @ 13 interrupt sources (External : 4, Internal : 9) © Allsources have independent latches each, and nested interrupt control is available. © Three edge-selectable external interrupts with noise reject © High-speed task switching by register bank changeover @ Input / Output ports (33 pins) @ Two 16 bit Timer / Counters © Timer, Event counter, Pulse width measurement, External trigger timer, Window modes @ Two 8 bit Timer / Counters @ Timer, Event counter, Capture (Pulse width / duty measurement) modes 980910EBP1 @For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. . Site products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property oF other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. —— . , By 12 Purchase of TOSHIBA |? C components conveys a license under the Philips I? C Patent Rights to use these ii components in an I? C system, provided that the system conforms to the I’ C Standard Specification as defined by BUS) Phitips. 3-A8701-1
@ Time Base Timer @ Interrupt frequency : 1 Hz to 16384 Hz @ Watchdog Timer @ Serial bus Interface @ ?C-bus (single master) /8 bits SIO timeshared 2ch @ On-screen display circuit © Character patterns : 251 characters © Character displayed : 32 columns 8 rows @ Composition :8 x 9dots © Size of character : 3 kinds (Line by line) © Color of character : 7 kinds (Character by character) © Variable display position : Horizontal 128 steps, Vertical 256 steps © Fringing, Smoothing function © Conform to US CLOSED CAPTION DECODER REGULATION @ 8 bit successive approximate type A/D converter with sample and hold © 6 analog inputs © Conversion time : 23 us at 8 MHz @ High current outputs : LED direct drive capability (Typ. 20 mA x 4 bits). @ Data slicer circuit 1ch @ Jitter elimination circuit @ Test video signal generator @ Two Power saving operating modes e@sTOPmode : Oscillation stops. Battery / Capacitor back-up. Port output hold / high-impedance. @IDLEmode : CPUstops, and Peripherals operate using high-frequency clock. Release by interrupts. @ Emulation Pod : BMA8700CSNOA 3-A8701-2
Package Pin Assignments (Top View) QFP44-P-1414-0.80D QFP44-P-1414-0.80D a is BIS eo is seeiheeegee geesleexesss < t | — _- 33.92 31 3029 26.27 2625 24.23 SRG (SDA0) P35 <—>| 34 22 |<> P70 HD) TMPA8701CHF (VIN1 /CSIN) P32 <>! 36 20 |~<—> P66 (B) TMPA8701CKF (TCAIVINO) P33 <->) 37 19 |<> P65 (4) TMPA8701CMF NC. 38 18 }<—> P64 (R) Voo —>| 39 7 NC. Vss —>| 40 16 957 pag <>| 41 15 <> P63 (RIN) pat <>] az 14 | <> ps2 (Gin /csour) P42 <>] 43 13 P61 (BIN/AIN5) Pas | 44 12 [xe P60 (Y/BLIN/ AINA) O 423456789 01 Seek ESBS RS [F3s2222 FaSeaes Necn Hage a z i Package Pin Assignments (Top View) SDIP42-P-600-1.78 SDIP42-P-600-1.78 Vss a4 42 P— Voo pao<>G 2 41 <> P33 (TC4/ VINO) pai<>d 3 40 P<> p32 (VINI/CSIN) par<>] 4 39 <— Wey pasa 5s 380 P35 (SDAQ) paar 6 370 P34 (SCLO) pase 7 36 <> P31 (INT4/TC3) pay 9 34H 20 (INTS /STOP) (7¢2/iNTO) P50-<>C} 10 a3 fl<> FEST TMPA8701CHN (sit /ScL1) P51-<>G 11 32 [> xout TMPA8701CKN (S01/SDA1) P52] 12 31 P<— XIN TMPA8701CMN (SCKT/INT2/TC1 /AINO) P53 413 30 TEST (AIN1) P54 14 297 osc2 (AIN2) PSS Gis 28 osct (AIN3) P56 16 27 71 (VD) (Y/BLIN/AIN4) P60 qi7 26H P70 (HD) (aint /AiNs) P61 <>C 18 2s <> P67(v a1) (GIN/CSOUT) P62 C19 24 <> P66 (B) (RIN) P63 20 23 P65 (G) P57<>H] 21 22 P<> P6aiR) 3-A8701-3
eo % memory ROM an, cin, fe, ¢, _¢ an |e [5] Resonatorf OSC) TP er) {],catsol| for OSD {eset On-screen display circuit Elimina-| beret pins ETER VoD . U U ROW U Power 4 ss V Data Memory | | FOMLsenss™e | men (ss Less [6s oe Fa U moses Program rae in TEST Em com | . Tet pin TEST Program Memory standby Controller [ f ff f trom) Time Base 16 bit B bit Serial Bus conmecing {xouT=fP Wom | coer || [warcaon —_ pins frequ. Generator Timer ms : : : Peps Bbit AD eer | ccuk FF CDATA val, Lesa P20 PAT PS7 P35 ‘o ‘ es \\ P40 P50 P30 Video signal vo Fors 3-A8701-4
Lee | resem | Inpasousent 1 bit input/ with latch. When ni — bit input/output port with latch. When used asan input | ¢eernal interrupt input 5 /STOP mode °20 (INTS /STOP) | vo(Input. input) | por, aninterrupt input or STOP mode release signal input, | ™erna) errup ht the latch must be set to "1" natin 38 | P35 (SDAO) VO (WO) 6bit programmable input/output port. (tri-state) Each bit | (2c bus O serial data input /output reef evenerrnteeentne fue stremeneseeeeeere ofthis port can be individually as an input or an output 1 Sanna snsoecsosnsneceeetntse 7 | p34 VO (U ' rial clock input / 37, [P34 (SLO) VOW) +] under software control. During reset, all bits are configured |. Dus Oserial clock input /output 41 [p33 (Tcavvino) | vO(Input, input) | as inputs. Timer / counter 4 input / Video signal input 0 40 | P32 (VIN1/CSIN) | VO (Input, Input) ‘When used as an input port, a timer /counter input, data Video signal input 1 /Composite sync input pe anatomist gigerinputor an interrupt input. the pin must besettothe Picryevnsnew tn nnecti es 36 | P31 (inTa/Tc3) | vO(Input,input) _| input mode. input Serena nero . . . ~--] When used asa serial bus interface input /output, the pin haan 35 | p30 v0 must be set to the sink open drain mode, the latch must be set to “1”, and the pin must be set to the output mode. 8 bit programmable input/output port (tri-state). Each bit 9102 | par to pao of this port can be individually as an input or an output under software control. During reset, all bits are configured asinputs. 21_ [P57 10 8 bit programmable input/output port. (tr-state) a Bee aay oP oon" each otto porteanbe ndidveliyesaninpatoran UTIIIIIIT Irn nnn 4, | to P54,ain1) YO (input) output under software control. During reset, al bits are AID converter analog input ee savnsestnessd Ona eda ae inpute “as asia anais snare” 43 | P53 (AINO/TC1/ | VO (input. Input. When used as an input port, a serial bus interface input, the | 1 input /External interrupt input /SIO1 serial INT2/SCK1) Input, VO) pin must be set to the input mode. When used asserial bus | clock data input pessiefneeeenenestndirnmnnensecd interface utput the lateh mustbesetto"t*,andthepin | peieei esti dats put /eukeat SOV seat put / output Sit serial 12. | P52 (sDa1/S01) | v0 (vo, Output) must be set to the output mode. data output preferred] Wh used as asia bus interface input output, the pin | aeeaet era cicek insu oeteakISIOH i put/output /S101 11 [P51 (sci1/sit) | vO (VO, Input must be set to the sink open drain mode, the latch must be | serial data input ovseesefrseeneeeseessteastenfeceneeeerseeeesenee get to 1", and the pin must be set to the output mode. ere gat MOU cssnseeeenensneneeeessnse a rupt input O/T a 10 | ps0 GNTG/7C2) | vo input. input) External interrupt input 0/ Timer /Counter 2 input 27 | P71 (WD) 2 bit input/output port with latch. When used asan input _| Vertical synchronous signal input esseeseafesseseseeeescseseseeeeed YO (Input) port, a vertical synchronous signal input, or a horizontal sesssnsnneeenssnsannecntsunsnnennsnsnsnnneeeesens 26 | P70 (HD) synchronous signal input, the latch must be set to “1”. Horizontal synchronous signal input, 25 | P67 (Y/BL) 24" | Bee (8) 8 bit programmable input / output port (tri-state, P63 to P6O os Tees (gy | MO Outoun : High current output). Each bit of this port can be R.G,B,Y/BLoutput bY pee wy individually as an input or an output under software oe saaf ete acs sssseseenfesssussseeeesenseseeeeseed control. During reset, all bits are configured as inputs. seseesuesnneeagusssonseensuunsnnennnnnasoneeeessss 19, ] P62 (GIN/CSOUT) | VO (Input/Output) | address OF91}4 must be set to “1” G.B,Y/BL jLnviseesenalgenerarer cute | 48 [P61 (BIN/AINS) | VO(input/input) | When P63 to P6O port used as RIN, GIN, BIN, Y/BLIN input, | inpyt 1p [P60 (w7aLIN7 [v0 Ginput7input) | these ports must be set tothe input mode. } A/D convereter anaiog input AINA) i 28,29. | OSC1OSC2 Resonator connecting pin of on-screen display Ceuta aaeesssssseeseseeseseeessneneest Input, Out R F connecting pin (High frequen 31,32] xin, xour Input, Output jesonator connecting pin (High frequency) For external clock input, XIN is used and XOUT is opened. [33_[ RESET [vo | Resetsignal input or watchdog timer output /address-trap-reset output /aystem-clockreset output TEST Test pin for out-going test. Be tied tolow. | | Vpp.Vss.WWss_| Power Supply +5V,0V(GND) 3-A8701-5
- CPU core Functions The CPU core consists of a CPU, a system clock controller, an interrupt controller, a watchdog timer, and ROM corrective function. This section provides a description of the CPU core, the program memory (ROM), the data memory (RAM), and the reset circuit. 1.1. Memory Address Map The TLCS-870 Series is capable of addressing 64 Kbytes of memory. Figure 1-1 shows the memory address maps of the A8701CH/CK/CM. In the TLCS-870 Series, the memory is organized 4 address spaces (ROM, RAM, SFR, and DBR). It uses a memory mapped I/O system, and all I/O registers are mapped in the SFR / DBR address spaces. There are 16 banks of general-purpose registers. The register banks are also assigned to the first 128 bytes of the RAM address space. sen (/ 00H 0000} 00004 003 0031 00s F F F o0ao a0 toa Register banks i 128 Bytes : 128 Bytes i 128 Bytes (8 registers x16 ooBr 00BF o0BF banks) ooco o0co 0co Ram}: : i i 640 Bytes i 640 Bytes i 640 Bytes 033 033 o33F oF80 oF80 oF80 ed = A000 | = 8400 7 co00 el : : 32512 Entry sreafor : i page cal i 16128 ; 28320 i Bytes instructions H Bytes i Bytes : roo [oe roo [oo ero. [oon Rom i 192 i 192 : 192 Bytes Bytes i Bytes a rs a FOE Pocono]. YEO table for FFCO instructions ror |. eons ror |. 22 0¥es. eeor |e ) (16 vectors) FEO es FEO ees FFEO |S aytes ) Vector table FFFF FEF FEFF interrupts reset ‘A8701CH ‘A8701CK A8701CM (16 vector) (Wete) SFR. Special Function Register includes DBR : Data Buffer Register includes ROM : Read Only Memory includes 10 ports S10 data buffer rogram memory Peripheral control registers ‘On screen display (OSD) control registers RAM : Random Access Memory Includes Peripheral status registers Data slicer control registers Data memory System control registers eee Interrupt control registers jeneral-purpose register banks Program Status Word Figure 1-1. Memory Address Map 3-A8701-6
Electrical Characteristics
Absolute Maximum Ratings (Vss = 0 V) ; Ports P2, P3, P4, P5, P64 to P67, P7 Output Current (Per 1pin) mA Ports P2, P3, PA, P5, P64 to P67, P7 Output Current (Total) mA Operating Temperature [Tope [= 30t0.70 Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded 3-A8701-143
Recommended Operating Conditions | (Vss =0 V, Topr = - 30 to 70°C) NORMAL mode Supply Voltage Vop fe= IDLE mode v
8 MHz
STOP mode | 20 | wo Vpp Vin | Except hysteresis input x0.70 Vpp 2 4.5V Input High Voltage Hysteresis input wee, Vpp Vv Vpp Vir | Except hysteresis input Vop x 0.30 Vpp = 4.5V Input Low Voltage Vit2_ | Hysteresis input Voo Vv x0.25 Vpp vis | = veo asy x0-10 XIN, XOUT Vpp =4.5 to 5.5V | — | 80 | Double frequency Clock Frequency Vpp =4.5 | mode (FORS = 1) MHz fosp |OSC1,OSC2 to5.5V ° Normal freguency 2 12 mode (FORS = 0) Note 1: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Note 2: fc: The condition of power supply voltage is limited to NORMAL and IDLE mode. Furthermore, since the CPU clock serves dual purposes as a clock for the CCD slier, always be sure to use an 8 MHz oscillator. 3-A8701-144
D.C. Characteristics (Vss = 0 V, Topr = — 30 to 70°C) Test we A Parameter Symbol Circuit} Test Condition Typ. Unit Vpp = 5.5 V, [tne [rst | — [ere Nov |- | - | =| . Vpp =5.5V, moacinn [mm [omesanene | = [ARoy [=| = [2] [lina | RESET, STOP Vin=5.5V/0V Output Leakage 1 Open drain ports and Vpp =5.5V, A Current 0 | tri-state ports Vout =5.5V a Output High 7 Vpp =4.5V, Voltage Vouz2 | Tri-state ports lon = -0.7 mA 4.1 Vv Except XOUT, OSC2, Vpp =4.5V, Output Low Voltage | VoL P60 to 63 | - | lov=1.6mA Vv Vpp =4.5V, Output Low Current | lo3 | P60 to P63 | - | Voi=1.0V mA Supply Current in Vpp =5.5V NORMAL Mode pp (Note 3) 12 | 25 | ma Supply Current in fc=8 MHz itt Mode Vin =5.3V/0.2V mA Supply Current in Vpp =5.5V A STOP Mode Vin=5.3V/0.2V MI Note 1: Typical values show those at Topr =25°C, VDD =5 V. Note 2: Input Current : The current through pull-up or pull-down resistor is not included. Note 3: Typical current consumption during A/D conversion is 1.2 mA. A/D Conversion Characteristics (Vss = 0 V, Vpp =4.5 to 5.5 V, Topr = - 30 to 70°C) Test age A Parameter Symbol Circuit Test Condition Typ. Unit Analog Reference Voltage ARE! | = | DD | = | Vv ee ee ee AnalogReference Voltage Range | Varer | — | =Voo-Vss__— | — | Voo| — | Vv | Analog Input Voltage [van [ = [Ms | = |vo0] v | Zero Point Error P= | = | eastessy LEE] Full Scale Error | = | — | | = | = | #2 | tse Note: Total error does not include quantization error. 3-A8701-145
A.C. Chracteristics (Vss = 0 V, Vpp = 4.5 to 5.5 V, Topr = - 30 to 70°C) Test igs . Parameter Symbol | circuit Test Condition Typ. Unit . . In NORMAL mode Machine Cycle Time tey “ws In IDLE mode High Level Clock Pulse Width For external clock operation | 65 5 Low Level Clock Pulse Width (XIN input), fc= 8 MHz ° Recommended Oscillating (Vss = 0 V, Vpp = 4.5 to 5.5 V, Topr = - 30 to 70°C) Parameter Oscillator Frequency Recommended Oscillator Conditions High-frequency . |_8Mnz_| P P Crystal Oscillator | 8MHz |TOYOCOM 2108 8.0000 20pF | 20pF | 6MHz [TOKO — A285HCIS-13319 (5 mm) OsD LC Resonator TOKO _TA285HCIS-13306 (5 mm) XIN XOUT osc osc --f----SMHz.--- J, l : ' (1) High-frequency (2) LC Resonator for OSD Note: An electrical shield by metal shield plate on the surface of the IC package should be recommendable in order to prevent the device from the high electric fieldstress applied from CRT (Cathode Ray Tube) for continuous reliable operation. 3-A8701-146