A7985ATR STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 44
Technical content
Datasheet sections
- 1 Pin settings
- 1.1 Pin connection
- 1.2 Pin description
- 2 Maximum ratings
- 3 Thermal data
- 4 Electrical characteristics
- 5 Functional description
- 5.1 Oscillator and synchronization
- 5.2 Soft-start
- 5.3 Error amplifier and compensation
- 5.4 Overcurrent protection
- 5.5 Enable function
- 5.6 Hysteretic thermal shutdown
- 6 Application information
- 6.1 Input capacitor selection
- 6.2 Inductor selection
- 6.3 Output capacitor selection
- 6.4 Compensation network
- 6.4.1 Type III compensation network
- 6.4.2 Type II compensation networ k
- 6.5 Thermal considerations
- 6.6 Layout considerations
- 6.7 Application circuit
- 7 Application ideas
- 7.1 Positive buck-boost
- 7.2 Inverting buck-boost
Features
2 A DC output current Qualified following AEC-Q100 requirements (see PPAP for more details) 4.5 V to 38 V input voltage Output voltage adjustable from 0.6 V 250 kHz switching frequency, programmable up to 1 MHz Internal soft-start and enable Low dropout operation: 100% duty cycle Voltage feed-forward Zero load current operation Overcurrent and thermal protection HSOP8 package
Applications
Dedicated to automotive applications Automotive LED driving
Description
The A7985A is a step-down switching regulator with a 2.5 A (minimum) current limited embedded Power MOSFET, so it is able to deliver up to 2 A current to the load depending on the application conditions. The input voltage can range from 4.5 V to 38 V, while the output voltage can be set starting from
0.6 V to V
IN. Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz. The HSOP8 package with exposed pad allows the reduction of R th(JA) down to 40 °C/W. Figure 1. Application circuit
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
Table 1. Pin description
2 SYNCH
power turn-ons have a phase shift of half a period. 1.2 V the device is ON and with EN lower than 0.63 V the device is OFF. 4 COMP Error amplifier output to be used for loop frequency compensation. works at its free-running frequency of 250 KHz. CC Unregulated DC input voltage.
2 Maximum ratings
3 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
- Package mounted on demonstration board.
4 Electrical characteristics
TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics
Table 4. Electrical characteristics (continued)
5 Functional description
OFF time of the power switch. synchronization signal. Its switching frequency can be adjusted by an external resistor. A thermal shutdown block, to prevent thermal runaway. Figure 3. Block diagram
5.1 Oscillator and synchronization
shown in Figure 6 by an external resistor connected to ground. according to the input voltage change (see Figure 5.a). through the input capacitor (see the L5988D datasheet). Figure 4. Oscillator circuit block diagram truncation of sawtooth, due to the external synchronization.
FSW is desired switching frequency.
5.2 Soft-start
avoids inrush current surge and makes the output voltage increase monothonically. the soft-start time and then the output voltage slew rate depend on the switching frequency. Figure 7. Soft-start scheme For example, with a switching frequency of 250 kHz, the SSTIME is 8 ms.
5.3 Error amplifier and compensation
mode operational amplifier, so with high DC gain and low output impedance. The uncompensated error amplifier characteristics are shown in Table 5. compensation network selection).
5.4 Overcurrent protection
time” or “blanking time”. The masking time is about 200 ns. skips two pulses. This mechanism is repeated and the device can skip up to seven pulses. the number of skipped cycles is decreased by one unit (see Figure 8). order to keep constant the output current around the current limit. Table 5. Uncompensated error amplifier characteristics
A7985A Functional description This kind of overcurrent protection is effective if the output current is limited. To prevent the current from diverging, the current ripple in the inductor during the ON-time must not be higher than the current ripple during the OFF-time. That is: Equation 4 If the output voltage is shorted, V OUT 0, IOUT = ILIM, D/FSW = TON_MIN, (1-D)/FSW 1/FSW. So from the above equation the maximum switching frequency that guarantees to limit the current results: Equation 5 With RDS(on) = 300 m, DRC = 0.08 , the worst condition is with VIN = 38 V, ILIM = 2.5 A; the maximum frequency to keep the output current limited during the short-circuit results 74 kHz. Based on the pulse-by-pulse mechanism, that reduces the switching frequency down to one eighth, the maximum F SW, adjusted by the FSW pin, that assures a full effective output current limitation is 74 kHz * 8 = 592 kHz. If, with VIN = 38 V, the switching frequency is set higher than 592 kHz, during short-circuit condition the system finds a different equilibrium with higher current. For example, with FSW = 700 kHz and the output shorted to ground, the output current is limited around: Equation 6 where FSW* is 700 kHz divided by eight. VIN V– OUT RDSON IOUT DCR I OUT–– VOUT VF RDSON IOUT DCR I OUT++ + FSW * VF DCR I+ LIM TON_MIN IOUT
Figure 8. Overcurrent protection
5.5 Enable function
than 0.3 V, the device is disabled and the power consumption is reduced to less than 30A. device is disabled. The pin is also VCC compatible.
5.6 Hysteretic thermal shutdown
area, so ensuring an accurate and fast temperature detection.
6 Application information
6.1 Input capacitor selection
The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 7 where I o is the maximum DC output current, D is the duty cycle, is the efficiency. Considering = 1, this function has a maximum at D = 0.5 and it is equal to Io/2. In a specific application the range of possible duty cycles must be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 8 and Equation 9 where V F is the forward voltage on the freewheeling diode and VSW is voltage drop across the internal PDMOS. The peak-to-peak voltage across the input capacitor can be calculated as: Equation 10 where ESR is the equivalent series resistance of the capacitor. Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic/tantalum types. IRMS IO D 2D 2 DMAX VOUT VF+ DMIN VOUT VF+ VPP IO ----– D D
neglecting the small ESR of ceramic capacitors. In Table 6, some multi-layer ceramic capacitors suitable for this device are reported.
6.2 Inductor selection
minimum inductance value in order to have the expected current ripple must be selected. The rule to fix the current ripple value is to have a ripple at 20% -40% of the output current. Table 6. Input MLCC capacitors
where FSW is the switching frequency, 1/(TON + TOFF). inductance value to have IL= 30% of IO is about 28 H. output current that can be delivered, without triggering the overcurrent protection. In Table 7 some inductor part numbers are listed.
6.3 Output capacitor selection
Table 7. Inductors
must be chosen in order to sustain the load transient. In Table 8 below some capacitor series are listed.
6.4 Compensation network
Table 8. Output capacitors
gain changes and how to keep it constant in spite of the external synchronization). Figure 9. The error amplifier, the PWM modulator and the LC output filter As seen in Section 5.3 on page 14, two different kinds of network can compensate the loop. compensation network are illustrated.
6.4.1 Type III compensation network
far from the zero dB frequency. Figure 10. Type III compensation network
and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn. Figure 11. Open loop gain: module Bode diagram
- Choose a value for R 1, usually between 1 k and 5 k.
- Choose a gain (R 4/R1) in order to have the required bandwidth (BW), that means:
where K is the feed-forward constant and 1/K is equal to 18.
- Calculate C 4 by placing the zero at 50% of the output filter double pole frequency (fLC):
- Calculate C 5 by placing the second pole at four times the system bandwidth (BW):
- Set also the first pole at four times th e system bandwidth and also the second zero at
3.5 (FSW/3.5), so lower than 100 kHz if the FSW is set higher than 500 kHz. 32 kHz and the phase margin is 51 °. Figure 12. Open loop gain Bode diagram with ceramic output capacitor
6.4.2 Type II co mpensation network
the stabilizing of the loop. In Figure 13 the Type II network is shown. Figure 13. Type II compensation network
and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)) are drawn. Figure 14. Open loop gain: module Bode diagram
- Choose a value for R 1, usually between 1 k and 5 k, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
- Choose a gain (R 4/R1) in order to have the required bandwidth (BW), that means:
and VS is the sawtooth amplitude. The voltage feed-forward keeps the ratio VS/VIN constant.
- Calculate C 4 by placing the zero one decade below the output filter double pole:
- Then calculate C 3 in order to place the second pole at four times the system bandwidth (BW): Equation 34 For example, with VOUT = 5 V, VIN = 24 V, IO = 2 A, L = 22 H, COUT = 330 F, and ESR = 70 m the Type II compensation network is: Equation 35
36 kHz and the phase margin is 53 °. Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor
6.5 Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if the junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the not-negligible R DS(on) of the power switch; these are equal to: Equation 36 where D is the duty cycle of the application and the maximum RDS(on) overtemperature is 220 m. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increase compared with the ideal case. b) switching losses due to Power MOSF ET turn-on and turn-off; these can be calculated as: Equation 37 where T RISE and TFALL are the overlap times of the voltage across the power switch (VDS) and the current flowing into it during turn-on and turn-off phases, as shown in Figure 16. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 40 ns. c) Quiescent current lo sses, calculated as: Equation 38 where IQ is the quiescent current (IQ = 2.4 mA). The junction temperature TJ can be calculated as: Equation 39 where TA is the ambient temperature and PTOT is the sum of the power losses just seen. Rth(JA) is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth(JA) measured on the demonstration board described in the following paragraph is about 40 °C/W for the HSOP8 package. PSW VIN IOUT TRISE TFALL+ PQ VIN IQ= TJ TA Rth JA PTOT+=
Figure 16. Switching losses
6.6 Layout considerations
be placed very close to the device. close as possible to the input voltage pin of the device. of the converter allowing high power conversion.
In Figure 17 a layout example is shown. Figure 17. Layout example
6.7 Application circuit
In Figure 18 the demonstration board application circuit is shown. Figure 18. Demonstration board application circuit Table 9. Component list
7 Application ideas
7.1 Positive buck-boost
The A7985A can implement the step-up/down converter with a positive output voltage. Figure 34. Positive buck-boost regulator higher than 16 V, the gate must be protected through a Zener diode and resistor).
The current flowing through the internal Power MOSFET is transferred to the load only during the OFF time, so according to the maximum DC switch current (2.0 A), the maximum output current for the buck boost topology can be calculated from Equation 42. Equation 42 where ISW is the average current in the embedded Power MOSFET in the ON time. To chose the right value of the inductor and to manage transient output current, which, for a short time, can exceed the maximum output current calculated by Equation 42, also the peak current in the Power MOSFET must be calculated. The peak current, shown in Equation 43, must be lower than the minimum current limit (2.5 A). Equation 43 where r is defined as the ratio between the inductor current ripple and the inductor DC current. Therefore, in the buck boost topology the maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value). In Figure 35 the maximum output current for the above configuration is depicted, varying the input voltage from 4.5 V to 38 V. The dashed line considers a more accurate estimation of the duty cycles given Equation 44, where power losses across diodes, the external Power MOSFET, and the internal Power MOSFET are taken into account. ISW IOUT ISW,PK IOUT 2---+ 3.7A= r VOUT
Figure 35. Maximum output current according to max. DC switch current (2.0 A):
7.2 Inverting buck-boost
to the standard buck topology. where the duty cycle is given by Equation 46.
8 Package information
specifications, grade definitions and product status are available at: www.st.com. Figure 38. HSOP8 package outline
Table 10. HSOP8 package mechanical data
9 Ordering information
Table 11. Ordering information
Table 12. Document revision history 19-Apr-2012 1 Initial release. 08-Oct-2012 2 Document status promoted from preliminary data to production data. In Section 5.6 changed temperature value from 130 to 120 °C. of Figure 38 and Table 10, minor modifications). Updated cross-references throughout document. Minor modifications throughout document.