A6727B STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 26
Technical content
Datasheet sections
- 1 Typical application circuit and block diagram
- 1.1 Application circuit
- 1.2 Block diagram
- 2 Pin description and connection diagram
- 2.1 Thermal data
- 3 Electrical specifications
- 3.1 Absolute maximum ratings
- 3.2 Electrical characteristics
- 4 Device description
- 5 Driver section
- 5.1 Power dissipation
- 6 Soft-start and disable
- 6.1 Low-side-less startup (LS-less)
- 6.2 Enable/ disable
- 7 Overcurrent protection
- 7.1 Overcurrent threshold setting
- 8 Output voltage monitor and protections
- 8.1 Undervoltage protection
- 8.2 Overvoltage protection
- 8.3 Feedback disconnection protection
- 8.4 Undervoltage lock out
- 9 Application details
- 9.1 Output voltage selection
- 9.2 Compensation network
- 9.3 Layout guidelines
- 10 Application information
- 10.1 Output inductor
- 10.2 Output capacitors
- 10.3 Input capacitors
- 11 Package information
- 11.1 SO-8 package information
- 12 Ordering information
Features
- AEC Q100 qualified grade 1
- Flexible power supply from 5 V to 12 V
- Power conversion input as low as 1.5 V
- ± 1.5 % output voltage accuracy
- High-current integrated drivers
- Adjustable output voltage
- 0.8 V internal reference
- Simple voltage mode control loop
- Sensorless and programmable OCP across
- Low-side R DS(on)
- Oscillator internally fixed at 300 kHz
- Internal soft-start
- LS-less to manage pre-bias startup
- Disable function
- OV/UV protection
- FB disconnection protection
- SO-8 package
Applications
- Dedicated to automotive applications
Description
The A6727B is a single-phase step-down controller with integrated high-current drivers that provides complete control logic, protection and reference voltage to realize a general DC-DC converter by using a compact SO-8 package. The device flexibility allows the management of conversions with power input VIN as low as 1.5 V and device supply voltage in the range of 5 V to 12 V. The A6727B provides simple control loop with voltage mode error-amplifier. The integrated 0.8 V reference allows the regulation of output voltages with ±1.5 % accuracy over temperature variations. The oscillator is internally fixed to 300 kHz. The A6727B provides programmable overcurrent protection as well as over and undervoltage protection. The current information is monitored across the low-side MOSFET RDS(on) saving the use of expensive and space-consuming sense resistors while output voltage is monitored through FB pin. FB disconnection protection prevents excessive and dangerous output voltages from floating FB pin. SO-8 Maturity status link A6727B Automotive single-phase PWM controller A6727B Datasheet DS14159 - Rev 2 - March 2023 For further information contact your local STMicroelectronics sales office.
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
1.2 Block diagram
Figure 2. Block diagram
2 Pin description and connection diagram
Figure 3. Pin connection (top view)
4 VCC
Table 1. Pin description 2 UGATE HS driver output. Connect to HS MOSFET gate. 3 GND All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane. 4 LGATE LS driver output. Connect to LS MOSFET gate.
5 VCC
Device and LS driver power supply. Operative range from 4.1 V to 13.2 V. Filter with at least 1 μF MLCC to GND. resistor ROS to GND may be used to regulate voltages higher than the reference.
7 COMP / DIS/OC
COMP. Error amplifier output. Connect to FB through an RF - CF // CP to compensate the control loop. DIS. The device can be disabled by forcing this pin lower than 0.5 V (typ.). To disable the device, the external pull-down overcomes 10 mA of COMP output current for about 15 ms. Once disabled, COMP output current drops to 0.1 mA. bus) to program OC threshold. When VCC > 5 V, ROCSET needs to be not-connected.
8 PHASE
to monitor when HS MOSFET is off.
2.1 Thermal data
Table 2. Thermal data
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3. Absolute maximum ratings Table 4. ESD performance
3.2 Electrical characteristics
Table 5. Electrical characteristics (VCC = 12 V; TA = - 40 °C to 125 °C, unless otherwise specified.)
- Guaranteed by design, not to be tested
Electrical characteristics
4 Device description
The A6727B is a single-phase PWM controller with embedded high-current drivers that provides complete control logic and protection to realize a general DC-DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its high level of integration, this 8-pin device allows a reduction of cost and size of the power supply solution. The A6727B is designed to operate from a 5 V to 12 V supply bus. Thanks to the high precision 0.8 V internal reference, the output voltage can be precisely regulated as low as 0.8 V with ±1.5 % accuracy over temperature variations. The switching frequency is internally set to 300 kHz. This device provides a simple control loop with a voltage-mode error amplifier. The error amplifier features a 15 MHz gain-bandwidth product and 8 V/µs slew rate, allowing high regulator bandwidth for fast transient response. To avoid load damages, the A6727B provides overcurrent protection as well as overvoltage, undervoltage and feedback disconnection protection. When the device is supplied from 5 V, overcurrent trip threshold is programmable by a simple resistor. Output current is monitored through low-side MOSFET RDS(on), saving the use of expensive and space- consuming sense resistor. Output voltage and feedback disconnection are monitored through FB pin. The A6727B implements soft-start by increasing the internal reference from 0 V to 0.8 V in 5.1 ms (typ.) in closed loop regulation. Low-side-less feature allows the device to perform the soft-start over pre-biased output avoiding high-current return through the output inductor and dangerous negative spikes at the load side. A6727B Device description DS14159 - Rev 2 page 6/26
5 Driver section
The integrated high-current drivers allow different types of power MOSFET to be used (also multiple MOSFETs to reduce the equivalent RDS(on)), maintaining fast switching transition. The driver for the high-side MOSFET uses BOOT pin as supply and PHASE pin as return. The driver for low-side MOSFET uses the VCC pin as supply and GND pin as return. The controller embodies an anti-shoot-through and adaptive deadtime control to minimize low-side body diode conduction time, maintaining good efficiency and saving the use of Schottky diode:
- the device senses the PHASE pin to check that high-side MOSFET is off. When the sensed voltage drops below an internal threshold, the low-side MOSFET is suddenly turned on.
- the device senses the LGATE pin to check that low-side MOSFET is off. When the sensed voltage drops below an internal threshold, the high-side MOSFET is suddenly turned on. If the current flowing in the inductor is negative, the voltage on PHASE pin never drops. To allow the low-side MOSFET to turn on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET does not drop, the low-side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (see maximum duty cycle limitation and recommended operating conditions, in Table 5 ) to be chosen freely.
5.1 Power dissipation
The A6727B embeds high-current MOSFET drivers for both high-side and low-side MOSFETs. The power dissipated by the device avoids overcoming the maximum junction operative temperature. Two main terms contribute to the device power dissipation: bias power and driver power.
- Bias power (P DC) depends on the static consumption of the device through the supply pins and it is calculated as follows (assuming to supply HS and LS drivers with the same VCC of the device): P D C = V C C ⋅ I C C + I BO OT (1)
- Driver power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term has to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs is: P SW = F SW ⋅ Q gHS ⋅ V BO OT − V PH ASE + Q g LS ⋅ V CC (2) where VBOOT -VPHASE is the voltage across the bootstrap capacitor. The external gate resistor helps the device to dissipate the switching power since the same power PSW is dissipated by the internal driver impedance and the external resistor. This process causes a general cooling of the device. A6727B Driver section DS14159 - Rev 2 page 7/26
6 Soft-start and disable
closed loop regulation, gradually charging the output capacitors to the final regulation voltage. cycles) plus 2048 clock cycles, then it begins a new soft-start.
6.1 Low-side-less startup (LS-less)
manner, the dangerous negative spike on the output voltage is avoided. case, at the end of soft-start time, LS is enabled and discharges the output to the final regulation value. Figure 4. LS-less startup Figure 5. Non-LS-less startup
6.2 Enable/ disable
The device can be disabled externally by pushing COMP/DIS pin under 0.5 V (typ). In disable condition HS and LS MOSFETs are turned off, and a 0.1 mA current sources from COMP/DIS pin. Setting the pin, this current pulls it over the threshold and the device enables again performing a new SS. To disable the device, the external pull-down needs to overcome 10 mA of COMP output current for about 15 ms. Once disabled, COMP output current drops below 0.1 mA. Figure 6. Startup sequence; VCC = 5 V Figure 7. Overcurrent hiccup
7 Overcurrent protection
The overcurrent function protects the converter from a shorted output or overload, by sensing the output current information across the low-side MOSFET drain-source on- resistance, RDS(on).This method reduces costs and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low-side RDS(on) current sense is implemented by comparing the voltage at the PHASE node when LS MOSFET is turned on with the programmed OCP threshold voltage, internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an overcurrent event is detected. If two overcurrent events are detected in two consecutive switching cycles, the protection is triggered and the device turns off both LS and HS MOSFETs for 2048 clock cycles (plus internal SS remaining time, if triggered during an SS phase); then it begins a new soft-start. If the overcurrent condition is not removed, the continuous fault causes the A6727B to enter hiccup mode with a typical period of 13.6 ms Figure 6, assuring safe load protection and very low power dissipation.
7.1 Overcurrent threshold setting
When supplied with VCC = 5 V, the A6727B allows an overcurrent threshold ranging from 50 mV to 500 mV to be programmed, by adding a resistor (ROCSET) between COMP and VCC. During a short period of time (5.5 ms - 6.5 ms) following the first enable (given VCC over UVLO threshold), an internal 60 µA current (IOCSET) is sunk, determining a voltage drop across ROCSET.This voltage drop, differently sensed between VCC and COMP, divided by a factor 3, is sampled and internally held by the device as overcurrent threshold until next VCC cycling. Different sensing versus VCC allows the OCSET procedure to be fully independent from VIN rail. The OC setting procedure overall time length ranges from 5.5 ms to 6.5 ms, proportionally to the threshold. Connecting gan ROCSET resistor between COMP and VCC, the programmed threshold is: I OC t ℎ = 1 3 ⋅ I OC SE T ⋅ R OC SET R D S o n (3) ROCSET values range from 2.5 kΩ to 25 kΩ. ROCSET low values make the system sensitive to start-up in-rush current and noise.This may result in a continuous OCP triggering and hiccup mode. If ROCSET is not connected (and VCC = 5 V), the device sets the maximum threshold. If the device is supplied with a VCC higher than 7 V, ROCSET cannot be connected. In this case, as soon as VCC rises over VCC_OC (8V typ.), the A6727B switches OC threshold to 400 mV (internally fixed value). See Figure 6 for OC threshold setting and soft-start oscilloscope sample waveforms. A6727B Overcurrent protection DS14159 - Rev 2 page 10/26
8 Output voltage monitor and protections
The A6727B monitors the voltage at FB pin and compares it to internal reference voltage in order to provide undervoltage and overvoltage protections.
8.1 Undervoltage protection
If the voltage at FB pin drops below UV threshold (0.6 V typ.), the device turns off both HS and LS MOSFETs, waits for 2048 clock cycles and then performs a new soft-start. If undervoltage condition is not removed, the device enters the hiccup mode with a typical period of 13.6 ms. UVP is active from the end of soft-start
8.2 Overvoltage protection
If the voltage at FB pin rises over OV threshold (1 V typ.), overvoltage protection turns off HS MOSFET and turns on LS MOSFET overriding PWM logic as long as overvoltage is detected. OVP is always active with top priority as soon as the overcurrent threshold setting phase has been completed
8.3 Feedback disconnection protection
In order to provide load protection even if FB pin is not connected, a 100 nA bias current is always sourced from this pin. If FB pin is not connected, this current permanently pulls up FB over OVP threshold: thus LS is latched on preventing output voltage from rising out of control
8.4 Undervoltage lock out
In order to avoid anomalous behaviors of the device when the supply voltage is too low to support its internal rails, UVLO is provided: the device starts up when VCC reaches UVLO upper threshold and shut downs when VCC drops below UVLO lower threshold A6727B Output voltage monitor and protections DS14159 - Rev 2 page 11/26
9 Application details
9.1 Output voltage selection
variations (excluding output resistor divider tolerance, when present).
9.2 Compensation network
The control loop showed in Figure 8 is a voltage mode control loop. The error amplifier is a voltage mode type. GND, can be neglected in control loop calculation). The converter transfer function is the small signal transfer function between the output of the EA and VOUT. the peak-to-peak oscillator voltage ΔVOSC. Figure 8. PWM control loop
To place the poles and zeroes of the compensation network, the following suggestions may be followed: a) Set the gain RF/RFB in order to get the desired closed loop regulator bandwidth according to the approximated formula (suggested values for RFB range from 2 kΩ to 5 kΩ): R F R F B = F 0 d b F L C ⋅ Δ V OSC V I N (7) b) Place FZ1 below FLC (typically 0.5 * FLC): C F = 1 π ⋅ R F ⋅ F L C c) Place FP1 at FESR: C P = C F 2 π ⋅ R F ⋅ C F ⋅ F E SR − 1 d) Place FZ2 at FLC and FP2 at half of the switching frequency: R S = R F B F SW 2 ⋅ F L C − 1 C S = 1 π ⋅ R S ⋅ F SW e) Check that compensation network gain is lower than open loop EA gain; f) Estimate phase margin obtained (it should be greater than 45°) and repeat, modifying parameters, if necessary.
9.3 Layout guidelines
The A6727B provides control functions and high-current integrated drivers to implement high-current step-down DC-DC converters. In this kind of application, a good layout is very important. When placing components, the power section is the first priority because the length of each connection and loop have to be reduced as minimum as possible. To minimize noise and voltage spikes (EMI and losses), power connections (highlighted in Figure 10) must be part of a power plane and realized by wide and thick copper traces: loop must be minimized. The critical components, such as the power MOSFETs, must be very close one to the other. The use of multi-layer printed circuit board is recommended. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC should be connected nearthe HS drain. Use a proper number of vias when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, the same high-current trace on more than one PCB layer reduces the parasitic resistance associated to that connection. The output bulk capacitors (COUT) have to be connected as close as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace. A6727B Layout guidelines DS14159 - Rev 2 page 14/26
10.1 Output inductor
The inductor value is defined by a compromise among the dynamic response, ripple, efficiency,cost and size. Usually, the inductance is calculated to maintain the inductor ripple current (ΔIL) between 20% and 30% of the maximum output current. Given the switching frequency (FSW), the input voltage (VIN), the output voltage (VOUT) and the desired ripple current (ΔIL), the inductance can be calculated as follows: L = V I N − V OU T F SW ⋅ Δ I L ⋅ V OU T V I N (8) Figure 12 shows the ripple current vs. the output voltage for different inductance, with VIN = 5 V and VIN = 12 V. Increasing the value of the inductance, the inductor ripple current (and output voltage ripple accordingly) reduces but, at the same time, the converter response time to load transients increases. Higher inductance means that the inductor needs more time to change its current from initial to final value. Until the inductor has finished its charging, the additional output current is supplied by the output capacitors. Minimizing the response time, the required output capacitance can be minimized. If the compensation network is designed with high bandwidth, during a load transient the device can saturate duty cycle (0% or 80%). When this condition is reached, the response time is limited only by the time required to charge the inductor. Figure 12. Inductor current ripple vs. output voltage
Application information
DS14159 - Rev 2 page 16/26
10.2 Output capacitors
Output capacitor choice depends on the output voltage ripple and the output voltage deviation during a load transient. During steady-state conditions, the output voltage ripple is influenced by both ESR and capacitive value of the output capacitors as follows: Δ V OU T _ E SR = Δ I L ⋅ E SR (9) Δ V OU T _ C = Δ I L ⋅ 1 8 ⋅ C O U T ⋅ F SW (10) Where ΔIL is the inductor current ripple. Since they are not in phase, the total ripple is lower than the sum of their modules. Both ESL and board parasitic inductance can contribute to the output ripple significantly. During a load variation, the output capacitors supply the load with the current or absorb the current in excess delivered by the inductor until converter reaction is completed. In fact, even if the controller reacts immediately to the load transient saturating the duty cycle to 80% or 0%, the current slew rate is limited by the inductance. The output voltage drop, based on ESR and capacitive charge/discharge and considering an ideal load-step, can be estimated as follows: Δ V OU T _ E SR = Δ I OU T ⋅ E SR (11) Δ V OU T _ C = L ⋅ Δ I O U T 2 2 ⋅ C OU T ⋅ Δ V L (12) Where ΔVL is the voltage applied to the inductor during the transient (VIN- VOUT for the load appliance or VOUT for the load removal). MLCC capacitors typically have low ESR to minimize the ripple but also have low capacitance which doesn’t minimize the voltage deviation during the load transient. On contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive voltage deviation during the load transient, but also higher ESR value resulting in higher ripple voltage and resistive voltage drop. For these reasons, a mix between the electrolytic and MLCC capacitor is suggested so to minimize the ripple and reduce the voltage deviation in dynamic mode.
10.3 Input capacitors
The input capacitor bank is designed mainly to stand input RMS current, which depends on the output current (IOUT) and duty cycle (D) for the regulation as follows: I RMS = I OU T ⋅ D ⋅ 1 − D (13) The equation reaches its maximum value, IOUT/2, when D = 0.5 Losses depend on the input capacitor ESR: P = ES R ⋅ I R MS 2 (14) A6727B Output capacitors DS14159 - Rev 2 page 17/26
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
11.1 SO-8 package information
Figure 13. SO-8 package dimensions
Package information
DS14159 - Rev 2 page 18/26
Figure 14. SO-8 footprint Table 6. SO-8 mechanical data
Figure 15. SO-8 tape and reel package dimensions Table 7. SO-8 tape and reel mechanical data
Table 8. Ordering information
Ordering information
DS14159 - Rev 2 page 21/26
Revision history
Table 9. Document revision history 19-Dec-2022 1 Initial release.
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