A6159M

STR-A6159M SANKEN | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 3.1 Derating Curves -------------------------------- -------------------------------- ------
• 3.2 MOSFET Safe Operating Area Curves -------------------------------- ----------
• 3.3 Ambient Temperature versus Power Dissipation, PD1 Curves --------------
• 3.4 Internal Frame Temperature versus Power Dissipation, PD2 Curves ------
• 3.5 Transient Thermal Resistance Curves -------------------------------- -----------
• 9.1 Startup Operation -------------------------------- -------------------------------- -
• 9.2 Undervoltage Lockout (UVLO) -------------------------------- -----------------
• 9.3 Constant Output Voltage Control -------------------------------- --------------
• 9.4 Leading Edge Blanking Function -------------------------------- ---------------
• 9.5 Auto Standby Function -------------------------------- ---------------------------
• 9.6 Auto Bias Function (STR-A61××) -------------------------------- --------------
• 9.7 Overcurrent Protection Function (OCP) -------------------------------- ------
• 9.8 Overload Protection (OLP) -------------------------------- ----------------------
• 9.9 Overvoltage Protection (OVP) -------------------------------- ------------------
• 9.10 Thermal Shutdown Function (TSD) -------------------------------- ------------
• 10.1 External Components -------------------------------- -----------------------------
• 10.2 PCB Trace Layout and Component Placement ------------------------------

Features

 Current Mode Type Pulse Ratio Control  Auto Standby Function  No Load Power Consumption < 40mW  Leading Edge Blanking Function  Auto Bias Function  Protections Overcurrent Protection (OCP); pulse-by-pulse Overload Protection (OLP); auto-restart Overvoltage Protection (OVP); latched shutdown Thermal Shutdown Protection (TSD); latched shutdown Typical Application Circuit VAC C1 C5 R1 D2 R2 T1 D51 C51 R51 R52 R54 R56 C52 D P S PC1 PC1C4 ROCP BR1 R53 R55 L51 C53 VOUT GND 1 2 3 4 D D VCC NC S/OCP FB/OLPGND ST 8 7 5 STR-A6100 CYC3 DZ1 DST Package DIP8 Not to Scale Lineup  Electrical Characteristics Products Fixed off-time Auto bias function Startup resistance STR-A61×× 8 μs Yes − STR-A61××M 11.5 μs − − STR-A61××E 11.5 μs − Yes* * ST pin does not need Diode.  Power MOSFET Electrical Characteristics and output power, POUT (1) Products VDSS (min.) RDS(ON) (max.) POUT (Open frame) AC220V AC85 ~265V STR-A6132 500 V 2.62 Ω 16 W(2) 18 W(3) STR-A6131 3.95 Ω 13 W(2) 15 W(3) STR-A6131M STR-A6153E 650 V 1.9 Ω 22 W 18 W STR-A6151 3.95 Ω 15 W 13 W STR-A6151M STR-A6159 6 Ω 13 W 10 W STR-A6159M STR-A6169 800 V 19.2 Ω 8 W 5 W (1) The EI -16 core of transformer is assumed. The output power is based on the thermal ratings, and the peak output power can be 120 to 140 % of the value stated here. At low output voltage, small core and short ON Duty, the output power may be less than the value stated here. (2) AC100V (3) AC120V

Applications

 White goods  Auxiliary SMPS  Low power SMPS, etc. http://www.sanken-ele.co S/OCP VCC FB/OLP ST D D GND

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 3 Dec. 25, 2013 1. Absolute Maximum Ratings  The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.  Unless otherwise specified, TA is 25 °C, 7 pin = 8 pin Parameter Symbol Test Conditions Pins Rating Units Notes Drain Peak Current (1) IDPEAK Single pulse 8 – 1 3.2 A A6131/31M

4.0 A6132

2.5 A6151/51M

3.4 A6153E

1.8 A6159/59M

1.2 A6169

(2) IDMAX (3) 8 – 1 3.2 A A6131/31M (4) (5) EAS ILPEAK = 2.1 A 8 – 1 mJ A6131/31M ILPEAK = 2.6 A 78 A6132 ILPEAK = 2.5 A 72 A6151/51M ILPEAK = 3.4 A 136 A6153E ILPEAK = 1.8 A 24 A6159/59M ILPEAK = 1.2 A 7 A6169 S/OCP Pin Voltage VOCP 1 – 3 − 0.5 to 6 V VCC Pin Voltage VCC 2 – 3 35 V FB/OLP Pin Voltage VFB/OLP 4 – 3 − 0.5 to 10 V ST Pin Voltage VST 5 − 3 − 0.3 to 600 V MOSFET Power Dissipation (6) PD1 (7) 8 – 1 1.35 W Control Part Power Dissipation (8) PD2 VCC × ICC 2 – 3 0.15 W A61×× A61××M

0.46 A6153E

operation TF − 20 to 125 °C Recommended operation temperature TF = 115 °C (max.) Operating Ambient Temperature TOP ― − 20 to 125 °C Storage Temperature Tstg ― − 40 to 125 °C Junction Temperature Tch ― 150 °C (1) Refer to Figure 3-1 SOA Temperature Derating Coefficient Curve (2) Maximum Switching Current is Drain current that is limited by the VGS(th) of internal MOSFET and the gate drive voltage of internal control IC setting. TA = −20 to 125 °C (4) Refer to Figure 3-2 Avalanche Energy Derating Coefficient Curve (5) Single pulse, VDD = 99 V, L = 20 mH (6) Refer to Section 3.3 Ta-PD1 curve (7) When embedding this hybrid IC onto the printed circuit board (cupper area in a 15 mm × 15 mm) (8) Refer to Section 3.4 Ta-PD2 curve

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 4 Dec. 25, 2013 2. Electrical Characteristics  The polarity value for current specifies a sink as "+," and a source as "−," referencing the IC.  Unless otherwise specified, TA = 25 °C, VCC = 20 V, 7 pin = 8 pin Parameter Symbol Test Conditions Pins Min. Typ. Max. Units Notes Power Supply Startup Operation Operation Start Voltage VCC(ON) 2 − 3 16 17.5 19.2 V Operation Stop Voltage (1) VCC(OFF) 2 − 3 9 10 11 V Circuit Current in Operation ICC(ON) 2 − 3 − − 4 mA Circuit Current in Non Operation ICC(OFF) VCC = 14 V 2 − 3 − − 50 µA Auto Bias Threshold Voltage (1) (2) VCC(BIAS) 2 − 3 9.6 10.6 11.6 V A61×× VCC(BIAS)－VCC(OFF) (2) − − 0.2 − − V A61×× Startup Current ISTARTUP VCC = 15 V 2 − 3 − 1230 − 790 − 340 µA ST Pin Leakage Current ISTART(leak) 5 − 3 − − 30 µA PRC Operation Maximum OFF Time tOFF(MAX) 8 − 3 7.3 8 8.7 µs A61×× 10.5 11.5 12.5 A61××M A6153E Standby Operation Burst Threshold Voltage VBURST 4 − 3 0.70 0.79 0.88 V A61×× 0.66 0.75 0.84 A61××M A6153E Protection Operation Leading Edge Blanking Time tBW − 200 320 480 ns OCP Threshold Voltage VOCP(TH) 1 − 3 0.69 0.77 0.86 V A61×× 0.96 1.13 1.28 A61××M A6153E OLP Threshold Voltage VOLP 4 − 3 6.5 7.2 7.9 V FB/OLP Pin Source Current in OLP Operation IOLP 4 − 3 −35 −26 −18 µA A61×× A6153E FB/OLP Pin Maximum Source Current IFB(MAX) 4 − 3 −388 −300 −227 µA A61×× A6153E VCC Pin OVP Threshold Voltage VCC(OVP) 2 − 3 28.7 31.2 34.1 V Latched Shutdown Keep Current ICC(H) 2 − 3 − − 200 μA Latched Shutdown Release Threshold Voltage VCC(La.OFF) 2 − 3 6.6 7.3 8.0 V Thermal Shutdown Operating Temperature Tj(TSD) − 135 − − °C (1) VCC(BIAS) > VCC(OFF) always. (2) STR-A61××M and STR-A6153E do not have the Auto Bias Threshold voltage because auto bias function is not included.

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 5 Dec. 25, 2013 Parameter Symbol Test Conditions Pins Min. Typ. Max. Units Notes MOSFET Drain-to-Source Breakdown Voltage VDSS ID = 300 μA 8 – 1 500 − − V A6131/31M A6132 650 − − A6151/51M A6159/59M A6153E 800 − − A6169 Drain Leakage Current IDSS VD = VDSS 8 – 1 − − 300 μA On Resistance RDS(ON) ID = 0.4 A 8 – 1 − − 1.9 Ω A6153E − − 2.62 A6132 − − 3.95 A6131/31M A6151/51M − − 6 A6159/59M − − 19.2 A6169 Switching Time tf VD = 10V 8 – 1 − − 250 ns Thermal Characteristics Thermal Resistance (3) θch-F − − − 52 °C/W (3) θch-F is thermal resistance between channel and frame. Frame temperature (TF) is measured at the base of pin 3. 3. Performance Curves

3.1 Derating Curves

Figure 3-1 SOA Temperature Derating Coefficient Curve Figure 3-2 Avalanche Energy Derating Coefficient Curve 100 0 25 50 75 100 125 150 Safe Operating Area Temperature Derating Coefficient (%) Channel Temperature, Tch (°C) 100 25 50 75 100 125 150 EAS Temperature Derating Coefficient (%) Channel Temperature, Tch (°C)

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 6 Dec. 25, 2013

3.2 MOSFET Safe Operating Area Curves

 When the IC is used, the safe operating area curve should be multiplied by the temperature derating coefficient derived from Figure 3-1.  The broken line in the safe operating area curve is the drain current curve limited by on-resistance.  Unless otherwise specified, TA = 25 °C, Single pulse  STR-A6131 / 31M  STR-A6132  STR-A6151 / 51M  STR-A6159 / 59M  STR-A6169  STR-A6153E 0.01 0.1 1 10 100 1000 Drain Current, ID (A) Drain-to-Source Voltage (V) 0.01 0.1 1 10 100 1000 Drain Current, ID (A) Drain-to-Source Voltage (V) 0.01 0.1 1 10 100 1000 Drain Current, ID (A) Drain-to-Source Voltage (V) 0.01 0.1 1 10 100 1000 Drain Current, ID (A) Drain-to-Source Voltage (V) 0.01 0.1 1 10 100 1000 Drain Current, ID (A) Drain-to-Source Voltage (V) 0.01 0.1 1 10 100 1000 Drain Current, ID (A) Drain-to-Source Voltage (V) 0.1ms 1ms 0.1ms 1ms 0.1ms 1ms 0.1ms 1ms 0.1ms 1ms 0.1ms 1ms

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 7 Dec. 25, 2013

3.3 Ambient Temperature versus Power Dissipation, PD1 Curves

3.4 Internal Frame Temperature versus Power Dissipation, PD2 Curves

 STR-A61××  STR-A61××M  STR-A6153E 0.2 0.4 0.6 0.8 1.2 1.4 1.6 0 25 50 75 100 125 150 Power Dissipation, PD1 (W) Ambient Temperature, TA (°C ) 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0 20 40 60 80 100 120 140 Power Dissipation, PD2 (W) Internal Frame Temperature, TF (°C) PD2 = 0.15 W 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 25 50 75 100 125 150 Power Dissipation, PD2 (W) Internal Frame Temperature, TF (°C) PD2 = 0.46 W

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 8 Dec. 25, 2013

3.5 Transient Thermal Resistance Curves

 STR-A6131 / 31M  STR-A6132  STR-A6151 / 51M  STR-A6159 / 59M 0.01 0.1 100 Transient Thermal Resistance θch-c (°C/W) Time (s) 0.01 0.1 Transient Thermal Resistance θch-c (°C/W) Time (s) 0.01 0.1 100 Transient Thermal Resistance θch-c (°C/W) Time (s) 0.01 0.1 Transient Thermal Resistance θch-c (°C/W) Time (s) 1µ 10µ 100µ 1m 10m 100m 1 10 1µ 10µ 100µ 1m 10m 100m 1µ 10µ 100µ 1m 10m 100m 1 10 1µ 10µ 100µ 1m 10m 100m

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 9 Dec. 25, 2013  STR-A6169  STR-A6153E 0.01 0.1 Transient Thermal Resistance θch-c (°C/W) Time (s) 0.001 0.01 0.1 Transient Thermal Resistance θch-c (°C/W) Time (s) 1µ 10µ 100µ 1m 10m 100m 1µ 10µ 100µ 1m 10m 100m

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 10 Dec. 25, 2013 4. Functional Block Diagram STR-A61×× STR-A61××M TSD OVP DelayLatch－ UVLO Internal Bias Drive OLPS Q R Bias Burst FB PWM Latch Discharge OCP － － MOS FET Power OFF Timer Buffer Blanking VCC ST 7,8 D S/OCP FB/OLP GND TSD OVP DelayLatch－ UVLO Internal Bias Drive OLPS Q R FB PWM Latch Discharge OCP MOS FET Power OFF Timer Buffer Blanking Burst ＋ VCC ST 7,8 D S/OCP FB/OLP GND

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 11 Dec. 25, 2013 STR-A6153E 5. Pin Configuration Definitions S/OCP VCC GND FB/OLP ST D D Pin Name Descriptions

1 S/OCP MOSFET source and input of overcurrent

protection (OCP) signal

2 VCC Power supply voltage input for control part and

input of overvoltage protection (OVP) signal

3 GND Ground

4 FB /OLP Input of constant voltage control signal and

input of over load protection (OLP) signal

5 ST Startup current input

6 − (Pin removed) D Power MOSFET drain TSD OVP DelayLatch－ UVLO Internal Bias Drive OLPS Q R FB PWM Latch Discharge OCP MOS FET Power OFF Timer Buffer Blanking Burst ＋ VCC ST 7,8 D S/OCP FB/OLP GND

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 13 Dec. 25, 2013 7. Package Outline  DIP8 (Type A)  DIP8 (Type B) 8. Marking Diagram STR-A6131/32/51/59/69/31M/59M/51E STR-A6151M Part Number S K Y M D Sanken Control Number Lot Number Y = Last Digit of Year (0-9) M = Month (1-9,O,N or D) D =Period of days (1 to 3) 1 : 1st to 10th 2 : 11th to 20th 3 : 21st to 31st Part Number S K Y M D M Sanken Control Number Lot Number Y = Last Digit of Year (0-9) M = Month (1-9,O,N or D) D =Period of days (1 to 3) 1 : 1st to 10th 2 : 11th to 20th 3 : 21st to 31st A 6 1 5 1 NOTES: 3) Dimension is in millimeters 4) Pb-free. Device composition compliant with the RoHS directive (A61×× / A6153E A6131M / A6159M) NOTES: 1) Dimension is in millimeters 2) Pb-free. Device composition compliant with the RoHS directive

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 14 Dec. 25, 2013 9. Operational Description  All of the parameter values used in these descriptions are typical values of STR-A6151, unless they are specified as minimum or maximum.  With regard to current direction, "+" indicates sink current (toward the IC) and " –" indicates source current (from the IC).

9.1 Startup Operation

Figure 9-1 shows the circuit around VCC pin. Figure 9-2 shows VCC pin voltage behavior during the startup period. VAC D2 R2 D P BR1 VCC GND ST VD DST Figure 9-1 VCC pin peripheral circuit IC starts operationVCC pin voltage VCC(ON) VCC(OFF) Startup failure Startup success Target operating voltage Time Increase with rising of output voltage Figure 9-2 VCC pin voltage during startup period The IC incorporates the startup circuit. The circuit is connected to ST pin. During the startup process, the constant current, I STARTUP = − 790 µA, charges C2 at VCC pin. When VCC pin voltage increases to VCC(ON) = 17.5 V, the IC starts the operation. Then circuit current increases and VCC pin voltage decreases. Since the Operation Stop Voltage V CC(OFF) = 10 V is low, the auxiliary winding voltage reaches to setting value before VCC pin voltage decreases to V CC(OFF). Thus control circuit continues the opera tion. The voltage from the auxiliary winding D in Figure 9-1 becomes a power source to the control circuit in operation. The approximate value of auxiliary winding voltage is about 15 V to 20 V, taking account of the winding turns of D winding so that VCC pin voltage becomes Equation (2) within the specification of input and output voltage variation of power supply. .)(minVV.)(maxV )OVP(CCCC)BIAS(CC  The startup time of IC is determined by C2 capacitor value. The approximate startup time tSTART is calculated as follows: STRATUP )INT(CC)ON(CC START I VV×C2t － (2) where, tSTART : Startup time of IC (s) VCC(INT) : Initial voltage on VCC pin (V)

9.2 Undervoltage Lockout (UVLO)

Figure 9-3 shows the relationship of VCC pin voltage and circuit current ICC. When VCC p in voltage increases to V CC(ON) = 17.5 V, the control circuit starts switching operation and the circuit current ICC increases. When VCC pin voltage decreases to V CC(OFF) = 10 V, the control circuit stops operation by UVLO (Undervoltage Lockout) circuit, and reverts to the state before startup. Circuit current, ICC ICC（ON） VCC（OFF） VCC（ON） VCC pin voltage StartStop Figure 9-3 Relationship between VCC pin voltage and ICC

9.3 Constant Output Voltage Control

Figure 9-4 shows FB/OLP pin peripheral circuit, Figure 9-5 shows the waveform of I D and FB comparator input. The IC achieves the constant voltage control of the power supply output by PRC (Pulse Ratio Control). PRC

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 15 Dec. 25, 2013 controls on-time with fixed off -time. In addition, the IC uses the peak -current-mode control method, which enhances the response speed and provides the stable operation. Timer reset OFF signal output ON/OFF FB Comp. OCP Comp. Buffer VSC VOCPM VOCP(TH) S/OCP ID Gate controlS R Q PRC latch circuit Drive D OFF Timer Circuit FB/OLP PC1C3 IFB DZ1 GND 7,8 ROCP VROCP Figure 9-4 FB/OLP pin peripheral circuit VSC FB comparator Drain current, ID VOCPM Figure 9-5 The waveform of ID and FB comparator input The internal fixed off -time, tOFF is made from internal off timer circuit, the turn -on timing of power MOSFET depends on tOFF.  Turn-on After the period of t OFF, OFF signal output becomes High, Q of PRC latch circuit is latched to Low. As a result, turn-on signal is input to the gate control circuit, and power MOSFET turns on.  Tuen-off When the OCP comparator or the FB comparator resets the PRC latch circuit, Q of PRC latch circuit is latched to High. As a result, turn -off signal is input to the gate control circuit, and power MOSFET turns off. The IC controls the peak value of VOCPM voltage to be close to target voltage (V SC), comparing VOCPM with VSC by internal FB comparator. VOCPM is amplified V ROCP voltage that is a detection voltage by current detection resistor, ROCP.  Light load conditions When load conditions become lighter, the output voltage, V OUT, increases. Thus, the feedback current from the error amplifier on the secondary -side also increases. The feedback current is sunk at the FB/OLP pin, transferred through a photo -coupler, PC1, and the FB/OLP pin voltage decreases. Thus, V SC decreases, and the peak value of VOCPM is controlled to be low, and the peak drain current of ID decreases. This control prevents the output voltage f rom increasing.  Heavy load conditions When load conditions become greater, the IC performs the inverse operation to that described above. Thus, V SC increases and the peak drain current of I D increases. This control prevents the output voltage from decreasing.

9.4 Leading Edge Blanking Function

The constant voltage control of output of the IC uses the peak-current-mode control method. In peak-current-mode control method, there is a case that the power MOSFET turns off due to unexpected response of FB comparator or overcurrent protection circuit (OCP) to the steep surge current in turning on a power MOSFET. In order to prevent this operation, Leading Edge Blanking Time, tBW = 320 ns is built-in. In the period of t BW, the IC does not respond to the surge voltage in turning on the power MOSFET.

9.5 Auto Standby Function

Automatic standby mode is activated automatically when the drain current, I D, reduces under light load conditions, at which ID is less than 25% of the maximum drain current (it is in the Overcurrent Protection state). The operation mode becomes burst oscillation, as shown in Figure 9-6. The 25% of the maximum drain current corresponds to the Burst Threshold Voltage of FB/OLP pin, VBURST = 0.79 V ( 0.75 V for STR-A61××M and STR-A6153E). Burst oscillation mode reduces switching losses and improves power supply efficiency because of periodic non-switching intervals. Generally, to improve efficiency under light load conditions, the frequency of the burst mode becomes

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 16 Dec. 25, 2013 just a few kilohertz. Because the IC suppresses the peak drain current well during burst mode, audible noises can be reduced. Normal operation Standby operation Normal operation Burst oscillationOutput current, IOUT Drain current, ID Below several kHz Figure 9-6 Auto Standby mode timing

9.6 Auto Bias Function (STR-A61××)

STR-A61×× includes the auto bias function. The function becomes active during burst oscillation mode. When VCC pin voltage decreases to the Auto Bias Threshold Voltage, V CC(BIAS) = 10.6 V, during burst oscillation mode, the IC shift s to PRC operation so th at VCC pin voltage does not decrease. As a result, the IC achieves stable standby operation. However, if the Bias Assist function is always activated during steady -state operation including standby mode, the power loss increases. Therefore, the VCC pin vol tage should be more than V CC(BIAS), for example, by adjusting the turns ratio of the auxiliary winding and secondary winding and/or reducing the value of R2 in Figure 10-2 (refer to Section 10.1 Peripheral Components for a detail of R2).

9.7 Overcurrent Protection Function (OCP)

Overcurrent Protection Function (OCP) detects each drain peak current level of a power MOSFET on pulse-by-pulse basis, and limits the output power when the current level reaches to OCP threshold voltage, VOCP(TH) = 0.77 V ( 1.13 V for STR-A61××M and STR-A6153E). Figure 9-7 shows the output characteristics. When OCP becomes active, the output voltage decreases and the auxiliary winding voltage, V D decreases in proportion to the output voltage. When VCC pin volta ge decreases to V CC(OFF) = 10 V, the control circuit stops operation by UVLO circuit, and reverts to the state before startup. After that, VCC pin voltage is increased by Startup Current, I STARTUP. When VCC pin voltage increases to V CC(ON) = 17.5 V, the IC restarts the operation. Thus the intermittent operation by UVLO is repeated in OCP operation. The IC usually has some propagation delay time. The steeper the slope of the actual drain current at a high AC input voltage is, the larger the actual peak of drain current is. As a result, the detection voltage becomes higher than VOCP(TH). Thus, the output current depend s on the AC input voltage in OCP operation (refer to Figure 9-7). Output voltage, VOUT（V） Output current, IOUT（A） High AC input voltageLow AC input voltage Figure 9-7 Output characteristic curve When the multi outputs transformer is used, there is the case that the auxiliary winding voltage, V D does not decrease and the intermittent operation is not started , even if output voltage decreases in OCP operation. This is due to the poor coupling of transformer. In this case, the overload protection (OLP) becomes active. (refer to Section 9.8.)

9.8 Overload Protection (OLP)

Figure 9-8 shows the FB/OLP pin peripheral circuit. Figure 9-9 shows the OLP operational waveforms. When the peak drain current of I D is limited by OCP operation, the output voltage, V OUT, decreases and the feedback current from the secondary photo -coupler becomes zero. Thus, the feedback current, I FB, charges C3 connected to the FB/OLP pin and the FB/OLP pin voltage increases. When the FB/OLP pin voltage increases to VFB(OLP) = 7.2 V or more for the OLP delay time, tDLY or more, the OLP function is activated and the IC stops switching operation. tDLY is calculated using Equation (3). OLP FZOLP DLY I )VVV(×3Ct －－ (3) there, tDLY: OLP delay time VZ: zener voltage of zener diode, DZ1 VF: forward voltage of D3 IOLP: FB/OLP Pin Source Current in OLP Operation is − 26 µA After the switching operation stops, VCC pin voltage decreases to Operation Stop Voltage VCC(OFF) = 10 V and the intermittent operation by UVLO is repeated. This intermittent operation reduces the stress of parts such as power MOSFET and second ary side rectifier

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 17 Dec. 25, 2013 diode. In addition, this operation reduces power consumption because the switching period in this intermittent operation is short compared with oscillation stop period. When the abnormal condition is removed, the IC returns to normal operation automatically. As shown in Figure 9-9, tDLY should be longer than tSTART which is the period until the output voltage becomes constant . If t DLY is shorter than t START, the power supply may not start due to OLP operation. PC1 ROCP 1 3 4 S/OCP FB/OLPGND IFBVROCP DZ1 Figure 9-8 FB/OLP pin peripheral circuit VCC pin voltage FB/OLP pin voltage Drain current, ID VCC(OFF) VOLP tDLY VCC(ON) Non-switching interval tSTART tSTART tDLY Figure 9-9 OLP operational waveforms

9.9 Overvoltage Protection (OVP)

Figure 9-10 shows the OVP operational waveforms. When a voltage between VCC pin and GND terminal increases to VCC(OVP) = 31.2 V or more, OVP function is activated. When the OVP function is activated, the IC stops switching operation at the latched state. After that, VCC pin voltage is decreased by circuit current of IC. When VCC pin voltage becomes VCC(OFF) = 10 V or less, VCC pin voltage is increased by Startup Current. When VCC pin voltage increases to VCC(ON) = 17.5 V, the circuit current increases and VCC pin voltage decrease s. In this way, VCC pin voltage goes up and down between VCC(OFF) and VCC(ON) during the latched state, excessive increase of VCC pin voltage is prevented. Releasing the latched s tate is done by turning off the input voltage and by dropping the VCC pin voltage below VCC(La.OFF) = 7.3 V. VCC pin voltage VCC（ON）=17.5V VCC（OFF）=10V VCC（OVP）=31.2V Drain current, ID Latched state Figure 9-10 OVP operational waveforms If output voltag e detection circuit becomes open, the output voltage of secondary side increases. In case the VCC pin voltage is provided by using auxiliary winding of transformer, the overvoltage conditions can be detected because the VCC pin voltage is proportional to output voltage. The approximate value of output voltage VOUT(OVP) in OVP condition is calculated by using Equation (4). 2.31×V VV )NORMAL(CC )NORMAL(OUT OUT(OVP)  (4) where, VOUT(NORMAL): Output voltage in normal operation VCC(NORMAL): VCC pin voltage in normal operation

9.10 Thermal Shutdown Function (TSD)

When the temperature o f control circuit increases to Tj(TSD) = 135 °C or more, Thermal Shutdown function is activated. When the TSD function is activated, the IC stops switching operation at the latched state (see the Section 9.9). Releasing the latched state is done by turning off the input voltage and by dropping the VCC pin voltage below VCC(La.OFF) = 7.3 V.

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 18 Dec. 25, 2013 10.Design Notes

10.1 External Components

Take care to use properly rated, including derating as necessary and proper type of components. VAC C6 R1 BR1 D P PC1C3ROCP CRD clamp snubber C（RC） damper snubber 1 2 3 4 D D VCC NC S/OCP FB/OLPGND ST 8 7 5 DST DZ1 STRA6100 ( ) RST Figure 10-1 The IC peripheral circuit  Electrolytic Capacitor Apply proper derating to ripple current, voltage, and temperature rise. Use of high ripple current and low impedance types, designed for switch mode power supplies, is recommended.  S/OCP Pin Peripheral Circuit Choose a type of low internal inductance because a high frequency switching current flo ws to R OCP in Figure 10-1, and of properly allowable dissipation.  VCC Pin Peripheral Circuit The value of C2 in Figure 10-1 is generally recommended to be 10µ to 47μF (refer to Section 9.1, because the startup time is determined by the value of C2). In actual power supply circuits, there are cases in which the VCC pin voltage fluctuates in proportion to the output current, I OUT (see Figure 10-2), and the Overvoltage Protection function (OVP) on the VCC pin may be activated. This happens because C2 is charged to a peak voltage on the auxiliary winding D, which is caused by the transient surge voltage couple d from the primary winding when the power MOSFET turns off. For alleviating C2 peak charging, it is effective to add some value R2, of several tenths of ohms to several ohms, in series with D2 (see Figure 10-1). The optimal value of R2 should be determined using a transformer matching what will be used in the actual application, because the vari ation of the auxiliary winding voltage is affected by the transformer structural design. Without R2 With R2 VCC pin voltage Output current, IOUT Figure 10-2 Variation of VCC pin voltage and power  FB/OLP Pin Peripheral Circuit Figure 10-1 performs high frequency noise rejection and phase compensation, and should be connected close to these pins. The value of C3 is recommended to be about 2200p to 0.01µF. In order to make the v alue of C3 low and make the output response fast, DZ1 and C4 are connected. DZ1 prevents C4 charg ing in normal operation. The zener voltage of DZ1, V Z should be set higher than FB/OLP pin voltage in normal operation. Usually, the value of VZ is about 4.7 V to 5.6 V. C4 is for OLP delay time, tDLY setting. If C4 is too small, the power supply may not start due to OLP operation (see Section 9.8). The value of C4 is about 4.7 μF to 22 μF. C3, C4 and DZ1 should be selected based on actual operation in the application.  ST Pin Peripheral Circuit When STR -A61×× and STR -A61××M are used, D ST or R ST should be connected to S T pin as shown in Figure 10-1. D ST and R ST prevent negative voltage from applying to S T pin. If S T pin voltage becomes under −0.3 V, the power supply may not start. The value of D ST and R ST should be selected based on actual operation in the application. Recommended value of RST is 33 kΩ, Recommended characteristics of DST is as follows: Characteristics Recommended range Peak Reverse Voltage, VRM > 35 V Forward current, IF > 1.5 mA Reverse Recovery Time, trr < 27 μs Reverse Leakage Current, IR < 100 μA  Snubber Circuit In case the serge voltage of V DS is large, the circuit should be added as follows (see Figure 10-1); ・ A clamp snubber circuit of a capacitor -resistor- diode (CRD) combination should be added on the primary winding P. ・ A damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the D pin and the GND pin. In case the damper snubber circuit is added, this components should be connected near D pin and S/OCP pin.

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 19 Dec. 25, 2013  Phase Compensation A typical phase compensation circuit with a secondary shunt regulator (U51) is shown in Figure 10-3. C52 and R53 are for phase compensation. The value of C52 and R53 are recommended to be around 0.047 μF to 0.47 μF and 4.7 kΩ to 470 kΩ, respectively. They should be selected based on actual operation in the application. D51 C51 R51 R52 U51 R54 R56 C52 S PC1 R53 R55 L51 C53 VOUT GND Figure 10-3 Peripheral circuit around secondary shunt regulator (U51)  Transformer Apply proper design margin to core temperature rise by core loss and copper loss. Because the switching currents contain high frequency currents, the skin effect may become a consideration. Choose a suitable wire gauge in consideration of the RMS current and a current density of about 3 to 4A/mm2. If measures to further reduce temperature are still necessary, the following should be considered to increase the total surface area of the wiring: ▫ Increase the number of wires in parallel. ▫ Use litz wires. ▫ Thicken the wire gauge. Fluctuation of the VCC pin voltage by I OUT worsens in the following cases, requiring a transformer designer to pay close attention to the placement of the auxiliary winding D: ▫ Poor coupling between the primary and secondary windings (this causes high surge voltage and is seen in a design with low output voltage and high output current) ▫ Poor coupling between the auxiliary winding D and the secondary stabilized output winding where the output line voltage is controlled constant by the output voltage feedback (this is susceptible to surge voltage) In order to reduce the influence of surge voltage on the VCC pin, Figure 10-4 shows winding structural examples that are considered the placement of the auxiliary winding D. ▫ Winding structural example (a) : Separating the auxiliary winding D from the primary windings P 1 and P2. where: P1 and P2 are windings divided the primary winding into two. ▫ Winding structural example (b) : Placing the auxiliary winding D within the secondary -side stabilized output winding, S1, in order to improve the coupling of those windings. where: S1 is a stabilized output winding of secondary-side windings, controlled to constant voltage. Margin tape Margin tape Margin tape Margin tape P1 S1 P2 S2 D P1 S1 D S2 S1 P2 Winding structural example (a) Winding structural example (b) P1、P2 ：Primary main winding D ：Primary auxiliary winding S1 ：Secondary Stabilized output winding S2 ：Secondary output winding Bobbin Bobbin Figure 10-4 Winding structural examples

10.2 PCB Trace Layout and Component

Since the PCB circuit trace design and the component layout significantly affects operation, EMI noise, and power dissipation, the high frequency PCB trace should be low impedance with small loop and wide trace. In addition, the ground traces affect radiated EMI noise, and wide, short traces should be taken into account. Figure 10-5 shows the circuit design example. (1) Main Circuit Trace Layout: S/OCP pin to ROCP to C1 to T1 (winding P) to D pin This is the main trace containing switching currents, and thus it should be as wide trace and sm all loop as possible. If C1 and the IC are distant from each other, placing a capacitor such as film capacitor (about 0.1 μF and with proper voltage rating) close to the transformer or the IC is recommended to reduce impedance of the high frequency current loop.

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 20 Dec. 25, 2013 (2) Control Ground Trace Layout Since the operation of IC may be affected from the large current of the main trace that flows in control ground trace, the control ground trace should be separated from main trace and connected at a singl e point grounding of point A in Figure 10-5 as close to the ROCP pin as possible. (3) VCC Trace Layout: GND pin to C2 (negative) to T1 (winding D) to R2 to D2 to C2 (positive) to VCC pin This is the trace for supplying power to the IC, and thus it should be as small loop as possible. If C2 and the IC are distant from each other, placing a capacitor such as film capacitor C f (about 0.1 μF to 1.0 μF) close to the VCC pin and the GND pin is recommended. (4) ROCP Trace Layout ROCP should be placed as close as possible to the S/OCP pin. The connection between the power ground of the main trace and the IC ground should be at a single point ground (point A in Figure 10-5) which is close to the base of ROCP. (5) FB/OLP Trace Layout The components connected to FB/OLP pin should be as close to FB /OLP pin as possible. The trace between the components and FB/OLP pin should be as short as possible. (6) Secondary Rectifier Smoothing Circuit Trace Layout: T1 (winding S) to D51 to C51 This is the trace of the rectifier smoothing loop, carrying the switching current, and thus it should be as wide trace and small loop as possible. If this trace is thin and long, inductance resulting from the loop may increase surge voltage at turning off the power MOSFET. Proper rectifier smoothing trace layout helps to increase margin against the power MOSFET breakdown voltage, and reduces stress on the clamp snubber circuit and losses in it. (7) Thermal Considerations Because the power MOSFET has a positive thermal coefficient of RDS(ON), consider it in thermal design. Since the copper area under the IC and the D pin trace act as a heatsink, its traces should be as wide as possible. C1 C6 R1 D2 R2 C51 D P S PC1 ROCP 1 2 3 4 D D VCC NC S/OCP FB/OLPGND ST 8 7 5 STR-A6100 A DST DZ1 CY D51 (1) Main trace should be wide trace and small loop (6) Main trace of secondary side should be wide trace and small loop (7)Trace of D pin should be wide for heat release (2) Control GND trace should be connected at a single point as close to the ROCP as possible (3) Loop of the power supply should be small (4)ROCP should be as close to S/OCP pin as possible. (5)The components connected to FB/OLP pin should be as close to FB/OLP pin as possible Figure 10-5 Example of peripheral circuit around the IC

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 22 Dec. 25, 2013 12.Reference Design of Power Supply As an example, the following show the power supply specification, the circuit schematic, the bill of materials, and the transformer specification.  Power supply specification IC STR-A6159 Input voltage AC 85 V to AC 265 V Maximum output power 5 W Output 5 V / 1 A  Circuit schematic Refer to Figure 11-2  Bill of materials Symbol Part type Ratings(1) Recommended Sanken Parts Symbol Part type Ratings(1) Recommended Sanken Parts F1 Fuse AC 250 V, 500 mA R6 General, chip 10 Ω, 1/4 W L1 (2) CM inductor 16.5 mH R9 (2) General, chip 0 Ω, 1/4 W ZNR1 (2) Varistor Open R91 Metal oxide, chip 270 kΩ, 1/4 W D1 General 600 V, 1 A AM01A (Axial) R92 Metal oxide, chip 270 kΩ, 1/4 W D2 Fast recovery 200 V, 1 A AL01Z R93 Metal oxide, chip 270 kΩ, 1/4 W D3 Zener, chip 5.1 V PC1 Photo-coupler PC123 or equiv D4 General, chip 200 V, 1 A IC1 IC － STR-A6159 D91 Fast recovery 1000 V, 0.2 A EG01C T1 Transformer See the specification C1 (2) Film 0.15 μF, 270 V L2 (2) Inductor 2.2 μF C2 Electrolytic 22 μF, 450 V D11 Schottky, chip 60 V, 2 A SJPB-H6 C3 Ceramic, chip 4700 pF, 50 V C11 Electrolytic 680 μF, 10 V C4 Electrolytic 22 μF, 50 V C12 Electrolytic 220 μF, 10 V C5 Electrolytic 2.2 μF, 50 V C13 Ceramic, chip 0.1 μF, 50 V C8 (2) Ceramic, chip 0.33 μF, 50 V C14 (2) Ceramic, chip Open C91 Ceramic, chip 1000 pF, 630 V R11 General, chip 220 Ω, 1/8 W C99 (2) Ceramic, Y1 2200 μF, AC 250 V R12 General, chip 1.5 kΩ, 1/8 W R1 (2) General, chip Open R13 (2) General, chip, 1% 0 Ω, 1/8 W R2 (2) General, chip Open R14 General, chip, 1% 10 kΩ, 1/8 W R3 General, chip 10 Ω, 1/4 W R15 General, chip, 1% 10 kΩ, 1/8 W R4 General, chip 10 Ω, 1/4 W R16 General, chip 47kΩ, 1/8 W R5 General, chip 10 Ω, 1/4 W IC2 Shunt regulator VREF = 2.5 V TL431 or equiv (1) Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less. (2) It is necessary to be adjusted based on actual operation in the application. (3) Resistors applied high DC voltage and of high resistance are re commended to select resistors designed against electromigration or use combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application.

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 23 Dec. 25, 2013  Transformer specification ▫ Primary inductance, LP : 3.1 mH ▫ Core size : EI-16 ▫ Al-value : 114 nH/N2 (Center gap of about 0.188 mm) ▫ Winding specification Winding Symbol Number of turns (T) Wire diameter (mm) Construction Primary winding P1 66 φ 0.18 UEW Double-layer, solenoid winding Primary winding P2 99 φ 0.18 UEW Triple-layer, solenoid winding Auxiliary winding D 29 φ 0.18 UEW Solenoid winding Output S1 11 φ 0.4 × 3 TIW Solenoid winding VOUT(+) VOUT(-) Bobbin D S1P1 VDC D VCC GND D : Start at this pinCross-section view

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 24 Dec. 25, 2013 OPERATING PRECAUTIONS In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the load from each rated v alue or surge voltage or noise is considered for derating in order to assure or improve the reliability. In general, derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these stresses, instantaneous values, maximum values and minimum values must be taken into consideration. In addition, it should be noted that s ince power devices or IC’s including power devices have large self-heating value, the degree of derating of junction temperature affects the reliability significantly. Because reliability can be affected adversely by improper storage environments and hand ling methods, please observe the following cautions. Cautions for Storage  Ensure that storage conditions comply with the standard temperature (5 to 35°C) and the standard relative humidity (around 40 to 75%); avoid storage locations that experience extreme changes in temperature or humidity.  Avoid locations where dust or harmful gases are present and avoid direct sunlight.  Reinspect for rust on leads and solderability of the products that have been stored for a long time. Cautions for Testing and Handling When tests are carried out during inspection testing and other standard test periods, protect the products from power surges from the testing device, shorts between the product pins, and wrong connections. Ensure all test parameters are within the ratings specified by Sanken for the products. Remarks About Using Silicone Grease with a Heatsink  When silicone grease is used in mounting the products on a heatsink, it shall be applied evenly and thinly. If more silicone grease than required is applied, it may produce excess stress.  V olatile-type silicone greases may crack after long periods of time, resulting in reduced heat radiation effect. Silicone greases with low consistency (hard grease) may cause cracks in the mold resin when screwing the products to a heatsink. Our recommended silicone greases for heat radiation purposes, which will not cause any adverse effect on the product life, are indicated below: Type Suppliers G746 Shin-Etsu Chemical Co., Ltd. YG6260 Momentive Performance Materials Inc. SC102 Dow Corning Toray Co., Ltd. Soldering  When soldering the products, please be sure to minimize the working time, within the following limits:

• 260 ± 5 °C 10 ± 1 s (Flow, 2 times)
• 380 ± 10 °C 3.5 ± 0.5 s (Soldering iron, 1 time)  Soldering should be at a distance of at least 1.5 mm from the body of the products. Electrostatic Discharge  When handling the products, the operator must be grounded. Grounded wrist straps worn should have at least 1MΩ of resistance from the operator to ground to prevent shock hazard, and it should be placed near the operator.  Workbenches where the products are handled should be grounded and be provided with conductive table and floor mats.  When using measuring equipment such as a curve tracer, the equipment should be grounded.  When soldering the products, the head of soldering irons or the solder bath must be grounded in order to prevent leak voltages generated by them from being applied to the products.  The products should always be stored and transported in Sanken shipping contai ners or conductive containers, or be wrapped in aluminum foil.

STR-A6100 - DS Rev.2.0 SANKEN ELECTRIC CO.,LTD. 25 Dec. 25, 2013 IMPORTANT NOTES  The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the latest revision of the document before use.  Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the products herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual prop erty rights or any other rights of Sanken or any third party which may result from its use. Unless otherwise agreed in writing by Sanken, Sanken makes no warranties of any kind, whether express or implied, as to the products, including product merchantabil ity, and fitness for a particular purpose and special environment, and the information, including its accuracy, usefulness, and reliability, included in this document.  Although Sanken undertakes to enhance the quality and reliability of its products, the o ccurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device failure or malfunction.  Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equipment or apparatus (home appliances, office equi pment, telecommunication equipment, measuring equipment, etc.). When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and its control systems, traffic signal control systems or equip ment, fire/crime alarm systems, various safety devices, etc.), and whenever long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken sales representative to discuss, prior to the use of the products herein. The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required (aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited.  When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically or otherwise processing or treating the products, please duly consider all possible risks that may result from all such us es in advance and proceed therewith at your own responsibility.  Anti radioactive ray design is not considered for the products listed herein.  Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken’s distribution network.  The contents in this document must not be transcribed or copied without Sanken’s written consent.