A5191HRT ONSEMI | Alldatasheet
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Technical content
©2008 SCILLC. All rights reserved. Publication Order Number: May 2008 – Rev. 3 A5191HRT/D A5191HRT HART Modem
1.0 Key Features
- Can be used in designs presently using the SYM20C15
- Single-chip, half-duplex 1200 bits per second FSK modem
- Bell 202 shift frequencies of 1200Hz and 2200Hz
- 3.3V - 5.0V power supply
- Transmit-signal wave shaping
- Receive band-pass filter
- Low power: optimal for intr insically safe applications
- CMOS compatible
- Internal oscillator requires 460.8kHz crystal or ceramic resonator
- Meets HART physical layer requirements
- Industrial temperature range of -40°C to +85°C
- Available in 28-pin PLCC and 32-pin LQFP packages
2.0 Description
The A5191HRT is a single-chip, CMOS modem for use in high way addressable remote transducer (HART) field instruments and masters. The modem and a few external passive components provi de all of the functions needed to satisfy HART physical layer requirements including modulation, demodul ation, receive filtering, carrier detect, and transmit-signal shaping. The A5191HRT i s pin- compatible with the SYM20C15. See the Pin Description and Functio nal Description sections for details on pin compatibility with the SYM20C15. The A5191HRT uses phase continuous frequency shift keying (FSK) at 1200 bits per second. To conserve power the receive circuits are disabled during transmit operations and vice versa. This provides the half-duplex operation used in HART communications. Figure 1: 28-Pin PLCC Pin Out Diagrams (Green & Non-Green)
Figure 2: 32-Pin LQFP Pin Out Diagrams (Green & Non-Green) Table 1: Pin Out Summary 28-Pin PLCC, A5191HRTP/Pg (12197-504/508) Pin No. Signal Name Type Pin Description
1 TEST1 Input Connect to VSS
2 TEST2 - No connect
3 TEST3 - No connect
4 TEST4 - No connect
5 TEST5 Input Connect to VSS
6 INRESET Input Reset all digital logic when low
7 TEST7 Input Connect to VSS
8 TEST8 Input Connect to VSS
9 TEST9 Input Connect to VSS
10 OTXA Output Output transmit analog, FSK modulated HART transmit signal to 4-20mA loop interface circuit
11 IAREF Input Analog reference voltage
12 ICDREF Input Carrier detect reference voltage
13 OCBIAS Output Comparator bias current
14 TEST10 Input Connect to VSS
15 VDDA Power Analog supply voltage
16 IRXA Input FSK modulated HART receive signal from 4-20mA loop interface circuit
17 ORXAF Output Analog receive filter output
18 IRXAC Input Analog receive comparator input
19 OXTL Output Crystal oscillator output
20 IXTL Input Crystal oscillator input
21 VSS Ground Ground
22 VDD Power Digital supply voltage
23 INRTS Input Request to send
24 ITXD Input Input transmit date, transmitted HART data stream from UART
25 TEST11 - No connect
26 ORXD Output Received demodulated HART data to UART
27 OCD Output Carrier detect output
28 TEST12 - No connect
Rev. 3 | Page 2 of 13 | www.onsemi.com
Table 2: Pin Out Summary 32-Pin LQFP, A5191HRTl/Lg (12197-503/507) Pin No. Signal Name Type Pin Description
1 TEST5 Input Connect to VSS
2 INRESET Input Reset all logic when low, connect to VDD for normal operation
3 TEST7 Input Connect to VSS
4 TEST8 Input Connect to VSS
5 TEST9 Input Connect to VSS
6 VSS Ground Digital ground
7 OTXA Output Output transmit analog, FSK modulated HART transmit signal to 4-20mA loop interface circuit
8 IAREF Input Analog reference voltage
9 ICDREF Input Carrier detect reference voltage
10 OCBIAS Output Comparator bias current
11 TEST10 Input Connect to VSS
12 VSSA Ground Analog ground
13 VDDA Power Analog supply voltage
14 IRXA Input FS modulated HART receive signal from 4-20mA loop interface circuit
15 ORXAF Output Analog receive filter input
16 IRXAC Input Analog receive comparator input
17 OXTL Output Crystal oscillator output
18 IXTL Input Crystal oscillator input
19 VSSA Ground Analog ground
20 VSS Ground Digital ground
21 VDD Power Digital supply voltage
22 INRTS Input Request to send
23 ITXD Input Input transmit data, transmit HART data stream from UART
24 TEST11 - No connect
25 ORXD Output Received demodulated HART data to UART
26 OCD Output Carrier detect output
27 TEST12 - No connect
28 TEST1 Input Connect to VSS
29 TEST2 - No connect
30 VDD Power Digital supply voltage
31 TEST3 - No connect
32 TEST4 - No connect
3.0 Pin Descriptions
Table 3: Pin Descriptions Symbol Pin Name Description IAREF Analog reference voltage Analog input sets the dc operating point of the operational amplifiers and comparators and is usually selected to split the dc potential between VDD and VSS. See Table 5. ICDREF Carrier detect reference voltage Analog input controls at which level the carrier detect (OCD) becomes active. This is determined by the dc voltage difference between ICDREF and IAREF. Selecting ICDREF - IAREF equal to 0.08 VDC will set the carrier detect to a nominal 100 mVp-p INRESET Reset digital logic When at logic low (V SS) this input holds all the digital logic in reset. During normal operation INRESET should be at V DD. INRESET should be held low for a minimum of 10nS after VDD = 2.5V as shown in Table 3. INRTS Request to send Active-low input selects the operation of the modulator. OTXA is enabled when this signal is low. This signal must be held high during power-up. IRXA Analog receive input Input accepts the 1200/2200Hz signals from the external filter. IRXAC Analog receive comparator input Positive input of the carrier detect comparator and the receiver filter comparator. ITXD Digital transmit input (CMOS) Input to the modulator accepts digital data in NRZ form. When ITXD is low, the modulator output frequency is 2200Hz. When ITXD is high, the modulator output frequency is 1200Hz. IXTL Oscillator input Input to the internal oscillator must be connected to a parallel mode 460.8kHz ceramic resonator when using the internal oscillator or grounded when using an external 460.8kHz clock signal. OCBIAS Comparator bias current The current through this output controls the operating parameters of the internal operational amplifiers and comparators. For normal operation, OCBIAS current is set to 2.54A. Rev. 3 | Page 3 of 13 | www.onsemi.com
OCD Carrier detect output Output goes high when a valid input is recognized on IRXA. If the received signal is greater than the threshold specified on I CDREF for four cycles of the IRXA signal, the valid input is recognized. ORXAF Analog receive filter output Signal is the square wave output of the receiver high-pass filter. ORXD Digital receive output (CMOS) Signal outputs the digital receive data. W hen the received signal (IRXA) is 1200Hz, ORXD outputs logic high. When the received signal (IRXA) is 2200Hz, ORXD outputs logic low. ORXD is qualified internally with OCD. OTXA Analog transmit output Output provides the trapezoidal signal controlled by ITXD. When ITXD is low, the output frequency is 2200Hz. When ITXD is high, the output frequency is 1200Hz. This output is active when INRTS is low and 0.5 VDC when INRTS is high. OXTL Oscillator output Output from the internal oscillator must be connected to an external 460.8kHz clock signal or to a parallel mode 460.8kHz ceramic resonator when using the internal oscillator. TEST(12:1) Factory test Factory test pins; for normal operation, tie these signals as per Table 1 and Table 2 VDD Digital power Power for the digital modem circuitry VDDA Analog supply voltage Power for the analog modem circuitry VSS Ground Analog and digital ground VSSA Analog ground Figure 3: Reset Timing Note: This signal is also present on the LSI 20C15. It is labeled as Test6. The 20C15 data sheet mentions the reset function of this pin but does not emphasize its use to reset the chip. Reliable operation of the modem requires a hardware reset as shown in Figure 3. This is true for the AMIS 12197-503 and 12197-504 as well as the LSI 20C15.
4.0 Functional Description
The A5191HRT is a functional equivalent of the SYM20C15 HART Modem. It contains a tran smit data modulator and signal shaper, carrier detect circuitry, analog receiver and demodulator circuitry and an oscillator, as shown in Figure 4. Rev. 3 | Page 4 of 13 | www.onsemi.com
The internal HART modem modulates the transmit-signal and demodulates the receive signal. The transmit-signal shaper enables th e A5191HRT to transmit a HART compliant signal. The carrier is det ected by comparing the receiver filter output with the differen ce between two external voltage references. The analog receive circui try band-pass filters the received signal for input to the mo dem and the carrier detect circuitry. The oscillator provides the modem with a stable time base using either a simple external resonator or an external clock source. Figure 4: A5191HRT Block Diagram
4.1 A5191HRT Logic
The modem consists of a modulator and demodu lator. The modem uses shift frequencies of nominally 1200Hz (for a 1) and 220Hz (fo r a 0). The bit rate is 1200 bits/second. 4.1.1. Modulator The modulator accepts digital data in NRZ fo rm at the ITXD input and generates the FSK modulated signal at the OTXA output. INRTS must be a logic low for the modulator to be active. 4.1.2. Demodulator The demodulator accepts an FSK signal at t he IRXA input and reproduces the original modulating signal at the ORXD output. The nominal bit rate is 1200 bits per second. Figure 5 illustrates the demodulation process. Figure 5: Demodulator Signal Timing The output of the demodulator is qualified with the carrier detect signal (OCD), therefore, only IRXA signals large enough to be detected (100mVp-p typically) by the carrier detect circuit produce received serial data at ORXD. Maximum demodulator jitter is 12 percent of one bit given input frequencies within HART specifications, a clock frequency of 46 0.8kHz (±1.0 percent) and zero input (IRXA) asymmetry. Rev. 3 | Page 5 of 13 | www.onsemi.com
4.2 Transmit-Signal Shaper
The transmit-signal shaper generates a HART compliant FSK modulated signal at OTXA. Figure 6 and Figure 7 show the transmit- signal forms of the A5191HRT. For IAREF = 1.235 VDC, OTXA will have a voltage swing from approximately 0.25 to 0.75 VDC. Figure 6: OTXA Waveform (1200Hz) Figure 7: OTXA Waveform (2200Hz)
4.3 Carrier Detect Circuitry
The carrier detect comparator shown in Figure 8 generates logic lo w output if the IRXAC voltage is below ICDREF. The comparator output is fed into a carrier detect block (see Figure 4). The carrier detect block drives the carrier detect output pin OCD high if INRTS is high and four consecutive pulses out of the comparator have arri ved. OCD stays high as long as INRTS is high and the next comparator pulse is received in less than 2.5ms. Once OCD goes i nactive, it takes four consecutiv e pulses out of the comparator to Rev. 3 | Page 6 of 13 | www.onsemi.com
assert OCD again. Four consecut ive pulses amount to 3.33ms when the received si gnal is 1200Hz and to 1.82ms when the received signal is 2200HZ.
4.4 Analog Receiver Circuitry
4.4.1. Voltage References The A5191HRT requires two voltage references, IAREF and ICDREF. IAREF sets the dc operating point of the internal operational amplifiers and comparators. A 1.235 V DC reference (Analog Devices AD589) is suitable as IAREF. The level at which OCD (carrier detect) bec omes active is determined by the dc voltage difference (ICDREF - IAREF). Selecting a voltage difference of 0.08 V DC will set the carrier detect to a nominal 100 mVp-p. 4.4.2. Bias Current Resistor The A5191HRT requires a bias current resi stor to be connected between OCBIAS and V SS. The bias current controls the operating parameters of the internal operational amplifiers and comparators. The value of the bias current resistor is determined by the reference voltage IAREF and the following formula: The recommended bias current resistor is 500KW when IAREF is equal to 1.235 V DC. In Figure 8 all external capacitor values have a tolerance of ±5 perc ent and the resistors have a tolerance of ±1 percent, except the 3MW which has a tolerance of ±5 percent. External to the A5191HRT , the filter exhibits a three-po le, high-pass filter at 624Hz and a one-pole, low-pass filter at 2500Hz. Internally, the A5191HRT has a high-pass pole at 35Hz and a low-pass pole at 90kHz. The lo w- pass pole can vary as much as ±30 percent. The input impedance of the entire filter is greater than 150MW at frequencies below 50kHz. Figure 8: Receive Filter Schematic
4.5 Oscillator
The A5191HRT requires a 460.8kHz clock signal on OXTL. This can be provided by an external clock or external components may be connected to the A5191HRT internal oscillator. Rev. 3 | Page 7 of 13 | www.onsemi.com
5.0 Ordering Information
The A5191HRT is available in a 28-pin plastic leaded chip carr ier (PLCC) and 32-pin low-profile quad flat pack (LQFP). Use the following part number when ordering. Contact your local sales representative for more information: www.onsemi.com. Part Number Package Shipping Configuration Temperature Range A5191HRTLG-XTD 32-pin LQFP Green/RoHS compliant Tube/Tray -40°C to +85°C (Industrial) A5191HRTLG-XTP 32-pin LQFP Green/RoHS compliant Tape & Reel -40°C to +85°C (Industrial) A5191HRTPG-XTD 28-pin PLCC Green/RoHS compliant Tube/Tray -40°C to +85°C (Industrial) A5191HRTPG-XTP 28-pin PLCC Green/RoHS compliant Tape & Reel -40°C to +85°C (Industrial)
6.0 Electrical Specifications
Table 4: Absolute Maximums Symbol Parameter Min. Max. Units TA Ambient -40 +85 °C TS Storage temperature -55 150 °C VDD Supply voltage -0.3 6.0 V VIN, VOUT DC input, output -0.3 VDD + 0.3 V TL Re-flow solder profile Per IPC/JEDEC J-STD-020C °C Cautions: 1. CMOS devices are damaged by high-energy elec trostatic discharge. Devices must be stored in conductive foam or with all pins shunted. Precautions should be taken to avoid application of voltages higher than the maximum rating. Stresses above absolute maximum ratings may result in damage to the device. 2. Remove power before insertion or removal of this device. Table 5: DC Characteristics V DD = 3.0V to 5.5V, VSS = 0V TA = -40°C to +85°C Symbol Parameter VDD Min. Typ. Max. Units VIL Input voltage, low 3.0 – 5.5 0.3 * VDD V VIH Input voltage 3.0 – 5.5 0.7 * VDD V VOL Output voltage, low (IOL = 0.67mA) 3.0 – 5.5 0.4 V VOH Output voltage, high (IOH = -0.67mA) 3.0 – 5.5 2.4 V CIN Input capacitance Analog input IRXA Digital input 2.9 3.5 pF IIL/IH Input leakage current ± 500 nA IOLL Output leakage current ± 10 μA IDO Power supply current (RBIAS = 500kΩ, IAREF = 1.235V) 3.3 5.0 330 300 450 600 μA IAREF Analog reference 3.3 5.0 1.2 1.235 2.5 2.6 V ICDREF* Carrier detect reference (IAREF – 0.08V) 1.15 V OCBIAS Comparator bias current (RBIAS = 500 kΩ, IAREF = 1.235V) 2.5 μA *The HART specification requires carrier detect (OCD) to be active between 80 and 120 mV p-p. Setting ICDREF at IAREF - 0.08 VDC will set the carrier detect to a nominal 100 mVp-p. Rev. 3 | Page 9 of 13 | www.onsemi.com
Table 6: AC Characteristics VDD = 3.0V to 5.5V, VSS = 0V, TA = -40°C to +85°C Pin Name Description Min. Typ. Max. Units IRXA Receive analog input Leakage current Frequency – mark (logic 1) Frequency – space (logic 0) 1190 2180 1200 2200 ±150 1210 2220 nA Hz Hz ORXAF Output of the high-pass filter Slew rate Gain bandwidth (GBW) Voltage range 150 0.15 0.025 VDD – 0.15 V/μs kHz V/μs IRXAC Carrier detect and receive filter input Leakage current ±500 nA OTXA Modulator output Frequency – mark (logic 1) Frequency – mark (logic 0) Amplitude (IAREF 1.235V) Slope Loading (IAREF = 1.235V) 1196.9 2194.3 500 2.79 Hz Hz mVDD mV/μs kΩ ORXD Receive digital output Rise/fall time ns OCD Carrier detect output Rise/fall time ns The modular output frequencies are proportional to the input clock frequency (460.8kHz). Table 7: Modem Characteristics V DD = 3.0V to 5.5V, VSS = 0V, TA = -40°C to +85°C Parameter Min. Typ. Max. Units Demodulator jitter Conditions 1. Input frequencies at 1200Hz ±10Hz, 2200Hz ± 20Hz 2. Clock frequency of 460.8kHz ± 0.1% 3. Input (HLXA) asymmetry, 0 % of 1 bit Table 8: Ceramic Resonator - External Clock Specifications V DD = 3.0V to 5.5V, VSS = 0V, TA = -40°C to +85°C Parameter Min. Typ. Max. Units Resonator Tolerance Frequency 460.8 1.0 kHz External Clock frequency Duty cycle Amplitude 456.2 460.8 VOH - VOL 465.4 kHz V Rev. 3 | Page 10 of 13 | www.onsemi.com
7.0 Mechanical Specifications
Symbol Min. Nom. Max. A .165 .172 .180 A1 .099 .101 .110 D .485 .490 .495 D1 .450 .452 .495 D2 .390 .420 .430 D3 .300 REF E .485 .490 .495 E1 .450 .452 .455 E2 .390 .420 .430 E3 .300 REF e .050 BSC Figure 11: 28 Lead PLCC Rev. 3 | Page 11 of 13 | www.onsemi.com
Symbol Min. Nom. Max. A - - 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 D 9.00 BSC d/2 4.50 BSC D1 7.00 BSC E 9.00 BSC E/2 4.50 BSC E1 7.00 BSC L 0.45 0.60 0.75 e 0.80 BSC b 0.30 0.37 0.45 c 0.09 - 0.20 ccc - - 0.10 ddd - - 0.20 Figure 12: 32 Lead LQFP Rev. 3 | Page 12 of 13 | www.onsemi.com
Rev. 3 | Page 13 of 13 | www.onsemi.com A5191HRT
8.0 Revision History
Revision Date Modification
2 March 2005
3 May 2008 Update to new ON Semiconductor template
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