A3P3000L

A3P250L-VQ100I MICROSEMI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 242

Technical content

© 2013 Microsemi Corporation ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power

• Dramatic Reduction in Dynamic and Static Power Savings
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
• Low Power Consumption in Flash*Freeze Mode Allows for Instantaneous Entry to / Exit from Low-Power Flash*Freeze Mode
• Supports Single-Voltage System Operation
• Low-Impedance Switches High Capacity
• 250,000 to 3,000,000 System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off High Performance
• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System Performance
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit PCI (1.2 V systems) In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock ® to Secure FPGA Contents High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization Advanced and Pro (Professional) I/Os
• 700 Mbps DDR, LVDS-Capable I/Os
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II (A3PE3000L only)
• Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay (A3PE3000L only)
• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC ®3L Family (except PQ208) Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All with Integrated PLL (ProASIC3EL)
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V systems) and 350 MHz (1.5 V systems)) SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous Operation: – 250 MHz: For 1.2 V systems – 350 MHz: For 1.5 V systems ARM® Processor Support in ProASIC3L FPGAs
• ARM Cortex™-M1 Soft Processor Available with or without Debug Table 1 • ProASIC3 Lo w-Power Product Family ProASIC3L Devices A3P250L A3P600L A3P1000L A3PE3000L ARM Cortex-M1 Devices 1 M1A3P600L M1A3P1000L M1A3PE3000L System Gates 250,000 600,000 1,000,000 3,000,000 VersaTiles (D-flip-flops) 6,144 13,824 24,576 75,264 RAM Kbits (1,024 bits) 36 108 144 504 4,608-Bit Blocks 82 4 3 2 1 1 2 FlashROM Kbits 111 1 Secure (AES) ISP 2 Yes Yes Yes Yes Integrated PLL in CCCs 3 111 6 VersaNet Globals 18 18 18 18 I/O Banks 444 8 Maximum User I/Os 157 235 300 620 Package Pins VQFP PQFP FBGA VQ100 PQ208 FG144, FG256 PQ208 FG144, FG256, FG484 PQ208 FG144, FG256, FG484 PQ208 FG324, FG484, FG896 Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. AES is not available for ARM Cortex-M1 ProASIC3L devices. 3. For the A3PE3000L, the PQ208 pa ckage has six CCCs and two PLLs. Revision 13

ProASIC3L Low Power Flash FPGAs I/Os Per Package 1 ProASIC3L Low-Power Devices A3P250L 2 A3P600L A3P1000L A3PE3000L ARM Cortex-M1 Devices M1A3P600L M1A3P1000L M1A3PE3000L 3 Package I/O Type Single- Ended I/O 4 Differential I/O Pairs Single- Ended I/O 4 Differential I/O Pairs Single- Ended I/O 4 Differential I/O Pairs Single- Ended I/O 4 Differential I/O Pairs PQ208 151 34 154 35 154 35 147 65 F G 1 4 4 9 72 49 72 59 72 5 FG256 157 38 177 43 177 44 – – FG484 – – 235 60 300 74 341 168 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. 3. ARM Cortex-M1 support is TBD on this device. 4. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 5. FG256 and FG484 are footprint-compatible packages. 6. "G" indicates RoHS-compliant packages. Refer to "ProASIC3L Ordering Information" on page III for the location of the "G" in the part number. 7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2. 5 V: up to 72 I/Os per north or south bank 8. When the Flash*Freeze pin is used to directly enable Flash*Freez e mode and not as a regular I/O, the number of single-ended u ser I/Os available is reduced by one. Table 2 • ProASIC3L FPGAs Package Sizes Dimensions Length × Width (mm\\mm) 14 × 14 28 × 28 13 × 13 17 × 17 19 × 19 23 × 23 31 × 31 Nominal Area (mm2) 196 784 169 289 361 529 961

ProASIC3L Low Power Flash FPGAs Revision 13 III ProASIC3L Ordering Information Speed Grade Blank = Standard 1 = 15% Faster than Standard A3P1000L FG_ Part Number ProASIC3L Devices Package Type VQ = Very Thin Quad Flat Pack (0.5 mm pitch)

144 I Y

G Lead-Free Packaging Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature) I = Industrial ( –40°C to +85°C Ambient Temperature) Blank = Standard Packaging G= RoHS-Compliant (Green) Packaging 250,000 System GatesA3P250L = 600,000 System GatesA3P600L = 1,000,000 System GatesA3P1000L = 3,000,000 System GatesA3PE3000L= ProASIC3L Devices with Cortex-M1 600,000 System GatesM1A3P600L = 1,000,000 System GatesM1A3P1000L = 3,000,000 System GatesM1A3PE3000L = PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio

ProASIC3L Low Power Flash FPGAs Temperature Grade Offerings Speed Grade and Temperature Grade Matrix ProASIC3L Device Status Contact your local Microsemi SoC Products Group representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. Package A3P250L A3P600L A3P1000L A3PE3000L ARM Cortex-M1 Devices M1A3P600L M1A3P1000L M1A3PE3000L VQ100 C, I – – P Q 2 0 8 C , IC , IC , IC , I F G 1 4 4 C , IC , IC , I F G 2 5 6 C , IC , IC , I FG324 – – – C, I F G 4 8 4 – C , IC , IC , I FG896 – – – C, I Notes: 1. C = Commercial temperature range: 0°C to 70°C ambient temperature. 2. I = Industrial temperature range: –40°C to 85°C ambient temperature. Temperature Grade Std. –1 C 1 33 I 2 33 Notes: 1. C = Commercial temperature range: 0°C to 70°C ambient temperature. 2. I = Industrial temperature range: –40°C to 85°C ambient temperature. ProASIC3L Devices Status M1 ProASIC3L Devices Status A3P250L Production A3P600L Production M1A3P600L Production A3P1000L Production M1A3P1000L Production A3P3000L Production M1A3P3000L Production

ProASIC3L Low Power Flash FPGAs Revision 13 V Table of Contents ProASIC3L Device Family Overview ProASIC3L DC and Switching Characteristics Pin Descriptions and Packaging Package Pin Assignments Datasheet Information

1 – ProASIC3L Device Family Overview General Description The ProASIC3L family of Microsem i flash FPGAs dramatically reduc es dynamic power consumption by 40% and static power by 50% compared to the equivalent ProASIC3 device. These power savings are coupled with performance, density, true single-chip , 1.2 V to 1.5 V core and I/O operation as low as 1.2 V, reprogrammability, and advanced features. Using Microsemi's proven Flash*Freeze technolog y enables users to shut off dynamic power instantaneously and switch the device to static mode without the need to switch off clocks or power supplies while retaining internal states of the de vice. This greatly simplifies power management on a board done through I/Os and clocks. In addition, optimized soft ware tools using power-driven layout provide instant push-button power reduction. Nonvolatile flash technology gives ProASIC3L de vices the advantage of being a secure, low-power, single-chip solution that is Instant On. ProASIC3 L offers dramatic dynamic power savings giving the FPGA users flexibility to combine low power with high performance. These features e nable designers to create high -density systems using existing ASIC or FPGA design flows and tools. ProASIC3L devices offer 1 kbit of on-chip, reprogra mmable, nonvolatile FlashROM storage as well as clock conditioning circuitry (CCC) based on an integr ated phase-locked loop (PLL). ProASIC3L devices support devices from 250 k system gates to 3 million system gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os. M1 ProASIC3L devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. ARM Cortex-M1 is a so ft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and speed when implemented in an M1 ProASIC3L device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. ARM Cortex-M1 is available for free from Microsemi for use in M1 ProASIC3L FPGAs. The ARM-enabled devices have Microsemi SoC Produc ts Group ordering numbers that begin with M1 and do not support AES decryption. Flash*Freeze Technology The ProASIC3L devices offer Microsemi's proven Flash*Freeze technology, which allows instantaneous switching from an active state to a static state. ProASIC3L devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined wi th in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of ProASIC3L devices to support a wide range core voltage (1.2 V to 1.5 V) allows for an even greater reduction in power consumption, which enables low total system power. When the ProASIC3L device enters Flash*Freeze mode , the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined wit h a reprogrammable, single-chip, single-voltage solution, make ProASIC3L devices suitable for low-power data transfer and manipulation in portable media, secure communications, radio applications as well as high performance portable, industrial, test, scientific, and medical applications.

ProASIC3L Device Family Overview Flash Advantages Low Power The ProASIC3L family of Microsemi flash-bas ed FPGAs provide a low-power advantage, and when coupled with high performance, enables designers to make power-smart choices using a single-chip, reprogrammable, and Instant On device. ProASIC3L devices offer 40% dynamic power and 50% static power savings compared to the equivalent ProASIC3 device by reducing the core operating volt age to 1.2 V. In addition, the Power Driven Layout (PDL) feature in Libero ® System-on-Chip (SoC) offers up to 30% additional power reduction over the standard timing-driven place-and-route (TDPR). With Flash*Freeze technology, ProASIC3L devices are able to retain device SRAM and logic while dynamic power is reduced to a minimum, without the need to stop clock or power supplies. Combining these feat ures provides a low-power, feature-rich and high- performance solution. Security Nonvolatile, flash-based ProASIC3L devices do not require a boot PR OM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3L devices incorporate FlashLock, which provides a unique combination of reprogrammability and desi gn security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3L devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA indus try for programmed intellectual pr operty and configuration data. In addition, all FlashROM data in ProASIC3L devices can be encrypted prior to loading, using the industry- leading AES-128 (FIPS192) bit block cipher encryption standa rd. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3L devices have a built-in AES decrypti on engine and a flash-based AE S key that make them the most comprehensive programmable logic device security solution available today. ProASIC3L devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. Security, built into the FPGA fabric, is an inheren t component of the ProASI C3L family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The ProASIC3L family, with FlashLock and AES security, is unique in being highly resi stant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. A ProASIC3L device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration informati on in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3L FPGAs do not require system configurati on components such as EEPROMs or mi crocontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Instant On Flash-based ProASIC3L devices support Level 0 of th e Instant On classificati on standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock genera tion, and bus activity management. The Instant On feature of flash-based Pr oASIC3L devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In a ddition, glitches and brownouts in system power will not corrupt the Pr oASIC3L device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system pow er is restored. This enables the reduction or complete removal of t he configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3L devices simplify total system desig n and reduce cost and design risk while increasi ng system reliability and improving system initialization time.

ProASIC3L Low Power Flash FPGAs Revision 13 1-3 Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM- based FPGAs, flash-based ProASIC3L devices allow all functionality to be Instant On; no external boot PROM is required. On-boa rd security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry- standard AES algorithm. The ProASIC3L family de vice architecture mitigates the need for ASIC migration at higher user volumes. This makes t he ProASIC3L family a cost-effective ASIC replacement solution, manipulation in portable media and secure communications, radio applications as well as high performance portable Industrial, test, scientific and medical applications. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3L flash-based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3L FPGAs cannot be altered by high-energy neutrons and is therefore im mune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The ProASIC3L family offers many benefits, incl uding nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LV CMOS process with 7 layers of metal. Standard CMOS design techniques are used to implement logic and contro l functions. The combination of fine granularity, enhanced flexible routing resources, and abundant fl ash switches allows for very high logic utilization without compromising device routability or perform ance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary ProASIC3L architec ture provides granularity comparable to standard-cell ASICs. The ProASIC3L device consists of five distinct and programmable architectural features ( Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4):

• FPGA VersaTiles
• Dedicated FlashROM
• Dedicated SRAM/FIFO memory
• Extensive CCCs and PLLs
• I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by progr amming the appropriate flash switch interconnections. The versatility of the ProASIC3L core tile, as eith er a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC fa mily of third-generation- architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, re configurable interconnect programming. Maximum core utilization is possible for virtually any design.

ProASIC3L Device Family Overview User Nonvolatile FlashROM ProASIC3L devices have 1 kbit of on-chip, user-acce ssible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications:

• Internet Protocol addressing (wireless or fixed)
• System calibration settings
• Device serialization and/or inventory control
• Subscription-based business models (for example, set-top boxes)
• Secure key storage for secure communications algorithms
• Asset management/tracking
• Date stamping
• Version management The FlashROM is written using the standard Pr oASIC3L IEEE 1532 JTAG programming interface.The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG progr amming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits ; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address fr om the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The ProASIC3L development software solutions, Libero SoC and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Anothe r feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated qu ickly and easily using Libero SoC and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO ProASIC3L devices have embedded SRAM blocks along their north and south sides. Each variable- aspect-ratio SRAM block is 4,608 bits in size. Av ailable memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For ex ample, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM bl ocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FI FO control unit. The contro l unit allows the SRAM block to be configured as a synchronous FIFO with out using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also feat ures programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the norma l Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generati on of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC ProASIC3L devices provide designers with flexible clock conditioning circuit (CCC) capabilities. Each member of the ProASIC3L family contains six CCCs. One CCC (center west side) has a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. All six CCC blocks are usable; the four corner CCCs and the east CCC allo w simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block.

ProASIC3L Low Power Flash FPGAs Revision 13 1-7 The CCC block has these key features:

• Wide input frequency range (f IN_CCC) = 1.5 MHz up to 250 MHz
• Output frequency range (f OUT_CCC) = 0.75 MHz up to 250 MHz
• 2 programmable delay types for clock skew minimization
• Clock frequency synthesis Additional CCC specifications:
• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration.
• Output duty cycle = 50% ± 1.5% or better
• Low output jitter: worst case < 2.5% × clock per iod peak-to-peak period jitter when single global network used
• Maximum acquisition time is 300 µs
• Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns
• Four precise phases; maximum misalignment bet ween adjacent phases of 40 ps × 250 MHz / f OUT_CCC Global Clocking ProASIC3L devices have extensive s upport for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The ProASIC3L family of FPGAs feat ures a flexible I/O structure, su pporting a range of voltages (1.2 V, including single-ended, differential, and voltage-referenced (ProASIC3EL only). The I/Os are organized into banks, with two, four, or eight (ProASIC3EL only) banks per device. The configuration of these banks determines the I/O standards supported ( Table 1-1). For ProASIC3EL, each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be abl e to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following:
• Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
• Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). ProASIC3L banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Table 1-1 • I/O Standards Supported I/O Bank Type Device and Bank Location I/O Standards Supported LVTTL/ LVCMOS PCI/ PCI-X LVPECL, LVDS, B-LVDS, M-LVDS GTL+ 2.5 V/3.3 V, GTL 2.5 V/3.3 V, HSTL I and II, SSTL2 I and II, SSTL3 I and II Pro I/Os A3PE3000L 33 3 3 Advanced I/Os A3P250L, A3P600L, A3P1000L 33 3 Not supported

ProASIC3L Device Family Overview Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support ProASIC3L devices support JEDEC-defined wide range I/O operation. ProASIC3L devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components wit h greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configurat ion. A FlashPoint – Pr ogramming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-5 on page 1-9). 5. Set the I/O Output State. You can set Basic I/O se ttings if you want to use the default I/O settings for your pins, or use Custom I/O settings to cust omize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tri-State: I/O is tristated 6. Click OK to return to the FlashPoi nt – Programming File Generator window. Note: I/O States during programming are saved to the ADB and resulting programming files after completing programming file generation.

ProASIC3L Low Power Flash FPGAs Revision 13 1-9 Figure 1-5 • I/O States During Programming Window

2 – ProASIC3L DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of th e device at these or any other conditions beyond those listed under the Recommended O perating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V VCCI and VMV DC I/O buffer supply voltage –0.3 to 3.75 V VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) V TSTG

3 Storage temperature –65 to +150 °C

3 Junction temperature +125 °C

Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2.

ProASIC3L DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions 1 Symbol Parameter Commercial Industrial Units TA Ambient temperature 0 to +70 –40 to +85 °C TJ Junction Temperature 0 to + 85 –40 to +100 °C VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V VPUMP 5 Programming voltage Programming Mode 4 3.15 to 3.45 3.15 to 3.45 V Operation 5 0 to 3.6 0 to 3.6 V VCCPLL 6 Analog power supply (PLL) 1.2 V–1.5 V wide range core voltage 3 1.14 to 1.575 1.14 to 1.575 V VCCI and VMV 7

3.3 V wide range DC supply voltage

9 2.7 to 3.6 2.7 to 3.6 V LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-14 on page 2-10. VCCI should be at the same voltage within a given I/O bank. 3. All ProASIC3L devices must be programmed with the VCC core voltage at 1.5 V. 4. The programming temperat ure range supported is T ambient = 0°C to 85°C. 5. VPUMP can be left floating during nor mal operation (not programming mode). 6. VCCPLL pins should be tied to VCC pins. See the "VCCPLA/B/C/D/E/F PLL Supply Voltage" section on page 3-1 for further information. 7. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 8. For ProASIC ®3L devices, VCCI VCC. 9. 3.3 V wide range is compliant to the JESD8-A specification and supports 3.0 V VCCI operation. Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1 Product Grade Programming Cycles Program Retention (biased/unbiased) Maximum Storage Temperature TSTG (°C) 2 Maximum Operating Junction Temperature TJ (°C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits.

ProASIC3L Low Power Flash FPGAs Revision 13 2-3 I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is des igned into every ProASIC3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points ( Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI
• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. Table 2-4 • Overshoot and Undershoot Limits 1 VCCI Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 2.7 V or less 10% 1.4 V 5% 1.49 V 3 V 10% 1.1 V 5% 1.19 V 3.3 V 10% 0.79 V 5% 0.88 V 3.6 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at junction temperature at 85°C. 2. The duration is allowed at one out of six clock cycl es. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits.

ProASIC3L DC and Switching Characteristics PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 and Figure 2- 2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels dr op below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down Behavior of Low-Power Flas h Devices" chapter of the ProASIC3L FPGA Fabr ic User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels Region 1: I/O buffers are OFF Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCC VCC = 1.425 V Region 1: I/O Buffers are OFF Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc. Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCCI Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. VCC = VCCI + VT

ProASIC3L Low Power Flash FPGAs Revision 13 2-5 Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels Region 1: I/O buffers are OFF Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Min VCCI datasheet specification voltage at a selected I/O 2.3 V, or 3.0 V VCC VCC = 1.14 V Region 1: I/O Buffers are OFF Activation trip point: Va = 0.85 V ± 0.2 V Deactivation trip point: Vd = 0.75 V ± 0.2 V Activation trip point: Va = 0.9 V ± 0.15 V Deactivation trip point: Vd = 0.8 V ± 0.15 V VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCCI Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. VCC = VCCI + VT

ProASIC3L DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Designer software re fers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and st atic power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: T A = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. EQ 2 Maximum Power Allowed Max. junction temp. (C) Max. ambient temp. ( C)– Table 2-5 • Package Thermal Resistivities Package Type Device Pin Count jc ja UnitsStill Air 200 ft./min. 500 ft./min. Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W Fine Pitch Ball Grid Array (FBGA) A3P250L 144 12.2 43.8 37.7 35.8 C/W A3P600L 144 8.3 35.8 30.2 28.3 C/W A3P1000L 144 6.3 31.6 26.2 24.2 C/W A3P250L 256 12.0 38.6 34.7 33.0 C/W A3P600L 256 8.5 32.0 27.5 25.8 C/W A3P1000L 256 6.6 28.1 24.4 22.7 C/W AGLE3000 324 TBD TBD TBD TBD C/W A3P600L 484 9.5 27.5 21.9 20.2 C/W A3P1000L 484 8.0 23.3 19.0 16.7 C/W A3PE3000L 484 4.7 20.6 15.7 14.0 C/W A3PE3000L 896 2.4 13.6 10.4 9.4 C/W

ProASIC3L Low Power Flash FPGAs Revision 13 2-7 Temperature and Voltage Derating Factors Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (I DD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operati ng temperature, system clock frequency, and power mode usage. Microsemi recommends using the Power Calculator and SmartPower software estimation tools to evaluate the projected static and active power bas ed on the user design, pow er mode usage, operating voltage, and temperature. Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) Array Voltage VCC (V) Junction Temperature (°C) –40°C 0°C 25°C 70°C 85°C 110°C Table 2-7 • Power Supply State per Mode Modes/Power Supplies Power Supply Configurations VCC VCCPLL VCCI VJTAG VPUMP Flash*Freeze On On On On On/off/floating Sleep Off Off On Off Off Shutdown Off Off Off Off Off No Flash*Freeze On On On On On/off/floating Note: Off: Power Supply level = 0 V Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units Note: * IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents.

ProASIC3L DC and Switching Characteristics Table 2-9 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode* ICCI Current Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units VCCI/VJTAG = 1.2 V (per bank) Typical (25°C) VCCI/VJTAG = 1.5 V (per bank) Typical (25°C) VCCI/VJTAG = 1.8 V (per bank) Typical (25°C) VCCI/VJTAG = 2.5 V (per bank) Typical (25°C) VCCI/VJTAG = 3.3 V (per bank) Typical (25°C) Note: *IDD = NBANKS * ICCI Table 2-10 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode Core Voltage A3PE3000L Units Typical (25°C) 1.2 V/1.5 V 0 µA Table 2-11 • Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 Core Voltage A3P250L A3P600L A3P1000L A3PE3000L Units ICCA Current2 ICCI or IJTAG Current VCCI/VJTAG = 1.2 V (per bank) Typical (25°C) VCCI/VJTAG = 1.5 V (per bank) Typical (25°C) VCCI/VJTAG = 1.8 V (per bank) Typical (25°C) VCCI/VJTAG = 2.5 V (per bank) Typical (25°C) VCCI/VJTAG = 3.3 V (per bank) Typical (25°C) Notes: 1. *IDD = N BANKS * ICCI+ICCA. JTAG counts as one bank when powered. 2. Includes VCC and VPUMP and VCCPLL currents.

ProASIC3L Low Power Flash FPGAs Revision 13 2-9 Power per I/O Pin Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Pro I/O Banks VCCI (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended 3.3 V LVTTL/LVCMOS 3.3 – 16.34 3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 24.49 2.5 V LVCMOS 2.5 – 4.71 2.5 V LVCMOS – Schmitt trigger 2.5 – 6.13 1.8 V LVCMOS 1.8 – 1.66 1.8 V LVCMOS – Schmitt trigger 1.8 – 1.78 1.5 V LVCMOS (JESD8-11) 1.5 – 1.01 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 0.97 1.2 V LVCMOS 1.2 – 0.60 1.2 V LVCMOS – Schmitt trigger 1.2 – 0.53 3.3 V PCI 3.3 – 17.76 3.3 V PCI – Schmitt trigger 3.3 – 19.10 3.3 V PCI-X 3.3 – 17.76 3.3 V PCI-X – Schmitt trigger 3.3 – 19.10 Voltage-Referenced 3.3 V GTL 3.3 2.90 7.07 2.5 V GTL 2.5 2.13 3.62 3.3 V GTL+ 3.3 2.81 2.97 2.5 V GTL+ 2.5 2.57 2.55 HSTL (I) 1.5 0.17 0.85 HSTL (II) 1.5 0.17 0.85 SSTL2 (I) 2.5 1.38 3.30 SSTL2 (II) 2.5 1.38 3.30 SSTL3 (I) 3.3 3.21 8.08 SSTL3 (II) 3.3 3.21 8.08 Differential LVDS 2.5 2.26 0.95 LVPECL 3.3 5.71 1.62 Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI.

ProASIC3L DC and Switching Characteristics Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Advanced I/O Banks VCCI (V) Static Power PDC6 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.22 2.5 V LVCMOS 2.5 – 4.65 1.8 V LVCMOS 1.8 – 1.65 1.5 V LVCMOS (JESD8-11) 1.5 – 0.98 1.2 V LVCMOS 1.2 – 0.61 3.3 V PCI 3.3 – 17.64 3.3 V PCI-X 3.3 – 17.64 Differential LVDS 2.5 2.26 0.95 LVPECL 3.3 5.72 1.63 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. P DC6 is the static power (where applicable) measured on VCCI. 3. P AC10 is the total dynamic power measured on VCCI. Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks VCCI (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS

3.3 – 16.23 2.5 V LVCMOS 2.5 – 4.66 1.8 V LVCMOS 1.8 – 1.64 1.5 V LVCMOS (JESD8-11) 1.5 – 0.99 1.2 V LVCMOS 1.2 – 0.58 3.3 V PCI 3.3 – 17.64 3.3 V PCI-X 3.3 – 17.64 Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI.

ProASIC3L Low Power Flash FPGAs Revision 13 2-11 Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 Applicable to Pro I/Os CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Single-Ended 3.3 V LVTTL/LVCMOS 5 3.3 – 148.00 2.5 V LVCMOS 5 2.5 – 83.23 1.8 V LVCMOS 5 1.8 – 54.58 1.5 V LVCMOS (JESD8-11) 5 1.5 – 37.05 1.2 V LVCMOS 5 1.2 – 17.94 3.3 V PCI 10 3.3 – 204.61 3.3 V PCI-X 10 3.3 – 204.61 Voltage-Referenced 3.3 V GTL 10 3.3 – 24.08 2.5 V GTL 10 2.5 – 13.52 3.3 V GTL+ 10 3.3 – 24.10 2.5 V GTL+ 10 2.5 – 13.54 HSTL (I) 20 1.5 7.08 26.22 HSTL (II) 20 1.5 13.88 27.22 SSTL2 (I) 30 2.5 16.69 105.56 SSTL2 (II) 30 2.5 25.91 116.60 SSTL3 (I) 30 3.3 26.02 114.87 SSTL3 (II) 30 3.3 42.21 131.76 Differential LVDS – 2.5 7.70 89.62 LVPECL – 3.3 19.42 168.02 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI.

ProASIC3L DC and Switching Characteristics Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 Applicable to Advanced I/O Banks CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 141.97 2.5 V LVCMOS 5 2.5 – 79.98 1.8 V LVCMOS 5 1.8 – 52.26 1.5 V LVCMOS (JESD8-11) 5 1.5 – 35.62 1.2 V LVCMOS 5 1.2 – 21.29 3.3 V PCI 10 3.3 – 201.02 3.3 V PCI-X 10 3.3 – 201.02 Differential LVDS – 2.5 7.74 89.71 LVPECL – 3.3 19.54 167.54 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 Applicable to Standard Plus I/O Banks CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 – 125.97 2.5 V LVCMOS 5 2.5 – 70.82 1.8 V LVCMOS 5 1.8 – 36.39 1.5 V LVCMOS (JESD8-11) 5 1.5 – 25.34 1.2 V LVCMOS 5 1.2 – 16.24 3.3 V PCI 10 3.3 – 184.92 3.3 V PCI-X 10 3.3 – 184.92 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI.

ProASIC3L Low Power Flash FPGAs Revision 13 2-13 Power Consumption of Various Internal Resources Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at

1.2 V VCC

Device Specific Dynamic Power (µW/MHz) A3PE3000L A3P1000L A3P600L A3P250L PAC1 Clock contribution of a Global Rib 12.61 9.28 8.19 7.07 PAC2 Clock contribution of a Global Spine 2.66 1.59 1.19 1.01 PAC3 Clock contribution of a VersaTile row 0.56 0.52 PAC4 Clock contribution of a VersaTile used as a sequential module 0.07 PAC5 First contribution of a VersaTile used as a sequential module 0.05 PAC6 Second contribution of a VersaTile used as a sequential module 0.19 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.11 PAC8 Average contribution of a routing net 0.45 PAC9 Contribution of an I/O in put pin (standard-dependent) See Table 2-12 on page 2-9. through Table 2-14 on page 2-10. PAC10 Contribution of an I/O outp ut pin (standard-dependent) See Table 2-15 on page 2-11 through Table 2-17 on page 2-12. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 1.74 Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero SoC.

ProASIC3L DC and Switching Characteristics Table 2-19 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at

1.5 V VCC

Device Specific Dynamic Power (µW/MHz) A3PE3000L A3P1000L A3P600L A3P250L PAC1 Clock contribution of a Global Rib 19.7 14.50 12.80 11.00 PAC2 Clock contribution of a Global Spine 4.16 2.48 1.85 1.58 PAC3 Clock contribution of a VersaTile row 0.88 0.81 PAC4 Clock contribution of a VersaTile used as a sequential module 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O in put pin (standard-dependent) See Table 2-12 on page 2-9. through Table 2-14 on page 2-10. PAC10 Contribution of an I/O outp ut pin (standard-dependent) See Table 2-15 on page 2-11 through Table 2-17 on page 2-12. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.60 Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero SoC. Table 2-20 • Different Components Contributing to the Static Power Consumption in ProASIC3L Devices Parameter Definition Device Specific Dynamic Power (µW) A3PE3000L A3P1000L A3P600L A3P250L PDC1 Array static power in Active mode See Table 2-11 on page 2-8. PDC2 Array static power in Static (Idle) mode See Table 2-9 on page 2-8. PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7. PDC4 Static PLL contribution at 1.2 V core (operating mode only) 1.42 mW Static PLL contribution at 1.5 V core (operating mode only) 2.55 mW PDC5 Bank quiescent power (VCCI-dependent) See Table 2-8 on page 2-7, Table 2-9 on page 2-8, Table 2-11 on page 2-8. PDC6 I/O input pin static power (standard-dependent) See Table 2-12 on page 2-9 through Table 2-14 on page 2-10. PDC7 I/O output pin static power (standard-dependent) See Table 2-15 on page 2-11 through Table 2-17 on page 2-12. Note: *For a different output load, drive strength, or sl ew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero SoC.

ProASIC3L Low Power Flash FPGAs Revision 13 2-15 Power Calculation Methodology This section describes a simplified method to estima te power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC software. The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number a nd the frequency of each output clock generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-21 on page 2-17.
• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-22 on page 2-17.
• Read rate and write rate to the memory—guidel ines are provided for typical applications in Table 2-22 on page 2-17. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—P TOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—P STAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS* PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption—P DYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—P CLOCK PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine Architecture" section of the ProASIC3L FPGA Fabric User’s Guide. NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine Architecture" section of the ProASIC3L FPGA Fabric User’s Guide. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—P S-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on page 2-17. FCLK is the global clock signal frequency.

ProASIC3L DC and Switching Characteristics Combinatorial Cells Contribution—P C-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on page 2-17. FCLK is the global clock signal frequency. Routing Net Contribution—P NET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on page 2-17. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—P INPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-21 on page 2-17. FCLK is the global clock signal frequency. I/O Output Buffer Contribution—P OUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-21 on page 2-17. 1 is the I/O buffer enable rate—guidelines are provided in Table 2-22 on page 2-17. FCLK is the global clock signal frequency. RAM Contribution—P MEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations—guidelines are provided in Table 2-22 on page 2-17. PLL Contribution—P PLL PPLL = PDC4 + PAC13 * FCLKOUT FCLKOUT is the output clock frequency.1 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.

ProASIC3L Low Power Flash FPGAs Revision 13 2-17 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic elem ent relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency.
• The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – Bit 7 (MSB) = 0.78125% Enable Rate Definition Output enable rate is the average percentage of ti me during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-21 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Guideline 1 Toggle rate of VersaTile outputs 10% 2 I/O buffer toggle rate 10% Table 2-22 • Enable Rate Guidelines Recommended for Power Calculation Component Definition Guideline 1 I/O output buffer enable rate 100% 2 RAM enable rate for read operations 12.5% 3 RAM enable rate for write operations 12.5%

ProASIC3L DC and Switching Characteristics User I/O Characteristics Timing Model Figure 2-3 • Timing Model Operating Conditions: –1 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC =1 . 1 4V DQ Y Y DQDQ DQY Combinational Cell Combinational Cell Combinational Cell I/O Module (Registered) I/O Module (Non-Registered) Register Cell Register Cell I/O Module (Registered) I/O Module (Non-Registered) LVPECL (Applicable to Advanced I/O Banks Only)L LVPECL (Applicable to Advanced I/O Banks only) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) LVTTL 3.3 V Output drive strength = 12 mA High slew rate Y Combinational Cell Y Combinational Cell Y Combinational Cell I/O Module (Non-Registered) LVTTLOutput drive strength = 8 mA High slew rate I/O Module (Non-Registered) LVCMOS 1.5 VOutput drive strength = 4 mA High slew rate LVTTLOutput drive strength = 12 mA High slew rate I/O Module (Non-Registered) Input LVTTL Clock Input LVTTL Clock Input LVTTL Clock tPD = 0.56 ns tPD = 0.49 ns tDP = 1.34 ns tPD = 0.87 ns tDP = 2.64 ns (Advanced I/O Banks) tPD = 0.47 ns tDP = 3.66 ns (Advanced I/O Banks) tPD = 0.47 ns tDP = 3.97 ns (Advanced I/O Banks) tPD = 0.47 ns tPY = 0.76 ns (Advanced I/O Banks) tCLKQ = 0.55 ns tOCLKQ = 0.59 ns tSUD = 0.43 ns tOSUD = 0.31 ns tDP = 2.64 ns (Advanced I/O Banks) tPY = 0.76 ns (Advanced I/O Banks) tPY = 1.20 ns tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 0.76 ns (Advanced I/O Banks) tICLKQ = 0.24 ns tISUD = 0.26 ns tPY = 1.05 ns

ProASIC3L Low Power Flash FPGAs Revision 13 2-19 Figure 2-4 • Input Buffer Timing Model and Delays (example) tPY (R) PAD Y Vtrip GND tPY (F) Vtrip 50%50% VIH VCC VIL tDIN (R) DIN GND tDIN (F) 50%50% VCC PAD Y tPY D CLK Q I/O Interface DIN tDIN To Array tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F))

ProASIC3L DC and Switching Characteristics Figure 2-5 • Output Buffer Model and Delays (example) tDP (R) PAD VOL tDP (F) VtripVtrip VOH VCC D 50% 50% VCC 0 V DOUT 50% 50% 0 V tDOUT (R) tDOUT (F) From Array PAD tDP Std Load D CLK Q I/O Interface DOUT D tDOUT tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3L Low Power Flash FPGAs Revision 13 2-21 Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example) D CLK Q D CLK Q 10% VCCI tZL Vtrip 50% tHZ 90% VCCI tZH Vtrip 50% 50% tLZ 50% EOUT PAD D E 50% tEOUT (R) 50% tEOUT (F) PAD DOUT EOUT D I/O Interface E tEOUT tZLS Vtrip 50% tZHS Vtrip 50%EOUT PAD D E 50% 50%tEOUT (R) tEOUT (F) 50% VCC VCC VCC VCCI VCC VCC VCC VOH VOL VOL tZL, tZH, tHZ, tLZ, tZLS, tZHS tEOUT = MAX(tEOUT(r), tEOUT(f))

ProASIC3L DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—S oftware Default Settings Applicable to Pro I/O Banks I/O Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate VIL VIH VOL VOH IOL 3 IOH3 Min. V Max. V Min. V Max.2 V Max. V Min. Vm A m A 3.3 V LVCMOS 3.3 V LVCMOS Wide Range4 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range5

3.3 V PCI Per PCI Specification

3.3 V PCI-X Per PCI-X Specification

HSTL (II) 15 mA Notes: 1. Please note that 1.2V LVCMOS and 3.3V LVCMOS wide range is applicable to 100uA drive strength only. The configuration will NOT operate at the equivalent software. 2. Maximum VIH is 3.6 V for all I/O standards with hot-insertion is enabled. 3. Currents are measured at 85°C junction temperature. 4. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification. 5. All LVCMOS 1.2 V software macros support LVCMOS 1. 2 V wide range as specified in the JESD8-12 specification. 6. Output drive strength is below JEDEC specification. 7. Output slew rate can be extracted using the IBIS models.

ProASIC3L Low Power Flash FPGAs Revision 13 2-23 Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—S oftware Default Settings Applicable to Advanced I/O Banks I/O Standard Drive Strength Equiv. Software Default Drive Strength Option1 Slew Rate VIL VIH VOL VOH IOL 2 IOH2 Min. V Max. V Min. V Max. V Max. V Min. Vm A m A 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range4,5

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Notes: 1. Please note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software. 2. Currents are measured at 85°C junction temperature. 3. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification. 4. All LVCMOS 1.2 V software macros support LVCMOS 1. 2 V wide range as specified in the JESD8-12 specification. 5. Applicable to devices operating at VCCI ≥ VCC. 6. Output slew rate can be extracted using the IBIS models.

ProASIC3L DC and Switching Characteristics Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—S oftware Default Settings Applicable to Standard Plus I/O Banks I/O Standard Drive Strength Equiv. Software Default Drive Strength Option1 Slew Rate VIL VIH VOL VOH IOL 2 IOH2 Min. V Max. V Min. V Max. V Max. V Min. Vm A m A 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range 4,5 Notes: 1. Please note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software. 2. Currents are measured at 85°C junction temperature. 3. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification. 4. All LVCMOS 1.2 V software macros support LVCMOS 1. 2 V wide range as specified in the JESD8-12 specification. 5. Applicable to devices operating at VCCI ≥ VCC. 6. Output slew rate can be extracted using the IBIS models.

ProASIC3L Low Power Flash FPGAs Revision 13 2-25 Table 2-26 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standard Commercial1 Industrial2 IIL IIH IIL 3 IIH4 µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCMOS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

1.2 V LVCMOS

1.2 V LVCMOS Wide Range5 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

3.3 V GTL 10 10 15 15

2.5 V GTL 10 10 15 15

3.3 V GTL+ 10 10 15 15

2.5 V GTL+ 10 10 15 15

HSTL (I) 10 10 15 15 HSTL (II) 10 10 15 15 SSTL2 (I) 10 10 15 15 SSTL2 (II) 10 10 15 15 SSTL3 (I) 10 10 15 15 SSTL3 (II) 10 10 15 15 Notes: 1. Commercial range (0°C < T A < 70°C) 2. Industrial range (–40°C < T A < 85°C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3V < VIN <VIL. 4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Applicable to devices operating at VCCI  VCC.

ProASIC3L DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-27 • Summary of AC Measuring Points Standard Input Reference Voltage (VREF_TYP) Board Termination Voltage (VTT_REF) Measuring Trip Point (Vtrip) – – 1.4 V 3.3 V LVCMOS Wide Range – – 1.4 V 2.5 V LVCMOS – – 1.2 V 1.8 V LVCMOS – – 0.90 V 1.5 V LVCMOS – – 0.75 V 1.2 V LVCMOS * – – 0.6 V 1.2 V LVCMOS Wide Range* – – 0.6 V 3.3 V PCI – – 0.285 * VCCI (RR) 0.615 * VCCI (FF)) 3.3 V PCI-X – – 0.285 * VCCI (RR) 0.615 * VCCI (FF) 3.3 V GTL 0.8 V 1.2 V VREF 2.5 V GTL 0.8 V 1.2 V VREF 3.3 V GTL+ 1.0 V 1.5 V VREF 2.5 V GTL+ 1.0 V 1.5 V VREF HSTL (I) 0.75 V 0.75 V VREF HSTL (II) 0.75 V 0.75 V VREF SSTL2 (I) 1.25 V 1.25 V VREF SSTL2 (II) 1.25 V 1.25 V VREF SSTL3 (I) 1.5 V 1.485 V VREF SSTL3 (II) 1.5 V 1.485 V VREF LVDS – – Cross point LVPECL – – Cross point Note: *Applicable only to devices operating in the 1.2 V core range. Table 2-28 • I/O AC Parameter Definitions Parameter Parameter Definition t DP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer—High to Z tZH Enable to Pad delay through the Output Buffer—Z to High tLZ Enable to Pad delay through the Output Buffer—Low to Z tZL Enable to Pad delay through the Output Buffer—Z to Low tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to High tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

ProASIC3L Low Power Flash FPGAs Revision 13 2-27

1.5 V DC Core Voltage

Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425V, Worst Case VCCI Pro I/O Banks Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tPYS (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units Wide Range1,2

3.3 V PCI Per

spec.

3.3 V PCI-X Per

spec. HSTL (II) LVDS 24 mA 24 mA High – – 0.50 1.40 0.03 1.85 – – – – – – – – ns LVPECL 24 mA 24 mA High – – 0.50 1.40 0.03 1.67 – – – – – – – – ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 5. Output drive strength is below JEDEC specification.

ProASIC3L DC and Switching Characteristics Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI Advanced I/O Banks I/O Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) t ZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units Wide Range1,2 spec. spec. LVDS 24 mA – High – – 0.46 1.40 0.03 1.23 N/A N/A N/A N/A N/A N/A N/A ns LVPECL 24 mA – High – – 0.46 1.38 0.03 1.08 N/A N/A N/A N/A N/A N/A N/A ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCM OS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-29 Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V Standard Plus I/O Banks I/O Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units Wide Range1,2 spec. spec. Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case VCCI Pro I/O Banks Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tPYS (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units Wide Range1,2 Wide Range1,3 spec. spec. Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros s upport LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 6. Output drive strength is below JEDEC specification.

ProASIC3L Low Power Flash FPGAs Revision 13 2-31 L V D S 2 4 m A – H i g h – – 0 . 6 6 1 . 4 3 0 . 0 4 1 . 8 5 –––––––– n s L V P E C L 2 4 m A – H i g h – – 0 . 6 6 1 . 3 7 0 . 0 4 1 . 6 7 –––––––– n s Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case VCCI Advanced I/O Banks I/O Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units Wide Range1,2 Wide Range1,3 spec. – High 10 pF Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case VCCI Pro I/O Banks Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tPYS (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros s upport LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 6. Output drive strength is below JEDEC specification.

ProASIC3L DC and Switching Characteristics spec. – High 10 pF LVDS 24 mA – High – – 0.60 1. 40 0.04 1.23 N/A N/A N/A N/A N/A N/A N/A ns LVPECL 24 mA – High – – 0.60 1.38 0.04 1.08 N/A N/A N/A N/A N/A N/A N/A ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros s upport LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case VCCI Advanced I/O Banks I/O Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units

ProASIC3L Low Power Flash FPGAs Revision 13 2-33 Detailed I/O DC Characteristics Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case VCCI = 3.0 V Standard Plus I/O Banks I/O Standard Drive Strength (mA) Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units Wide Range1,2 Wide Range1,3 spec. spec. Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros s upport LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-35 • Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance V IN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin V IN = 0, f = 1.0 MHz 8 pF

ProASIC3L DC and Switching Characteristics Table 2-36 • I/O Output Buffer Maximum Resistances1 Applicable to Pro I/Os Standard Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 4 mA 100 200

1.8 V LVCMOS 2 mA 200 225

1.5 V LVCMOS 2 mA 200 224

1.2 V LVCMOS 2 mA 158 164

1.2 V LVCMOS Wide Range 100 µA Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS

3.3 V PCI/PCI-X Per PCI/PCI-X

3.3 V GTL 20 mA

4 11 –

2.5 V GTL 20 mA 4 14 –

3.3 V GTL+ 35 mA 12 –

2.5 V GTL+ 33 mA 15 –

HSTL (I) 8 mA 50 50 HSTL (II) 15 mA 4 25 25 SSTL2 (I) 15 mA 27 31 SSTL2 (II) 18 mA 13 15 SSTL3 (I) 14 mA 44 69 SSTL3 (II) 21 mA 18 32 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec 4. Output drive strength is below JEDEC specification.

ProASIC3L Low Power Flash FPGAs Revision 13 2-35 Table 2-37 • I/O Output Buffer Maximum Resistances1 Applicable to Advanced I/O Banks Standard Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 100 300

1.8 V LVCMOS 2 mA 100 200

1.2 V LVCMOS Wide Range 100 µA Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3L DC and Switching Characteristics Table 2-38 • I/O Output Buffer Maximum Resistances1 Applicable to Standard Plus I/O Banks Standard Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 25 75 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 100 200

1.2 V LVCMOS Wide Range 100 µA Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS Notes: 1. These maximum values are provided for informational reas ons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3L Low Power Flash FPGAs Revision 13 2-37 Table 2-39 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values VCCI R(WEAK PULL-UP) () R(WEAK PULL-DOWN) () Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

3.3 V (wide range I/Os) 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

1.2 V LVCMOS 25 k 110 k 25 k 150 k

1.2 V (wide range I/Os) 19 k 110 k 19 k 150 k

Notes: 1. R (WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) 2. R (WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)

ProASIC3L DC and Switching Characteristics Table 2-40 • I/O Short Currents IOSH/IOSL Applicable to Pro I/Os Standard Drive Strength IOSL (mA)* IOSH (mA)* 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 4 mA 16 18

1.8 V LVCMOS 2 mA 9 11

1.5 V LVCMOS 2 mA 13 16

1.2 V LVCMOS 2 mA 20 26

1.2 V LVCMOS Wide Range 100 µA 20 26

3.3 V PCI/PCIX Per PCI/PCI-X

2.5 V GTL 20 mA 2 169 124

3.3 V GTL+ 35 mA 268 181

2.5 V GTL+ 33 mA 169 124

HSTL (I) 8 mA 32 39 HSTL (II) 15 mA 2 66 55 SSTL2 (I) 15 mA 83 87 SSTL2 (II) 18 mA 169 124 SSTL3 (I) 14 mA 51 54 Notes: 1. *TJ = 100°C 2. Output drive strength is below JEDEC specification.

ProASIC3L Low Power Flash FPGAs Revision 13 2-39 Table 2-41 • I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks Standard Drive Strength IOSL (mA)* IOSH (mA)* 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 16 18

Note: *T J = 100°C

ProASIC3L DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junc tion temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-42 • I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks Drive Strength IOSL (mA)* IOSH (mA)* 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 12 mA 103 109 16 mA 103 109 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS Note: T J = 100°C Table 2-43 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

1.2 V LVCMOS (Schmitt trigger mode) 40 mV

ProASIC3L Low Power Flash FPGAs Revision 13 2-41 Table 2-44 • Duration of Short Circuit Event before Failure Temperature Time before Failure –40°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months Table 2-45 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C) LVDS/B-LVDS/ M-LVDS/LVPECL No requirement 10 ns * 10 years (100°C) Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

ProASIC3L DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low voltage transistor–transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. This standard uses an LVTTL input bu ffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range, as specified in the JESD8-A specification. Table 2-46 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/O Banks

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray.

ProASIC3L Low Power Flash FPGAs Revision 13 2-43 Table 2-48 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Figure 2-7 • AC Loading Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 03 . 3 1 . 4 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-45 Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-47 Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-49 Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

3.3 V LVCMOS Wide Range

Table 2-62 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Pro I/O Banks 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA2 Max. mA2 µA µA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85°C junction temperature. 3. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JDEC8-B specification 4. Software default selection highlighted in gray. Table 2-63 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Advanced I/O Banks 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA2 Max. mA2 µA µA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85°C junction temperature. 3. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JDEC8-B specification 4. Software default selection highlighted in gray.

ProASIC3L Low Power Flash FPGAs Revision 13 2-51 Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Standard Plus I/O Banks 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA2 Max. mA2 µA µA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85°C junction temperature. 3. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JDEC8-B specification 4. Software default selection highlighted in gray.

ProASIC3L DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. Table 2-65 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-66 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray.

ProASIC3L Low Power Flash FPGAs Revision 13 2-53 Table 2-67 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Figure 2-8 • AC Loading Table 2-68 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 02 . 5 1 . 2 5 Note: *Measuring point = Vtrip . See Table 2-27 on page 2-26 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-69 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-70 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-55 Table 2-71 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-72 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-73 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-74 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-57 Table 2-75 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-76 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-77 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-78 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-59 Table 2-79 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-80 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standa rd (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-81 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. VM i n . V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-82 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 8 mA –0.3 0.35 * VCCI 0.65 * V CCI 1.9 0.45 VCCI – 0.45 8 8 45 51 10 10 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray.

ProASIC3L Low Power Flash FPGAs Revision 13 2-61 Table 2-83 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 6 mA –0.3 0.35 * VCCI 0.65 * V CCI 1.9 0.45 VCCI – 0.45 6 6 35 44 10 10 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Figure 2-9 • AC Loading Table 2-84 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 01 . 8 0 . 9 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-85 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-86 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-63 Table 2-87 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-88 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-89 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-90 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-65 Table 2-91 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-92 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-93 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-94 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-67 Table 2-95 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-96 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-97 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-98 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray.

ProASIC3L Low Power Flash FPGAs Revision 13 2-69 Table 2-99 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Figure 2-10 • AC Loading Table 2-100 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 01 . 5 0 . 7 5 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-101 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-102 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-71 Table 2-103 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-104 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-105 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-106 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-73 Table 2-107 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-108 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-109 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-110 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-75 Table 2-111 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-112 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-113 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.2 V LVCMOS VIL VIH VOL VOH IOL IOH IOSH 1 IOSL1 IIL2 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA Max. mA µA µA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-114 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.2 V LVCMOS VIL VIH VOL VOH IOL IOH IOSH 1 IOSL1 IIL2 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA Max. mA µA µA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-115 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.2 V LVCMOS VIL VIH VOL VOH IOL IOH IOSH 1 IOSL1 IIL2 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA Max. mA µA µA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray.

ProASIC3L Low Power Flash FPGAs Revision 13 2-77 Figure 2-11 • AC Loading Table 2-116 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 01 . 2 0 . 6 5 Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-117 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Unit s Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-118 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Unit s Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-119 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-120 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-121 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-79 Table 2-122 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

1.2 V LVCMOS Wide Range

Table 2-123 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range Applicable to Pro I/O Banks 1.2 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA2 Max. mA2 µA µA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85°C junction temperature. 3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification 4. Software default selection highlighted in gray. Table 2-124 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 Wide Range Applicable to Advanced I/O Banks 1.2 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA2 Max. mA2 µA µA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85°C junction temperature. 3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification 4. Software default selection highlighted in gray. Table 2-125 • Minimum and Maximum DC Input and Output Levels for LVCMOS 1.2 V Wide Range Applicable to Standard Plus I/O Banks 1.2 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA2 Max. mA2 µA µA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Currents are measured at 85°C junction temperature. 3. All LVMCOS 1.2 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-12 specification 4. Software default selection highlighted in gray.

ProASIC3L Low Power Flash FPGAs Revision 13 2-81 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. AC loadings are defined per the PCI/PCI-X specifications for the database; Microsemi loadings for enable path characterization are described in Figure 2-12. AC loadings are defined per PCI/PC I-X specifications for the datapath; Microsemi loading for tristate is described in Table 2-127. Timing Characteristics Table 2-126 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Per PCI specification Per PCI curves 10 10 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-12 • AC Loading Test Point Enable Path R to VCCI for tLZ / tZL / tZLS 10 pF for tZH / tZHS / tZL / tZLS 10 pF for tHZ / tLZ R to GND for tHZ / tZH / tZHS R = 1 k Test Point Datapath R = 25 R to VCCI for tDP (F) R to GND for tDP (R) Table 2-127 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 0 3.3 0.285 * VCCI for t DP(R) 0.615 * VCCI for tDP(F) Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points. Table 2-128 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-129 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-130 • 3.3 V PCI/PCI-X – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-131 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-132 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-133 • 3.3 V PCI/PCI-X – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-83 Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-134 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. Figure 2-13 • AC Loading Table 2-135 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 10 pF 25GTL VTT

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-136 • 3.3 V GTL – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-137 • 3.3 V GTL – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/Os Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-85

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V Table 2-138 • Minimum and Maximum DC Input and Output Levels

2.5 GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. Figure 2-14 • AC Loading Table 2-139 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 10 pF 25GTL VTT

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-140 • 2.5 V GTL – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-141 • 2.5 V GTL – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-87

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V Timing Characteristics Table 2-142 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+ VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-15 • AC Loading Table 2-143 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 10 pF 25GTL+ VTT Table 2-144 • 3.3 V GTL+ – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-145 • 3.3 V GTL+ – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-146 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+ VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-16 • AC Loading Table 2-147 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 10 pF 25GTL+ VTT

ProASIC3L Low Power Flash FPGAs Revision 13 2-89 Timing Characteristics Table 2-148 • 2.5 V GTL+ – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature an d voltage supply levels, refer to Table 2-16 on page 2-12 for derating values. Table 2-149 • 2.5 V GTL+ – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature an d voltage supply levels, refer to Table 2-16 on page 2-12 for derating values.

ProASIC3L DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpo se high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-150 • Minimum and Maximum DC Input and Output Levels HSTL Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-17 • AC Loading Table 2-151 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip . See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 20 pF HSTL Class I VTT

ProASIC3L Low Power Flash FPGAs Revision 13 2-91 Timing Characteristics Table 2-152 • HSTL Class I – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-153 • HSTL Class I – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpo se high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-154 • Minimum and Maximum DC Input and Output Levels HSTL Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. Figure 2-18 • AC Loading Table 2-155 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 20 pF HSTL Class II VTT

ProASIC3L Low Power Flash FPGAs Revision 13 2-93 Timing Characteristics Table 2-156 • HSTL Class II – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-157 • HSTL Class II – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-158 • Minimum and Maximum DC Input and Output Levels SSTL2 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-19 • AC Loading Table 2-159 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 30 pF SSTL2 Class I VTT

ProASIC3L Low Power Flash FPGAs Revision 13 2-95 Timing Characteristics Table 2-160 • SSTL2 Class I – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/Os Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-161 • SSTL2 Class I – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-162 • Minimum and Maximum DC Input and Output Levels SSTL2 Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-20 • AC Loading Table 2-163 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 30 pF SSTL2 Class II VTT Table 2-164 • SSTL2 Class II – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-165 • SSTL2 Class II – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-97 SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-166 • Minimum and Maximum DC Input and Output Levels SSTL3 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-21 • AC Loading Table 2-167 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 30 pF SSTL3 Class I VTT Table 2-168 • SSTL3 Class I – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-169 • SSTL3 Class I – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-170 • Minimum and Maximum DC Input and Output Levels SSTL3 Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-22 • AC Loading Table 2-171 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip . See Table 2-16 on page 2-12 for a complete table of trip points. Test Point 30 pF SSTL3 Class II VTT Table 2-172 • SSTL3 Class II – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-173 • SSTL3 Class II – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V VREF = 1.5 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-99 Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjuncti on with the embedded Input R egister (InReg), Output Register (OutReg), Enable Register (EnReg), an d Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644 ) is a high-speed, differential I/O standard. It requires that one data bit be carried through two si gnal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The building blocks of the LVDS transmitter-receiver are one transmitte r macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, ProASIC3 also supports Bu s LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes). Figure 2-23 • LVDS Circuit Diagram and Board-Level Implementation 140  100  Z0 = 50  Z0 = 50  165  165  P N P N INBUF_LVDS OUTBUF_LVDS FPGA FPGA Bourns Part Number: CAT16-LV4F12

ProASIC3L DC and Switching Characteristics Table 2-174 • Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units VCCI Supply Voltage 2.375 2.5 2.625 V VOL Output Low Voltage 0.9 1.075 1.25 V VOH Output High Voltage 1.25 1.425 1.6 V IOL 1 Output Lower Current 0.65 0.91 1.16 mA IOH 1 Output High Current 0.65 0.91 1.16 mA VI Input Voltage 0 2.925 V IIH 2 Input High Leakage Current 10 µA IIL 2 Input Low Leakage Current 10 µA VODIFF Differential Output Voltage 250 350 450 mV VOCM Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 V VIDIFF Input Differential Voltage 100 350 mV Notes: 1. Currents are measured at 85°C junction temperature. 2. IOL/IOH is defined by VO DIFF/(Resistor Network). Table 2-175 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.075 1.325 Cross point Note: *Measuring point = V trip. See Table 2-27 on page 2-26 for a complete table of trip points.

ProASIC3L Low Power Flash FPGAs Revision 13 2-101 Timing Characteristics Table 2-176 • LVDS – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY Units –1 0.50 1.40 0.03 1.85 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-177 • LVDS – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Speed Grade t DOUT tDP tDIN tPY Units –1 0.46 1.40 0.03 1.23 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-178 • LVDS – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY Units –1 0.66 1.43 0.04 1.85 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-179 • LVDS – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Speed Grade t DOUT tDP tDIN tPY Units –1 0.60 1.40 0.04 1.23 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multid rop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accomm odate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appr opriate terminations. Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-24. The input and output buffer delays are available in the LVDS section in Table 2-174 on page 2-100. Example: For a bus consisting of 20 equidistant lo ads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R S =6 0  and RT =7 0 , given Z0 =5 0  (2") and Zstub =5 0  (~1.5"). Figure 2-24 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers ... RT RT BIBUF_LVDS R + - T + - R + - T + - D + - EN EN EN EN EN Receiver Transceiver Receiver Transceiver Driver RS RS RS RS RS RS RS RSRS RS Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub

ProASIC3L Low Power Flash FPGAs Revision 13 2-103 LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differ ential I/O standard. It requires that one data bit be carried through two signal lines . Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-25. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation beca use the output standard specifications are different. Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation Table 2-180 • Minimum and Maximum DC Input and Output Levels VCCI Supply Voltage 3.0 3.3 3.6 V VIL, VIH Input Low, Input High Voltages 0 3.6 0 3.6 0 3.6 V VIDIFF Input Differential Voltage 300 300 300 mV Table 2-181 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.64 1.94 Cross point Note: *Measuring point = Vtrip. See Table 2-27 on page 2-26 for a complete table of trip points.

187 W 100 

Z0 = 50  Z0 = 50  100  100  P N P N INBUF_LVPECL OUTBUF_LVPECLFPGA FPGA Bourns Part Number: CAT16-PC4F12

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-182 • LVPECL – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY Units –1 0.50 1.40 0.03 1.67 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-183 • LVPECL – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade t DOUT tDP tDIN tPY Units –1 0.46 1.38 0.03 1.08 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-184 • LVPECL – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/O Banks Speed Grade t DOUT tDP tDIN tPY Units –1 0.66 1.37 0.04 1.67 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-185 • LVPECL – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade t DOUT tDP tDIN tPY Units –1 0.60 1.38 0.04 1.08 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-105 I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Figure 2-26 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF INBUF INBUF TRIBUF CLKBUF INBUFINBUFCLKBUF Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered Pad Out CLK Enable Preset Data_out Data EOUT DOUT Enable CLK DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE D_Enable A B C D E E E E F G H I J L K Y Core Array

ProASIC3L DC and Switching Characteristics Table 2-186 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register H, DOUT tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A Note: *See Figure 2-26 on page 2-105 for more information.

ProASIC3L Low Power Flash FPGAs Revision 13 2-107 Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Figure 2-27 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Enable CLK Pad Out CLK Enable CLR Data_out Data Y AA EOUT DOUT Core ArrayDQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR D_Enable BB CC DD EE FF GG LL HH JJ KK CLKBUF INBUF INBUF TRIBUF INBUF INBUF CLKBUF INBUF Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered

ProASIC3L DC and Switching Characteristics Table 2-187 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA Note: *See Figure 2-27 on page 2-107 for more information.

ProASIC3L Low Power Flash FPGAs Revision 13 2-109 Input Register Figure 2-28 • Input Register Timing Diagram 50% Preset Clear Out_1 CLK Data Enable tISUE 50% 50% tISUD tIHD 50% 50% tICLKQ 1 0 tIHE tIRECPRE tIREMPRE tIRECCLR tIREMCLRtIWCLR tIWPRE tIPRE2Q tICLR2Q tICKMPWH tICKMPWL 50% 50% 50% 50% 50% 50% 50% 50%

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-188 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.24 0.29 ns tISUD Data Setup Time for the Input Data Register 0.27 0.31 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.38 0.45 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.46 0.54 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.46 0.54 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.23 0.27 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.23 0.27 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 0.36 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-189 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.32 0.37 ns tISUD Data Setup Time for the Input Data Register 0.35 0.41 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.50 0.58 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.60 0.71 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.60 0.71 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.30 0.35 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.30 0.35 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 0.36 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-111 Output Register Figure 2-29 • Output Register Timing Diagram Preset Clear DOUT CLK Data_out Enable tOSUE 50% 50% tOSUD tOHD 50% 50% tOCLKQ 1 0 tOHE tORECPRE tOREMPRE tORECCLR tOREMCLRtOWCLR tOWPRE tOPRE2Q tOCLR2Q tOCKMPWH tOCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50%

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-190 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.60 0.71 ns tOSUD Data Setup Time for the Output Data Register 0.32 0.37 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.45 0.53 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.82 0.96 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.82 0.96 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.23 0.27 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.23 0.27 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-191 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.78 0.92 ns tOSUD Data Setup Time for the Output Data Register 0.42 0.49 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.58 0.69 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.07 1.26 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.07 1.26 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.30 0.35 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.30 0.35 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-113 Output Enable Register Figure 2-30 • Output Enable Register Timing Diagram 50% Preset Clear EOUT CLK D_Enable Enable tOESUE 50% 50% tOESUDtOEHD 50% 50% tOECLKQ 1 0 tOEHE tOERECPRE tOEREMPRE tOERECCLR tOEREMCLRtOEWCLR tOEWPRE tOEPRE2Q tOECLR2Q tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% 50%

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-192 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.45 0.53 ns tOESUD Data Setup Time for the Output Enable Register 0.32 0.37 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.44 0.52 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.68 0.80 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.68 0.80 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.23 0.27 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.23 0.27 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 0.36 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-193 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.70 ns tOESUD Data Setup Time for the Output Enable Register 0.42 0.49 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.58 0.68 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.89 1.04 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.89 1.04 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.30 0.35 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.30 0.35 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 0.36 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-115 DDR Module Specifications Input DDR Module Figure 2-31 • Input DDR Timing Model Table 2-194 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B Input DDR Data CLK CLKBUF INBUF Out_QF (to core) FF2 FF1 INBUF CLR DDR_IN E A B C D Out_QR (to core)

ProASIC3L DC and Switching Characteristics Timing Characteristics Figure 2-32 • Input DDR Timing Diagram tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRICLR2Q1 12 3 4 5 6 7 8 9 CLK Data CLR Out_QR Out_QF tDDRICLKQ1 2 4 6 3 5 7 tDDRIHDtDDRISUD tDDRICLKQ2 Table 2-195 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.28 0.33 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.40 0.47 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.29 0.34 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.25 0.29 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.47 0.55 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.58 0.68 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.23 0.27 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.18 0.22 ns tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.31 0.36 ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.28 0.32 ns FDDRIMAX Maximum Frequency for Input DDR 250.00 250.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-117 Table 2-196 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.43 0.37 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.61 0.52 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.44 0.38 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.39 0.33 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.73 0.62 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.89 0.76 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.35 0.30 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.19 ns tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.31 ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.28 ns FDDRIMAX Maximum Frequency for Input DDR 160.00 160.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Output DDR Module Figure 2-33 • Output DDR Timing Model Table 2-197 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B Data_F (from core) CLK CLKBUF Out FF2 INBUF CLR DDR_OUT Output DDR FF1 X X X X X X X A B D EC C B OUTBUFData_R (from core)

ProASIC3L Low Power Flash FPGAs Revision 13 2-119 Timing Characteristics Figure 2-34 • Output DDR Timing Diagram 116 91 0 28 3 9 tDDROREMCLR tDDROHD1tDDROREMCLR tDDROHD2tDDROSUD2 tDDROCLKQ tDDRORECCLR CLK Data_R Data_F CLR Out tDDROCLR2Q 71 0 4 Table 2-198 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.72 0.84 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.39 0.45 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.39 0.45 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.82 0.96 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.23 0.27 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 0.22 ns tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.31 0.36 ns tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.28 0.32 ns FDDOMAX Maximum Frequency for the Output DDR 250.00 250.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-199 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 1.10 0.94 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.59 0.50 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.59 0.50 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.26 1.07 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.35 0.30 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.19 ns tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.36 0.31 ns tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.32 0.28 ns FDDOMAX Maximum Frequency for the Output DDR 160.00 160.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-121 VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT- 3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO,® Fusion, and ProASIC3 Macro Library Guide. Figure 2-35 • Sample of Combinatorial Cells MAJ3 A C BY MUX2 B A S Y AY B B A XOR2 Y NOR2 B A Y B A YOR2 INV A YAND2 B A Y NAND3B A C XOR3 YB A C NAND2

ProASIC3L DC and Switching Characteristics Figure 2-36 • Timing Model and Waveforms tPD A B tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell YNAND2 or Any Combinatorial Logic t PD tPD 50% VCC VCC VCC 50% GNDA, B, C 50% 50% 50% (RR) (RF) GND OUT OUT GND 50% (FF) (FR) tPD tPD

ProASIC3L Low Power Flash FPGAs Revision 13 2-123 Timing Characteristics Table 2-200 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter –1 Std. Units INV Y =!A t PD 0.41 0.48 ns AND2 Y = A · B t PD 0.48 0.57 ns NAND2 Y =!(A · B) t PD 0.48 0.57 ns OR2 Y = A + B t PD 0.50 0.58 ns NOR2 Y =!(A + B) t PD 0.50 0.58 ns XOR2 Y = A Bt PD 0.75 0.88 ns MAJ3 Y = MAJ(A, B, C) t PD 0.71 0.84 ns XOR3 Y = A  B Ct PD 0.89 1.05 ns MUX2 Y = A !S + B S t PD 0.52 0.61 ns AND3 Y = A · B · C t PD 0.57 0.67 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-201 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Combinatorial Cell Equation Parameter –1 Std. Units INV Y = !A t PD 0.54 0.63 ns AND2 Y = A · B t PD 0.63 0.74 ns NAND2 Y = !(A · B) t PD 0.63 0.74 ns OR2 Y = A + B t PD 0.65 0.76 ns NOR2 Y = !(A + B) t PD 0.65 0.76 ns XOR2 Y = A Bt PD 0.98 1.16 ns MAJ3 Y = MAJ(A , B, C) t PD 0.93 1.09 ns XOR3 Y = A  B Ct PD 1.17 1.37 ns MUX2 Y = A !S + B S t PD 0.68 0.79 ns AND3 Y = A · B · C t PD 0.75 0.88 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-125 Timing Characteristics Table 2-202 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units t CLKQ Clock-to-Q of the Core Register 0.56 0.66 ns tSUD Data Setup Time for the Core Register 0.44 0.51 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.46 0.55 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.41 0.48 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.41 0.48 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.23 0.27 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.23 0.27 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-203 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.73 0.86 ns tSUD Data Setup Time for the Core Register 0.57 0.67 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.61 0.71 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.53 0.63 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.53 0.63 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.30 0.35 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.30 0.35 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-127 Global Resource Characteristics A3P250L Clock Tree Topology Clock delays are device-specific. Figure 2-39 is an example of a global tree used for clock routing. The global tree presented in Figure 2-39 is driven by a CCC located on the west side of the A3P250L device. It is used to drive all D-flip-flops in the device. Figure 2-39 • Example of Global Tree Use in an A3P250L Device for Clock Routing Central Global Rib VersaTile Rows Global Spine CCC

ProASIC3L DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-132 . Table 2-204 to Table 2-210 on page 2-131 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-204 • A3P250L Global Resource – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 0.82 1.06 0.96 1.25 ns tRCKH Input High Delay for Global Clock 0.80 1.09 0.94 1.28 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.88 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns tRCKSW Maximum Skew for Global Clock 0.29 0.34 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-205 • A3P250L Global Resource – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.40 1.68 1.64 1.97 ns tRCKH Input High Delay for Global Clock 1.38 1.71 1.62 2.01 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.05 1.24 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.23 1.44 ns tRCKSW Maximum Skew for Global Clock 0.33 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-129 Table 2-206 • A3P600L Global Resource – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 0.90 1.14 1.06 1.34 ns tRCKH Input High Delay for Global Clock 0.89 1.17 1.04 1.38 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.88 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns tRCKSW Maximum Skew for Global Clock 0.28 0.33 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-207 • A3P600L Global Resource – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.48 1.76 1.74 2.07 ns tRCKH Input High Delay for Global Clock 1.47 1.80 1.72 2.11 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.05 1.24 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.23 1.44 ns tRCKSW Maximum Skew for Global Clock 0.33 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-208 • A3P1000L Global Resource – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.02 1.26 1.20 1.48 ns tRCKH Input High Delay for Global Clock 1.01 1.29 1.18 1.52 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.88 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns tRCKSW Maximum Skew for Global Clock 0.28 0.33 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-209 • A3P1000L Global Resource – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.61 1.89 1.89 2.22 ns tRCKH Input High Delay for Global Clock 1.60 1.92 1.88 2.26 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.05 1.24 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.23 1.44 ns tRCKSW Maximum Skew for Global Clock 0.33 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-131 Table 2-210 • A3PE3000L Global Resource – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.53 1.75 1.79 2.06 ns tRCKH Input High Delay for Global Clock 1.51 1.77 1.78 2.08 ns tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.88 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns tRCKSW Maximum Skew for Global Clock 0.26 0.30 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-211 • A3PE3000L Global Resource – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.52 1.94 1.78 2.28 ns tRCKH Input High Delay for Global Clock 1.49 1.96 1.76 2.30 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.05 1.24 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.23 1.44 ns tRCKSW Maximum Skew for Global Clock 0.47 0.55 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Clock Conditioning Circuits Timing Characteristics Table 2-212 • ProASIC3L CCC/PLL Specification CCC/PLL Operating at 1.2 V Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency f IN_CCC 1.5 250 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 250 MHz Delay Increments in Programmable Delay Blocks 1, 2 270 3 ps Number of Programmable Values in Each Programmable Delay Block 32 Serial Clock (SCLK) for Dynamic PLL4 100 MHz Input Cycle-to-Cycle Jitter (peak magnitude) 1 ns CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter

1 Global

3 Global

0.75 MHz to 24 MHz 0.50% 0.75% 0.70% 24 MHz to 100 MHz 1.00% 1.50% 1.20% 100 MHz to 250 MHz 2.50% 3.75% 2.75% Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter LockControl = 0 2 ns LockControl = 1 1 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 1.2 15.65 ns Delay Range in Block: Programmable Delay 2 1, 2 0.025 15.65 ns Delay Range in Block: Fixed Delay 1, 2 3.1 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 for deratings. 2. T J = 25°C, VCC = 1.2 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help for more information. 4. Maximum value obtained for a –1 speed grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.

ProASIC3L Low Power Flash FPGAs Revision 13 2-133 Table 2-213 • ProASIC3L CCC/PLL Specification CCC/PLL Operating at 1.5 V Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz Delay Increments in Programmable Delay Blocks 1, 2 160 3 ps Serial Clock (SCLK) for Dynamic PLL 4 110 Number of Programmable Values in Each Programmable Delay Block 32 Input Period Jitter 1.5 ns CCC Output Peak-to-Peak Period Jitter F CCC_OUT Max Peak-to-Peak Period Jitter 0.75 MHz to 24 MHz 0.50% 0.70% 24 MHz to 100 MHz 1.00% 1.20% 100 MHz to 250 MHz 1.75% 2.00 250 MHz to 350 MHz 2.50% 5.60% Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter LockControl = 0 1.6 ns LockControl = 1 0.8 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 0.6 5.56 ns Delay Range in Block: Programmable Delay 2 1, 2 0.025 5.56 ns Delay Range in Block: Fixed Delay 1, 2 2.2 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 for deratings. 2. T J = 25°C, VCC = 1.5 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help for more information. 4. Maximum value obtained for a –1 speed grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-40 • Peak-to-Peak Jitter Definition Tperiod_max Tperiod_min Output Signal

ProASIC3L DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-41 • RAM Models ADDRA11 DOUTA8 DOUTA7 DOUTA0 DOUTB8 DOUTB7 DOUTB0 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RAM4K9 RADDR8 RD17 RADDR7 RD16 RADDR0 RD0 WD17 WD16 WD0 WW1 WW0 RW1 RW0 PIPE REN RCLK RAM512X18 WADDR8 WADDR7 WADDR0 WEN WCLK RESETRESET

ProASIC3L Low Power Flash FPGAs Revision 13 2-137 Figure 2-46 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18. CLK RESET DOUT|RD Dn tCYC tCKH tCKL tRSTBQ Dm

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-214 • RAM4K9 – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tAS Address setup time 0.25 0.30 ns tAH Address hold time 0.00 0.00 ns tENS REN, WEN setup time 0.15 0.17 ns tENH REN, WEN hold time 0.10 0.12 ns tBKS BLK setup time 0.24 0.28 ns tBKH BLK hold time 0.02 0.02 ns tDS Input data (DIN) setup time 0.19 0.22 ns tDH Input data (DIN) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 1.82 2.14 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 2.40 2.83 ns tCKQ2 Clock High to new data valid on DOUT (pipelined) 0.91 1.07 ns tC2CWWL

1 Address collision clk-to-clk delay for reliable write after write on same address –

applicable to closing edge 0.24 0.29 ns tC2CRWH

1 Address collision clk-to-clk delay for reliable read access after write on same

address – applicable to opening edge 0.20 0.24 ns tC2CWRH

1 Address collision clk-to-clk delay for re liable write access after read on same

address – applicable to opening edge 0.25 0.30 ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 0.94 1.11 ns RESET Low to data out Low on DOUT (pipelined) 0.94 1.11 ns tREMRSTB RESET removal 0.29 0.34 ns tRECRSTB RESET recovery 1.53 1.80 ns tMPWRSTB RESET minimum pulse width 0.55 0.64 ns tCYC Clock cycle time 5.10 5.87 ns FMAX Maximum frequency 196 170 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-139 Table 2-215 • RAM4K9 – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tAS Address setup time 0.33 0.39 ns tAH Address hold time 0.00 0.00 ns tENS REN, WEN setup time 0.19 0.22 ns tENH REN, WEN hold time 0.13 0.15 ns tBKS BLK setup time 0.31 0.36 ns tBKH BLK hold time 0.02 0.03 ns tDS Input data (DIN) setup time 0.24 0.29 ns tDH Input data (DIN) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 2.38 2.80 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 3.14 3.69 ns tCKQ2 Clock High to new data valid on DOUT (pipelined) 1.19 1.40 ns tC2CWWL applicable to closing edge 0.25 0.30 ns tC2CRWH address – applicable to opening edge 0.27 0.32 ns tC2CWRH address – applicable to opening edge 0.37 0.44 ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 1.23 1.45 ns RESET Low to data out Low on DOUT (pipelined) 1.23 1.45 ns tREMRSTB RESET removal 0.38 0.45 ns tRECRSTB RESET recovery 2.00 2.35 ns tMPWRSTB RESET minimum pulse width 0.63 0.72 ns tCYC Clock cycle time 5.75 6.61 ns FMAX Maximum frequency 174 151 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Table 2-216 • RAM512X18 – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tAS Address setup time 0.25 0.30 ns tAH Address hold time 0.00 0.00 ns tENS REN, WEN setup time 0.09 0.11 ns tENH REN, WEN hold time 0.06 0.07 ns tDS Input data (WD) setup time 0.19 0.22 ns tDH Input data (WD) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 2.20 2.59 ns tCKQ2 Clock High to new data valid on DO (pipelined) 0.91 1.07 ns tC2CRWH

1 Address collision clk-to-clk delay for re liable read access after write on same

address – applicable to opening edge 0.18 0.21 ns tC2CWRH address – applicable to opening edge 0.21 0.25 ns tRSTBQ RESET Low to data out Low on RD (flow through) 0.94 1.11 ns RESET Low to data out Low on RD (pipelined) 0.94 1.11 ns tREMRSTB RESET removal 0.29 0.34 ns tRECRSTB RESET recovery 1.53 1.80 ns tMPWRSTB RESET minimum pulse width 0.55 0.64 ns tCYC Clock cycle time 5.10 5.87 ns FMAX Maximum frequency 196 170 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-141 Table 2-217 • RAM512X18 – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tAS Address setup time 0.33 0.39 ns tAH Address hold time 0.00 0.00 ns tENS REN, WEN setup time 0.12 0.14 ns tENH REN, WEN hold time 0.08 0.09 ns tDS Input data (WD) setup time 0.24 0.29 ns tDH Input data (WD) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on RD (output retained, WMODE = 0) 2.88 3.39 ns tCKQ2 Clock High to new data valid on RD (pipelined) 1.19 1.40 ns tC2CRWH address – applicable to opening edge 0.25 0.29 ns tC2CWRH address – applicable to opening edge 0.31 0.36 ns tRSTBQ RESET Low to data out Low on RD (flow-through) 1.23 1.45 ns RESET Low to data out Low on RD (pipelined) 1.23 1.45 ns tREMRSTB RESET removal 0.38 0.45 ns tRECRSTB RESET recovery 2.00 2.35 ns tMPWRSTB RESET minimum pulse width 0.63 0.72 ns tCYC Clock cycle time 5.75 6.61 ns FMAX Maximum frequency 174 151 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values

ProASIC3L DC and Switching Characteristics FIFO Figure 2-47 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 WW0 RD0 ESTOP FSTOP FULL AFULL EMPTY AFVAL11 AEMPTY AFVAL10 AFVAL0 AEVAL11 AEVAL10 AEVAL0 REN RBLK RCLK WEN WBLK WCLK RPIPE WD17 WD16 WD0 RESET

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-218 • FIFO – Applies to 1.5 V DC Core Voltage Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –1 Std. Units tENS REN, WEN Setup Time 1.40 1.65 ns tENH REN, WEN Hold Time 0.02 0.02 ns tBKS BLK Setup Time 0.40 0.47 ns tBKH BLK Hold Time 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.19 0.22 ns tDH Input Data (WD) Hold Time 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.40 2.83 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.91 1.07 ns tRCKEF RCLK High to Empty Flag Valid 1.75 2.06 ns tWCKFF WCLK High to Full Flag Valid 1.66 1.96 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.31 7.42 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.73 2.03 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.25 7.35 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.94 1.11 ns RESET Low to Data Out Low on RD (pipelined) 0.94 1.11 ns t REMRSTB RESET Removal 0.29 0.34 ns tRECRSTB RESET Recovery 1.53 1.80 ns tMPWRSTB RESET Minimum Pulse Width 0.55 0.64 ns tCYC Clock Cycle Time 5.10 5.87 ns FMAX Maximum Frequency for FIFO 196 170 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L Low Power Flash FPGAs Revision 13 2-147 Table 2-219 • FIFO – Applies to 1.2 V DC Core Voltage Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description –1 Std. Units tENS REN, WEN Setup Time 1.84 2.16 ns tENH REN, WEN Hold Time 0.02 0.03 ns tBKS BLK Setup Time 0.40 0.47 ns tBKH BLK Hold Time 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.24 0.29 ns tDH Input Data (WD) Hold Time 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 3.14 3.69 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 1.19 1.40 ns tRCKEF RCLK High to Empty Flag Valid 2.29 2.69 ns tWCKFF WCLK High to Full Flag Valid 2.18 2.56 ns tCKAF Clock High to Almost Empty/Full Flag Valid 8.25 9.70 ns tRSTFG RESET Low to Empty/Full Flag Valid 2.26 2.65 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 8.17 9.60 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 1.23 1.45 ns RESET Low to Data Out Low on RD (pipelined) 1.23 1.45 ns t REMRSTB RESET Removal 0.38 0.45 ns tRECRSTB RESET Recovery 2.00 2.35 ns tMPWRSTB RESET Minimum Pulse Width 0.63 0.72 ns tCYC Clock Cycle Time 5.75 6.61 ns FMAX Maximum Frequency for FIFO 174 151 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

ProASIC3L DC and Switching Characteristics Embedded FlashROM Characteristics Timing Characteristics Figure 2-55 • Timing Diagram A0 A1 tSU tHOLD tSU tHOLD tSU tHOLD tCKQ2 tCKQ2 tCKQ2 CLK Address Data D0 D0 D1 Table 2-220 • Embedded FlashROM Access Time – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tSU Address Setup Time 0.54 0.64 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 16.55 19.46 ns FMAX Maximum Clock Frequency 15 15 MHz Table 2-221 • Embedded FlashROM Access Time– Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tSU Address Setup Time 0.71 0.83 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 21.64 25.44 ns FMAX Maximum Clock Frequency 15 15 MHz

ProASIC3L Low Power Flash FPGAs Revision 13 2-149 JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-18 for more details. Timing Characteristics Table 2-222 • JTAG 1532 – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tDISU Test Data Input Setup Time 0.57 0.67 ns tDIHD Test Data Input Hold Time 1.13 1.33 ns tTMSSU Test Mode Select Setup Time 0.57 0.67 ns tTMDHD Test Mode Select Hold Time 1.13 1.33 ns tTCK2Q Clock to Q (data out) 5.67 6.67 ns tRSTB2Q Reset to Q (data out) 22.67 26.67 ns FTCKMAX TCK Maximum Frequency 24.00 21.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.23 0.27 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-223 • JTAG 1532 – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tDISU Test Data Input Setup Time 0.75 0.88 ns tDIHD Test Data Input Hold Time 1.50 1.76 ns tTMSSU Test Mode Select Setup Time 0.75 0.88 ns tTMDHD Test Mode Select Hold Time 1.50 1.76 ns tTCK2Q Clock to Q (data out) 6.00 7.06 ns tRSTB2Q Reset to Q (data out) 25.00 29.41 ns FTCKMAX TCK Maximum Frequency 20.00 17.00 MHz tTRSTREM ResetB Removal Time 0.45 0.53 ns tTRSTREC ResetB Recovery Time 0.00 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

3 – Pin Descriptions and Packaging Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise orig inated from the output buffer ground domain. This minimizes the noise transfer within the package and im proves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.2 V or 1.5 V. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power operation when VCC is at 1.2 V. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on ProASIC3L low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V for ProASIC3 devices When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Deco upling section of the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the ProASIC3L FPGA Fabric User’s Guide for a complete board solution for the PLL analog power supply and ground. There is one VCCPLF pin on ProASIC3L devices. VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. There is one VCOMPLF pin on ProASIC3L devices.

Pin Descriptions and Packaging VJTAG JTAG Supply Voltage ProASIC3L devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating t he JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin t ogether with the TRST pin c ould be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boar ds, the board containing the device can be powered down, provided both VJTAG and VCC to the part rema in powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage ProASIC3Ldevices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. Duri ng normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows:

• Output buffer is disabled (with tristate value of high impedance)
• Input buffer is disabled (with tristate value of high impedance)
• Weak pull-up is programmed GL Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connecti vity in the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the ProASIC3L FPGA Fabric User’s Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For exampl e, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant global s. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the "I/O Structur es in IGLOO and ProASIC3 Devices" chapter of the ProASIC3L FPGA Fabric User’s Guide for an explanation of the naming of global pins. FF Flash*Freeze Mode Activation Pin Flash*Freeze mode is available on ProASIC3L devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O.

ProASIC3L Low Power Flash FPGAs Revision 13 3-3 When Flash*Freeze mode is used, the FF pin must not be left floating, to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single- ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signa l. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pul l-up. This default config uration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. Table 3-1 shows the Flash*Freeze pin location on the available packages ProASIC3L devices. The Flash*Freeze pin location is independent of device (except for the PQ208 package), allowing migration to larger or smaller devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology and Low Power Modes" chapter of the ProASIC3L FPGA Fabric User’s Guide for more information on I/O states during Flash*Freeze mode. Table 3-1 • Flash*Freeze Pin Location ProASIC3L Package Flash*Freeze Pin VQ100 27 FG144 L3 FG256 T3 FG324 R5 FG484 W6 FG896 AH4 PQ208 PQ208-A3P250 PQ208-A3P600L PQ208-A3P1000L PQ208-A3P3000L

Pin Descriptions and Packaging JTAG Pins ProASIC3L devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevent s JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-2 for more information. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP , and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull- down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 3-2 and must satisfy the parallel re sistance value requirement. The values in Table 3-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circui t could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200  to 1 k VJTAG at 2.5 V 200  to 1 k VJTAG at 1.8 V 500  to 1 k VJTAG at 1.5 V 500  to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down.

ProASIC3L Low Power Flash FPGAs Revision 13 3-5 Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability an d performance. Microsemi IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Microsemi offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. Related Documents User’s Guides ProASICL FPGA Fabric User’s Guide http://www.microsemi.com/soc/documents/PA3L_UG.pdf Packaging The following documents provide packaging information and device selection for low power flash devices. Product Catalog http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf This document contains the package mechanical dr awings for all packages currently or previously supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials: http://www.microsemi.com/soc/products/solutions/package/docs.aspx.

4 – Package Pin Assignments VQ100 Note For Package Manufacturing and Environmental information, visit the Resource Center at Note: This is the top view of the package. 100

Pin Number A3P250L Function 1G N D

2 GAA2/IO118UDB3

3 IO118VDB3

4 GAB2/IO117UDB3

5 IO117VDB3

6 GAC2/IO116UDB3

7 IO116VDB3

8 IO112PSB3

10 GFB1/IO109PDB3

11 GFB0/IO109NDB3

12 VCOMPLF

13 GFA0/IO108NPB3

14 VCCPLF

15 GFA1/IO108PPB3

16 GFA2/IO107PSB3

17 VCC

18 VCCIB3

19 GFC2/IO105PSB3

20 GEC1/IO100PDB3

21 GEC0/IO100NDB3

22 GEA1/IO98PDB3

23 GEA0/IO98NDB3

24 VMV3

25 GNDQ

26 GEA2/IO97RSB2

27 FF/GEB2/IO96RSB2

28 GEC2/IO95RSB2

29 IO93RSB2

30 IO92RSB2

31 IO91RSB2

32 IO90RSB2

33 IO88RSB2

34 IO86RSB2

35 IO85RSB2

36 IO84RSB2

37 VCC

38 GND

39 VCCIB2

40 IO77RSB2

41 IO74RSB2

42 IO71RSB2

43 GDC2/IO63RSB2

44 GDB2/IO62RSB2

45 GDA2/IO61RSB2

46 GNDQ

47 TCK

48 TDI

49 TMS

50 VMV2

51 GND

52 VPUMP

54 TDO

55 TRST

56 VJTAG

57 GDA1/IO60USB1

58 GDC0/IO58VDB1

59 GDC1/IO58UDB1

60 IO52NDB1

61 GCB2/IO52PDB1

62 GCA1/IO50PDB1

63 GCA0/IO50NDB1

64 GCC0/IO48NDB1

65 GCC1/IO48PDB1

66 VCCIB1

67 GND

68 VCC

69 IO43NDB1

70 GBC2/IO43PDB1

71 GBB2/IO42PSB1

72 IO41NDB1

Pin Number A3P250L Function

73 GBA2/IO41PDB1

74 VMV1

75 GNDQ

76 GBA1/IO40RSB0

77 GBA0/IO39RSB0

78 GBB1/IO38RSB0

79 GBB0/IO37RSB0

80 GBC1/IO36RSB0

81 GBC0/IO35RSB0

82 IO29RSB0

83 IO27RSB0

84 IO25RSB0

85 IO23RSB0

86 IO21RSB0

87 VCCIB0

88 GND

89 VCC

90 IO15RSB0

91 IO13RSB0

92 IO11RSB0

93 GAC1/IO05RSB0

94 GAC0/IO04RSB0

95 GAB1/IO03RSB0

96 GAB0/IO02RSB0

97 GAA1/IO01RSB0

98 GAA0/IO00RSB0

99 GNDQ

100 VMV0

Pin Number A3P250L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-3 PQ208 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the top view of the package. 208-Pin PQFP 1 208

Pin Number A3PL250 Function 1G N D

8 IO115UDB3

9 IO115VDB3

10 IO114UDB3

11 IO114VDB3

12 IO113PDB3

13 IO113NDB3

14 IO112PDB3

15 IO112NDB3

16 VCC

17 GND

19 IO111PDB3

20 IO111NDB3

21 GFC1/IO110PDB3

22 GFC0/IO110NDB3

23 GFB1/IO109PDB3

24 GFB0/IO109NDB3

25 VCOMPLF

26 GFA0/IO108NPB3

27 VCCPLF

28 GFA1/IO108PPB3

29 GND

30 GFA2/IO107PDB3

31 IO107NDB3

32 GFB2/IO106PDB3

33 IO106NDB3

34 GFC2/IO105PDB3

35 IO105NDB3

37 IO104PDB3

38 IO104NDB3

39 IO103PSB3

40 VCCIB3

41 GND

42 IO101PDB3

43 IO101NDB3

44 GEC1/IO100PDB3

45 GEC0/IO100NDB3

46 GEB1/IO99PDB3

47 GEB0/IO99NDB3

48 GEA1/IO98PDB3

49 GEA0/IO98NDB3

50 VMV3

51 GNDQ

52 GND

55 GEA2/IO97RSB2

56 FF/GEB2/IO96RSB2

57 GEC2/IO95RSB2

58 IO94RSB2

59 IO93RSB2

60 IO92RSB2

61 IO91RSB2

62 VCCIB2

63 IO90RSB2

64 IO89RSB2

65 GND

66 IO88RSB2

67 IO87RSB2

68 IO86RSB2

69 IO85RSB2

70 IO84RSB2

71 VCC

72 VCCIB2

Pin Number A3PL250 Function

73 IO83RSB2

74 IO82RSB2

75 IO81RSB2

76 IO80RSB2

77 IO79RSB2

78 IO78RSB2

79 IO77RSB2

80 IO76RSB2

81 GND

82 IO75RSB2

83 IO74RSB2

84 IO73RSB2

85 IO72RSB2

86 IO71RSB2

87 IO70RSB2

88 VCC

89 VCCIB2

90 IO69RSB2

91 IO68RSB2

92 IO67RSB2

93 IO66RSB2

94 IO65RSB2

95 IO64RSB2

96 GDC2/IO63RSB2

97 GND

98 GDB2/IO62RSB2

99 GDA2/IO61RSB2

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV2

105 GND

106 VPUMP

108 TDO

Pin Number A3PL250 Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-5

109 TRST

110 VJTAG

111 GDA0/IO60VDB1

112 GDA1/IO60UDB1

113 GDB0/IO59VDB1

114 GDB1/IO59UDB1

115 GDC0/IO58VDB1

116 GDC1/IO58UDB1

117 IO57VDB1

118 IO57UDB1

119 IO56NDB1

120 IO56PDB1

121 IO55RSB1

122 GND

123 VCCIB1

126 VCC

127 IO53NDB1

128 GCC2/IO53PDB1

129 GCB2/IO52PSB1

130 GND

131 GCA2/IO51PSB1

132 GCA1/IO50PDB1

133 GCA0/IO50NDB1

134 GCB0/IO49NDB1

135 GCB1/IO49PDB1

136 GCC0/IO48NDB1

137 GCC1/IO48PDB1

138 IO47NDB1

139 IO47PDB1

140 VCCIB1

141 GND

142 VCC

143 IO46RSB1

144 IO45NDB1

Pin Number A3PL250 Function

145 IO45PDB1

146 IO44NDB1

147 IO44PDB1

148 IO43NDB1

149 GBC2/IO43PDB1

150 IO42NDB1

151 GBB2/IO42PDB1

152 IO41NDB1

153 GBA2/IO41PDB1

154 VMV1

155 GNDQ

156 GND

158 GBA1/IO40RSB0

159 GBA0/IO39RSB0

160 GBB1/IO38RSB0

161 GBB0/IO37RSB0

162 GND

163 GBC1/IO36RSB0

164 GBC0/IO35RSB0

165 IO34RSB0

166 IO33RSB0

167 IO32RSB0

168 IO31RSB0

169 IO30RSB0

170 VCCIB0

171 VCC

172 IO29RSB0

173 IO28RSB0

174 IO27RSB0

175 IO26RSB0

176 IO25RSB0

177 IO24RSB0

178 GND

179 IO23RSB0

180 IO22RSB0

Pin Number A3PL250 Function

181 IO21RSB0

182 IO20RSB0

183 IO19RSB0

184 IO18RSB0

185 IO17RSB0

186 VCCIB0

187 VCC

188 IO16RSB0

189 IO15RSB0

190 IO14RSB0

191 IO13RSB0

192 IO12RSB0

193 IO11RSB0

194 IO10RSB0

195 GND

196 IO09RSB0

197 IO08RSB0

198 IO07RSB0

199 IO06RSB0

200 VCCIB0

201 GAC1/IO05RSB0

202 GAC0/IO04RSB0

203 GAB1/IO03RSB0

204 GAB0/IO02RSB0

205 GAA1/IO01RSB0

206 GAA0/IO00RSB0

207 GNDQ

208 VMV0

Pin Number A3PL250 Function

Pin Number A3PL600 Function 1G N D

2 GAA2/IO174PDB3

3 IO174NDB3

4 GAB2/IO173PDB3

5 IO173NDB3

6 GAC2/IO172PDB3

7 IO172NDB3

8 IO171PDB3

9 IO171NDB3

10 IO170PDB3

11 IO170NDB3

12 IO169PDB3

13 IO169NDB3

14 IO168PDB3

15 IO168NDB3

19 IO166PDB3

20 IO166NDB3

21 GFC1/IO164PDB3

22 GFC0/IO164NDB3

23 GFB1/IO163PDB3

24 GFB0/IO163NDB3

26 GFA0/IO162NPB3

28 GFA1/IO162PPB3

30 GFA2/IO161PDB3

31 IO161NDB3

32 GFB2/IO160PDB3

33 IO160NDB3

34 GFC2/IO159PDB3

35 IO159NDB3

36 VCC

37 IO152PDB3

38 IO152NDB3

39 IO150PSB3

42 IO147PDB3

43 IO147NDB3

44 GEC1/IO146PDB3

45 GEC0/IO146NDB3

46 GEB1/IO145PDB3

47 GEB0/IO145NDB3

48 GEA1/IO144PDB3

49 GEA0/IO144NDB3

53 VMV2

54 GEA2/IO143RSB2

55 FF/GEB2/IO142RSB2

56 GEC2/IO141RSB2

57 IO140RSB2

58 IO139RSB2

59 IO138RSB2

60 IO137RSB2

61 IO136RSB2

63 IO135RSB2

64 IO133RSB2

66 IO131RSB2

67 IO129RSB2

68 IO127RSB2

69 IO125RSB2

70 IO123RSB2

Pin Number A3PL600 Function

73 IO120RSB2

74 IO119RSB2

75 IO118RSB2

76 IO117RSB2

77 IO116RSB2

78 IO115RSB2

79 IO114RSB2

80 IO112RSB2

82 IO111RSB2

83 IO110RSB2

84 IO109RSB2

85 IO108RSB2

86 IO107RSB2

87 IO106RSB2

90 IO104RSB2

91 IO102RSB2

92 IO100RSB2

93 IO98RSB2

94 IO96RSB2

95 IO92RSB2

96 GDC2/IO91RSB2

98 GDB2/IO90RSB2

99 GDA2/IO89RSB2

107 GNDQ

Pin Number A3PL600 Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-7

111 GDA0/IO88NDB1

112 GDA1/IO88PDB1

113 GDB0/IO87NDB1

114 GDB1/IO87PDB1

115 GDC0/IO86NDB1

116 GDC1/IO86PDB1

117 IO84NDB1

118 IO84PDB1

119 IO82NDB1

120 IO82PDB1

121 IO81PSB1

124 IO77NDB1

125 IO77PDB1

127 IO74NDB1

128 GCC2/IO74PDB1

129 GCB2/IO73PSB1

131 GCA2/IO72PSB1

132 GCA1/IO71PDB1

133 GCA0/IO71NDB1

134 GCB0/IO70NDB1

135 GCB1/IO70PDB1

136 GCC0/IO69NDB1

137 GCC1/IO69PDB1

138 IO67NDB1

139 IO67PDB1

143 IO65PSB1

144 IO64NDB1

Pin Number A3PL600 Function

145 IO64PDB1

146 IO63NDB1

147 IO63PDB1

148 IO62NDB1

149 GBC2/IO62PDB1

150 IO61NDB1

151 GBB2/IO61PDB1

152 IO60NDB1

153 GBA2/IO60PDB1

157 VMV0

158 GBA1/IO59RSB0

159 GBA0/IO58RSB0

160 GBB1/IO57RSB0

161 GBB0/IO56RSB0

163 GBC1/IO55RSB0

164 GBC0/IO54RSB0

165 IO52RSB0

166 IO50RSB0

167 IO48RSB0

168 IO46RSB0

169 IO44RSB0

172 IO36RSB0

173 IO35RSB0

174 IO34RSB0

175 IO33RSB0

176 IO32RSB0

177 IO31RSB0

179 IO29RSB0

180 IO28RSB0

Pin Number A3PL600 Function

181 IO27RSB0

182 IO26RSB0

183 IO25RSB0

184 IO24RSB0

185 IO23RSB0

188 IO20RSB0

189 IO19RSB0

190 IO18RSB0

191 IO17RSB0

192 IO16RSB0

193 IO14RSB0

194 IO12RSB0

196 IO10RSB0

197 IO09RSB0

198 IO08RSB0

199 IO07RSB0

Pin Number A3PL600 Function

Pin Number APL1000 Function 1G N D

2 GAA2/IO225PDB3

3 IO225NDB3

4 GAB2/IO224PDB3

5 IO224NDB3

6 GAC2/IO223PDB3

7 IO223NDB3

8 IO222PDB3

9 IO222NDB3

10 IO220PDB3

11 IO220NDB3

12 IO218PDB3

13 IO218NDB3

14 IO216PDB3

15 IO216NDB3

19 IO212PDB3

20 IO212NDB3

21 GFC1/IO209PDB3

22 GFC0/IO209NDB3

23 GFB1/IO208PDB3

24 GFB0/IO208NDB3

26 GFA0/IO207NPB3

28 GFA1/IO207PPB3

30 GFA2/IO206PDB3

31 IO206NDB3

32 GFB2/IO205PDB3

33 IO205NDB3

34 GFC2/IO204PDB3

35 IO204NDB3

37 IO199PDB3

38 IO199NDB3

39 IO197PSB3

42 IO191PDB3

43 IO191NDB3

44 GEC1/IO190PDB3

45 GEC0/IO190NDB3

46 GEB1/IO189PDB3

47 GEB0/IO189NDB3

48 GEA1/IO188PDB3

49 GEA0/IO188NDB3

54 GEA2/IO187RSB2

55 FF/GEB2/IO186RSB2

56 GEC2/IO185RSB2

57 IO184RSB2

58 IO183RSB2

59 IO182RSB2

60 IO181RSB2

61 IO180RSB2

63 IO178RSB2

64 IO176RSB2

66 IO174RSB2

67 IO172RSB2

68 IO170RSB2

69 IO168RSB2

70 IO166RSB2

Pin Number APL1000 Function

73 IO162RSB2

74 IO160RSB2

75 IO158RSB2

76 IO156RSB2

77 IO154RSB2

78 IO152RSB2

79 IO150RSB2

80 IO148RSB2

82 IO143RSB2

83 IO141RSB2

84 IO139RSB2

85 IO137RSB2

86 IO135RSB2

87 IO133RSB2

90 IO128RSB2

91 IO126RSB2

92 IO124RSB2

93 IO122RSB2

94 IO120RSB2

95 IO118RSB2

96 GDC2/IO116RSB2

98 GDB2/IO115RSB2

99 GDA2/IO114RSB2

Pin Number APL1000 Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-9

111 GDA0/IO113NDB1

112 GDA1/IO113PDB1

113 GDB0/IO112NDB1

114 GDB1/IO112PDB1

115 GDC0/IO111NDB1

116 GDC1/IO111PDB1

117 IO109NDB1

118 IO109PDB1

119 IO106NDB1

120 IO106PDB1

121 IO104PSB1

124 IO99NDB1

125 IO99PDB1

127 IO96NDB1

128 GCC2/IO96PDB1

129 GCB2/IO95PSB1

131 GCA2/IO94PSB1

132 GCA1/IO93PDB1

133 GCA0/IO93NDB1

134 GCB0/IO92NDB1

135 GCB1/IO92PDB1

136 GCC0/IO91NDB1

137 GCC1/IO91PDB1

138 IO88NDB1

139 IO88PDB1

143 IO86PSB1

144 IO84NDB1

Pin Number APL1000 Function

145 IO84PDB1

146 IO82NDB1

147 IO82PDB1

148 IO80NDB1

149 GBC2/IO80PDB1

150 IO79NDB1

151 GBB2/IO79PDB1

152 IO78NDB1

153 GBA2/IO78PDB1

158 GBA1/IO77RSB0

159 GBA0/IO76RSB0

160 GBB1/IO75RSB0

161 GBB0/IO74RSB0

163 GBC1/IO73RSB0

164 GBC0/IO72RSB0

165 IO70RSB0

166 IO67RSB0

167 IO63RSB0

168 IO60RSB0

169 IO57RSB0

172 IO54RSB0

173 IO51RSB0

174 IO48RSB0

175 IO45RSB0

176 IO42RSB0

177 IO40RSB0

179 IO38RSB0

180 IO35RSB0

Pin Number APL1000 Function

181 IO33RSB0

182 IO31RSB0

183 IO29RSB0

184 IO27RSB0

185 IO25RSB0

188 IO22RSB0

189 IO20RSB0

191 IO16RSB0

192 IO15RSB0

194 IO13RSB0

196 IO12RSB0

197 IO11RSB0

198 IO10RSB0

199 IO09RSB0

Pin Number APL1000 Function

2 GNDQ

4 GAB2/IO308PSB7V4

5 GAA2/IO309PDB7V4

6 IO309NDB7V4

7 GAC2/IO307PDB7V4

8 IO307NDB7V4

9 IO303PDB7V3

10 IO303NDB7V3

11 IO299PDB7V3

12 IO299NDB7V3

13 IO295PDB7V2

14 IO295NDB7V2

15 IO291PSB7V2

18 VCCIB7

19 IO285PDB7V1

20 IO285NDB7V1

21 IO279PSB7V0

22 GFC1/IO275PSB7V0

23 GFB1/IO274PDB7V0

24 GFB0/IO274NDB7V0

26 GFA0/IO273NPB6V4

28 GFA1/IO273PPB6V4

30 GFA2/IO272PDB6V4

31 IO272NDB6V4

32 GFB2/IO271PPB6V4

33 GFC2/IO270PPB6V4

34 IO271NPB6V4

35 IO270NPB6V4

37 IO252PDB6V2

38 IO252NDB6V2

39 IO248PSB6V1

40 VCCIB6

42 IO244PDB6V1

43 IO244NDB6V1

44 GEC1/IO236PDB6V0

45 GEC0/IO236NDB6V0

46 GEB1/IO235PPB6V0

47 GEA1/IO234PPB6V0

48 GEB0/IO235NPB6V0

49 GEA0/IO234NPB6V0

50 VMV6

53 VMV5

54 GNDQ

55 IO233NDB5V4

56 GEA2/IO233PDB5V4

57 IO232NDB5V4

58 FF/GEB2/IO232PDB5V4

59 IO231NDB5V4

60 GEC2/IO231PDB5V4

61 IO230PSB5V4

62 VCCIB5

63 IO218NDB5V3

64 IO218PDB5V3

66 IO214PSB5V2

67 IO212NDB5V2

68 IO212PDB5V2

69 IO208NDB5V1

70 IO208PDB5V1

72 VCCIB5

73 IO202NDB5V1

74 IO202PDB5V1

75 IO198NDB5V0

76 IO198PDB5V0

77 IO197NDB5V0

78 IO197PDB5V0

79 IO194NDB5V0

80 IO194PDB5V0

82 IO184NDB4V3

83 IO184PDB4V3

84 IO180NDB4V3

85 IO180PDB4V3

86 IO176NDB4V2

87 IO176PDB4V2

89 VCCIB4

90 IO170NDB4V2

91 IO170PDB4V2

92 IO166NDB4V1

93 IO166PDB4V1

94 IO156NDB4V0

95 GDC2/IO156PDB4V0

96 IO154NPB4V0

98 GDB2/IO155PSB4V0

99 GDA2/IO154PPB4V0

104 VMV4

ProASIC3L Low Power Flash FPGAs Revision 13 4-11

111 VMV3

112 GDA0/IO153NPB3V4

113 GDB0/IO152NPB3V4

114 GDA1/IO153PPB3V4

115 GDB1/IO152PPB3V4

116 GDC0/IO151NDB3V4

117 GDC1/IO151PDB3V4

118 IO134NDB3V2

119 IO134PDB3V2

120 IO132NDB3V2

121 IO132PDB3V2

123 VCCIB3

124 GCC2/IO117PSB3V0

125 GCB2/IO116PSB3V0

127 IO115NDB3V0

128 GCA2/IO115PDB3V0

129 GCA1/IO114PPB3V0

131 VCCPLC

132 GCA0/IO114NPB3V0

133 VCOMPLC

134 GCB0/IO113NDB2V3

135 GCB1/IO113PDB2V3

136 GCC1/IO112PSB2V3

137 IO110NDB2V3

138 IO110PDB2V3

139 IO106PSB2V3

140 VCCIB2

143 IO99NDB2V2

144 IO99PDB2V2

145 IO96NDB2V1

146 IO96PDB2V1

147 IO91NDB2V1

148 IO91PDB2V1

149 IO88NDB2V0

150 IO88PDB2V0

151 GBC2/IO84PSB2V0

152 GBA2/IO82PSB2V0

153 GBB2/IO83PSB2V0

154 VMV2

157 VMV1

158 GNDQ

159 GBA1/IO81PDB1V4

160 GBA0/IO81NDB1V4

161 GBB1/IO80PDB1V4

163 GBB0/IO80NDB1V4

164 GBC1/IO79PDB1V4

165 GBC0/IO79NDB1V4

166 IO74PDB1V4

167 IO74NDB1V4

168 IO70PDB1V3

169 IO70NDB1V3

170 VCCIB1

172 IO56PSB1V1

173 IO55PDB1V1

174 IO55NDB1V1

175 IO54PDB1V1

176 IO54NDB1V1

177 IO40PDB0V4

179 IO40NDB0V4

180 IO37PDB0V4

181 IO37NDB0V4

182 IO35PDB0V4

183 IO35NDB0V4

184 IO32PDB0V3

185 IO32NDB0V3

188 IO28PDB0V3

189 IO28NDB0V3

190 IO24PDB0V2

191 IO24NDB0V2

192 IO21PSB0V2

193 IO16PDB0V1

194 IO16NDB0V1

196 IO11PDB0V1

197 IO11NDB0V1

198 IO08PDB0V0

199 IO08NDB0V0

201 GAC1/IO02PDB0V0

202 GAC0/IO02NDB0V0

203 GAB1/IO01PDB0V0

204 GAB0/IO01NDB0V0

205 GAA1/IO00PDB0V0

206 GAA0/IO00NDB0V0

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. 123456789101112 A B C D E F G H J K L M A1 Ball Pad Corner

ProASIC3L Low Power Flash FPGAs Revision 13 4-13 FG144 Pin Number A3P250L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO29RSB0 A8 VCC A9 IO33RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO117UDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO14RSB0 B6 IO19RSB0 B7 IO22RSB0 B8 IO30RSB0 B9 GBB0/IO37RSB0 B10 GBB1/IO38RSB0 B11 GND B12 VMV1 C1 IO117VDB3 C2 GFA2/IO107PPB3 C3 GAC2/IO116UDB3 C4 VCC C5 IO12RSB0 C6 IO17RSB0 C7 IO24RSB0 C8 IO31RSB0 C9 IO34RSB0 C10 GBA2/IO41PDB1 C11 IO41NDB1 C12 GBC2/IO43PPB1 D1 IO112NDB3 D2 IO112PDB3 D3 IO116VDB3 D4 GAA2/IO118UPB3 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO35RSB0 D8 GBC1/IO36RSB0 D9 GBB2/IO42PDB1 D10 IO42NDB1 D11 IO43NPB1 D12 GCB1/IO49PPB1 E1 VCC E2 GFC0/IO110NDB3 E3 GFC1/IO110PDB3 E4 VCCIB3 E5 IO118VPB3 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO48PDB1 E9 VCCIB1 E10 VCC E11 GCA0/IO50NDB1 E12 IO51NDB1 F1 GFB0/IO109NPB3 F2 VCOMPLF F3 GFB1/IO109PPB3 F4 IO107NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO48NDB1 F9 GCB0/IO49NPB1 F10 GND F11 GCA1/IO50PDB1 F12 GCA2/IO51PDB1 FG144 Pin Number A3P250L Function G1 GFA1/IO108PPB3 G2 GND G3 VCCPLF G4 GFA0/IO108NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO58UPB1 G9 IO53NDB1 G10 GCC2/IO53PDB1 G11 IO52NDB1 G12 GCB2/IO52PDB1 H1 VCC H2 GFB2/IO106PDB3 H3 GFC2/IO105PSB3 H4 GEC1/IO100PDB3 H5 VCC H6 IO79RSB2 H7 IO65RSB2 H8 GDB2/IO62RSB2 H9 GDC0/IO58VPB1 H10 VCCIB1 H11 IO54PSB1 H12 VCC J1 GEB1/IO99PDB3 J2 IO106NDB3 J3 VCCIB3 J4 GEC0/IO100NDB3 J5 IO88RSB2 J6 IO81RSB2 J7 VCC J8 TCK J9 GDA2/IO61RSB2 J10 TDO J11 GDA1/IO60UDB1 J12 GDB1/IO59UDB1 FG144 Pin Number A3P250L Function

Pin Number A3P250L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-15 FG144 Pin Number A3P600L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO34RSB0 A8 VCC A9 IO50RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO173PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO13RSB0 B6 IO19RSB0 B7 IO31RSB0 B8 IO39RSB0 B9 GBB0/IO56RSB0 B10 GBB1/IO57RSB0 B11 GND B12 VMV1 C1 IO173NDB3 C2 GFA2/IO161PPB3 C3 GAC2/IO172PDB3 C4 VCC C5 IO16RSB0 C6 IO25RSB0 C7 IO28RSB0 C8 IO42RSB0 C9 IO45RSB0 C10 GBA2/IO60PDB1 C11 IO60NDB1 C12 GBC2/IO62PPB1 D1 IO169PDB3 D2 IO169NDB3 D3 IO172NDB3 D4 GAA2/IO174PPB3 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO54RSB0 D8 GBC1/IO55RSB0 D9 GBB2/IO61PDB1 D10 IO61NDB1 D11 IO62NPB1 D12 GCB1/IO70PPB1 E1 VCC E2 GFC0/IO164NDB3 E3 GFC1/IO164PDB3 E4 VCCIB3 E5 IO174NPB3 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO69PDB1 E9 VCCIB1 E10 VCC E11 GCA0/IO71NDB1 E12 IO72NDB1 F1 GFB0/IO163NPB3 F2 VCOMPLF F3 GFB1/IO163PPB3 F4 IO161NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO69NDB1 F9 GCB0/IO70NPB1 F10 GND F11 GCA1/IO71PDB1 F12 GCA2/IO72PDB1 FG144 Pin Number A3P600L Function G1 GFA1/IO162PPB3 G2 GND G3 VCCPLF G4 GFA0/IO162NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO86PPB1 G9 IO74NDB1 G10 GCC2/IO74PDB1 G11 IO73NDB1 G12 GCB2/IO73PDB1 H1 VCC H2 GFB2/IO160PDB3 H3 GFC2/IO159PSB3 H4 GEC1/IO146PDB3 H5 VCC H6 IO80PDB1 H7 IO80NDB1 H8 GDB2/IO90RSB2 H9 GDC0/IO86NPB1 H10 VCCIB1 H11 IO84PSB1 H12 VCC J1 GEB1/IO145PDB3 J2 IO160NDB3 J3 VCCIB3 J4 GEC0/IO146NDB3 J5 IO129RSB2 J6 IO131RSB2 J7 VCC J8 TCK J9 GDA2/IO89RSB2 J10 TDO J11 GDA1/IO88PDB1 J12 GDB1/IO87PDB1 FG144 Pin Number A3P600L Function

Pin Number A3P600L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-17 FG144 Pin Number A3P1000L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 A8 VCC A9 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO13RSB0 B6 IO26RSB0 B7 IO35RSB0 B8 IO60RSB0 B9 GBB0/IO74RSB0 B10 GBB1/IO75RSB0 B11 GND B12 VMV1 C1 IO224NDB3 C2 GFA2/IO206PPB3 C3 GAC2/IO223PDB3 C4 VCC C5 IO16RSB0 C6 IO29RSB0 C7 IO32RSB0 C8 IO63RSB0 C9 IO66RSB0 C10 GBA2/IO78PDB1 C11 IO78NDB1 C12 GBC2/IO80PPB1 D1 IO213PDB3 D2 IO213NDB3 D3 IO223NDB3 D4 GAA2/IO225PPB3 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO72RSB0 D8 GBC1/IO73RSB0 D9 GBB2/IO79PDB1 D10 IO79NDB1 D11 IO80NPB1 D12 GCB1/IO92PPB1 E1 VCC E2 GFC0/IO209NDB3 E3 GFC1/IO209PDB3 E4 VCCIB3 E5 IO225NPB3 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO91PDB1 E9 VCCIB1 E10 VCC E11 GCA0/IO93NDB1 E12 IO94NDB1 F1 GFB0/IO208NPB3 F2 VCOMPLF F3 GFB1/IO208PPB3 F4 IO206NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO91NDB1 F9 GCB0/IO92NPB1 F10 GND F11 GCA1/IO93PDB1 F12 GCA2/IO94PDB1 FG144 Pin Number A3P1000L Function G1 GFA1/IO207PPB3 G2 GND G3 VCCPLF G4 GFA0/IO207NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO111PPB1 G9 IO96NDB1 G10 GCC2/IO96PDB1 G11 IO95NDB1 G12 GCB2/IO95PDB1 H1 VCC H2 GFB2/IO205PDB3 H3 GFC2/IO204PSB3 H4 GEC1/IO190PDB3 H5 VCC H6 IO105PDB1 H7 IO105NDB1 H8 GDB2/IO115RSB2 H9 GDC0/IO111NPB1 H10 VCCIB1 H11 IO101PSB1 H12 VCC J1 GEB1/IO189PDB3 J2 IO205NDB3 J3 VCCIB3 J4 GEC0/IO190NDB3 J5 IO160RSB2 J6 IO157RSB2 J7 VCC J8 TCK J9 GDA2/IO114RSB2 J10 TDO J11 GDA1/IO113PDB1 J12 GDB1/IO112PDB1 FG144 Pin Number A3P1000L Function

Pin Number A3P1000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-19 FG256 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. 13579111315 246810121416 C E G J L N R D F H K M P T B A A1 Ball Pad Corner

Pin Number A3P250L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO07RSB0 A6 IO10RSB0 A7 IO11RSB0 A8 IO15RSB0 A9 IO20RSB0 A10 IO25RSB0 A11 IO29RSB0 A12 IO33RSB0 A13 GBB1/IO38RSB0 A14 GBA0/IO39RSB0 A15 GBA1/IO40RSB0 A16 GND B1 GAB2/IO117UDB3 B2 GAA2/IO118UDB3 B3 NC B4 GAB1/IO03RSB0 B5 IO06RSB0 B6 IO09RSB0 B7 IO12RSB0 B8 IO16RSB0 B9 IO21RSB0 B10 IO26RSB0 B11 IO30RSB0 B12 GBC1/IO36RSB0 B13 GBB0/IO37RSB0 B14 NC B15 GBA2/IO41PDB1 B16 IO41NDB1 C1 IO117VDB3 C2 IO118VDB3 C3 NC C4 NC C5 GAC0/IO04RSB0 C6 GAC1/IO05RSB0 C7 IO13RSB0 C8 IO17RSB0 C9 IO22RSB0 C10 IO27RSB0 C11 IO31RSB0 C12 GBC0/IO35RSB0 C13 IO34RSB0 C14 NC C15 IO42NPB1 C16 IO44PDB1 D1 IO114VDB3 D2 IO114UDB3 D3 GAC2/IO116UDB3 D4 NC D5 GNDQ D6 IO08RSB0 D7 IO14RSB0 D8 IO18RSB0 D9 IO23RSB0 D10 IO28RSB0 D11 IO32RSB0 D12 GNDQ D13 NC D14 GBB2/IO42PPB1 D15 NC D16 IO44NDB1 E1 IO113PDB3 E2 NC E3 IO116VDB3 E4 IO115UDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO19RSB0 FG256 Pin Number A3P250L Function E9 IO24RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO43PDB1 E14 IO46RSB1 E15 NC E16 IO45PDB1 F1 IO113NDB3 F2 IO112PPB3 F3 NC F4 IO115VDB3 F5 VCCIB3 F6 GND F7 VCC F8 VCC F9 VCC F10 VCC F11 GND F12 VCCIB1 F13 IO43NDB1 F14 NC F15 IO47PPB1 F16 IO45NDB1 G1 IO111NDB3 G2 IO111PDB3 G3 IO112NPB3 G4 GFC1/IO110PPB3 G5 VCCIB3 G6 VCC G7 GND G8 GND G9 GND G10 GND G11 VCC G12 VCCIB1 FG256 Pin Number A3P250L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-21 G13 GCC1/IO48PPB1 G14 IO47NPB1 G15 IO54PDB1 G16 IO54NDB1 H1 GFB0/IO109NPB3 H2 GFA0/IO108NDB3 H3 GFB1/IO109PPB3 H4 VCOMPLF H5 GFC0/IO110NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO48NPB1 H13 GCB1/IO49PPB1 H14 GCA0/IO50NPB1 H15 NC H16 GCB0/IO49NPB1 J1 GFA2/IO107PPB3 J2 GFA1/IO108PDB3 J3 VCCPLF J4 IO106NDB3 J5 GFB2/IO106PDB3 J6 VCC J7 GND J8 GND J9 GND J10 GND J11 VCC J12 GCB2/IO52PPB1 J13 GCA1/IO50PPB1 J14 GCC2/IO53PPB1 J15 NC J16 GCA2/IO51PDB1 FG256 Pin Number A3P250L Function K1 GFC2/IO105PDB3 K2 IO107NPB3 K3 IO104PPB3 K4 NC K5 VCCIB3 K6 VCC K7 GND K8 GND K9 GND K10 GND K11 VCC K12 VCCIB1 K13 IO52NPB1 K14 IO55RSB1 K15 IO53NPB1 K16 IO51NDB1 L1 IO105NDB3 L2 IO104NPB3 L3 NC L4 IO102RSB3 L5 VCCIB3 L6 GND L7 VCC L8 VCC L9 VCC L10 VCC L11 GND L12 VCCIB1 L13 GDB0/IO59VPB1 L14 IO57VDB1 L15 IO57UDB1 L16 IO56PDB1 M1 IO103PDB3 M2 NC M3 IO101NPB3 M4 GEC0/IO100NPB3 FG256 Pin Number A3P250L Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 NC M9 IO74RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 NC M14 GDB1/IO59UPB1 M15 GDC1/IO58UDB1 M16 IO56NDB1 N1 IO103NDB3 N2 IO101PPB3 N3 GEC1/IO100PPB3 N4 NC N5 GNDQ N6 GEA2/IO97RSB2 N7 IO86RSB2 N8 IO82RSB2 N9 IO75RSB2 N10 IO69RSB2 N11 IO64RSB2 N12 GNDQ N13 NC N14 VJTAG N15 GDC0/IO58VDB1 N16 GDA1/IO60UDB1 P1 GEB1/IO99PDB3 P2 GEB0/IO99NDB3 P3 NC P4 NC P5 IO92RSB2 P6 IO89RSB2 P7 IO85RSB2 P8 IO81RSB2 FG256 Pin Number A3P250L Function

Pin Number A3P250L Function T13 IO67RSB2 T14 GDA2/IO61RSB2 T15 TMS T16 GND FG256 Pin Number A3P250L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-23 FG256 Pin Number A3P600L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO11RSB0 A6 IO16RSB0 A7 IO18RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 GND B1 GAB2/IO173PDB3 B2 GAA2/IO174PDB3 B3 GNDQ B4 GAB1/IO03RSB0 B5 IO13RSB0 B6 IO14RSB0 B7 IO21RSB0 B8 IO27RSB0 B9 IO32RSB0 B10 IO38RSB0 B11 IO42RSB0 B12 GBC1/IO55RSB0 B13 GBB0/IO56RSB0 B14 IO52RSB0 B15 GBA2/IO60PDB1 B16 IO60NDB1 C1 IO173NDB3 C2 IO174NDB3 C3 VMV3 C4 IO07RSB0 C5 GAC0/IO04RSB0 C6 GAC1/IO05RSB0 C7 IO20RSB0 C8 IO24RSB0 C9 IO33RSB0 C10 IO39RSB0 C11 IO44RSB0 C12 GBC0/IO54RSB0 C13 IO51RSB0 C14 VMV0 C15 IO61NPB1 C16 IO63PDB1 D1 IO171NDB3 D2 IO171PDB3 D3 GAC2/IO172PDB3 D4 IO06RSB0 D5 GNDQ D6 IO10RSB0 D7 IO19RSB0 D8 IO26RSB0 D9 IO30RSB0 D10 IO40RSB0 D11 IO45RSB0 D12 GNDQ D13 IO50RSB0 D14 GBB2/IO61PPB1 D15 IO53RSB0 D16 IO63NDB1 E1 IO166PDB3 E2 IO167NPB3 E3 IO172NDB3 E4 IO169NDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO25RSB0 FG256 Pin Number A3P600L Function E9 IO31RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO62PDB1 E14 IO67PPB1 E15 IO64PPB1 E16 IO66PDB1 F1 IO166NDB3 F2 IO168NPB3 F3 IO167PPB3 F4 IO169PDB3 F5 VCCIB3 F6 GND F7 VCC F8 VCC F9 VCC F10 VCC F11 GND F12 VCCIB1 F13 IO62NDB1 F14 IO64NPB1 F15 IO65PPB1 F16 IO66NDB1 G1 IO165NDB3 G2 IO165PDB3 G3 IO168PPB3 G4 GFC1/IO164PPB3 G5 VCCIB3 G6 VCC G7 GND G8 GND G9 GND G10 GND G11 VCC G12 VCCIB1 FG256 Pin Number A3P600L Function

Pin Number A3P600L Function K1 GFC2/IO159PDB3 K2 IO161NPB3 K3 IO156PPB3 K4 IO129RSB2 K5 VCCIB3 K6 VCC K7 GND K8 GND K9 GND K10 GND K11 VCC K12 VCCIB1 K13 IO73NPB1 K14 IO80NPB1 K15 IO74NPB1 K16 IO72NDB1 L1 IO159NDB3 L2 IO156NPB3 L3 IO151PPB3 L4 IO158PSB3 L5 VCCIB3 L6 GND L7 VCC L8 VCC L9 VCC L10 VCC L11 GND L12 VCCIB1 L13 GDB0/IO87NPB1 L14 IO85NDB1 L15 IO85PDB1 L16 IO84PDB1 M1 IO150PDB3 M2 IO151NPB3 M3 IO147NPB3 M4 GEC0/IO146NPB3 FG256 Pin Number A3P600L Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 IO117RSB2 M9 IO110RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 IO94RSB2 M14 GDB1/IO87PPB1 M15 GDC1/IO86PDB1 M16 IO84NDB1 N1 IO150NDB3 N2 IO147PPB3 N3 GEC1/IO146PPB3 N4 IO140RSB2 N5 GNDQ N6 GEA2/IO143RSB2 N7 IO126RSB2 N8 IO120RSB2 N9 IO108RSB2 N10 IO103RSB2 N11 IO99RSB2 N12 GNDQ N13 IO92RSB2 N14 VJTAG N15 GDC0/IO86NDB1 N16 GDA1/IO88PDB1 P1 GEB1/IO145PDB3 P2 GEB0/IO145NDB3 P3 VMV2 P4 IO138RSB2 P5 IO136RSB2 P6 IO131RSB2 P7 IO124RSB2 P8 IO119RSB2 FG256 Pin Number A3P600L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-25 P9 IO107RSB2 P10 IO104RSB2 P11 IO97RSB2 P12 VMV1 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO88NDB1 R1 GEA1/IO144PDB3 R2 GEA0/IO144NDB3 R3 IO139RSB2 R4 GEC2/IO141RSB2 R5 IO132RSB2 R6 IO127RSB2 R7 IO121RSB2 R8 IO114RSB2 R9 IO109RSB2 R10 IO105RSB2 R11 IO98RSB2 R12 IO96RSB2 R13 GDB2/IO90RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO137RSB2 T3 FF/GEB2/IO142RSB T4 IO134RSB2 T5 IO125RSB2 T6 IO123RSB2 T7 IO118RSB2 T8 IO115RSB2 T9 IO111RSB2 T10 IO106RSB2 T11 IO102RSB2 FG256 Pin Number A3P600L Function T12 GDC2/IO91RSB2 T13 IO93RSB2 T14 GDA2/IO89RSB2 T15 TMS T16 GND FG256 Pin Number A3P600L Function

Pin Number A3P1000L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO22RSB0 A7 IO28RSB0 A8 IO35RSB0 A9 IO45RSB0 A10 IO50RSB0 A11 IO55RSB0 A12 IO61RSB0 A13 GBB1/IO75RSB0 A14 GBA0/IO76RSB0 A15 GBA1/IO77RSB0 A16 GND B1 GAB2/IO224PDB3 B2 GAA2/IO225PDB3 B3 GNDQ B4 GAB1/IO03RSB0 B5 IO17RSB0 B6 IO21RSB0 B7 IO27RSB0 B8 IO34RSB0 B9 IO44RSB0 B10 IO51RSB0 B11 IO57RSB0 B12 GBC1/IO73RSB0 B13 GBB0/IO74RSB0 B14 IO71RSB0 B15 GBA2/IO78PDB1 B16 IO81PDB1 C1 IO224NDB3 C2 IO225NDB3 C3 VMV3 C4 IO11RSB0 C5 GAC0/IO04RSB0 C6 GAC1/IO05RSB0 C7 IO25RSB0 C8 IO36RSB0 C9 IO42RSB0 C10 IO49RSB0 C11 IO56RSB0 C12 GBC0/IO72RSB0 C13 IO62RSB0 C14 VMV0 C15 IO78NDB1 C16 IO81NDB1 D1 IO222NDB3 D2 IO222PDB3 D3 GAC2/IO223PDB3 D4 IO223NDB3 D5 GNDQ D6 IO23RSB0 D7 IO29RSB0 D8 IO33RSB0 D9 IO46RSB0 D10 IO52RSB0 D11 IO60RSB0 D12 GNDQ D13 IO80NDB1 D14 GBB2/IO79PDB1 D15 IO79NDB1 D16 IO82NSB1 E1 IO217PDB3 E2 IO218PDB3 E3 IO221NDB3 E4 IO221PDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO38RSB0 FG256 Pin Number A3P1000L Function E9 IO47RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO80PDB1 E14 IO83PPB1 E15 IO86PPB1 E16 IO87PDB1 F1 IO217NDB3 F2 IO218NDB3 F3 IO216PDB3 F4 IO216NDB3 F5 VCCIB3 F6 GND F7 VCC F8 VCC F9 VCC F10 VCC F11 GND F12 VCCIB1 F13 IO83NPB1 F14 IO86NPB1 F15 IO90PPB1 F16 IO87NDB1 G1 IO210PSB3 G2 IO213NDB3 G3 IO213PDB3 G4 GFC1/IO209PPB3 G5 VCCIB3 G6 VCC G7 GND G8 GND G9 GND G10 GND G11 VCC G12 VCCIB1 FG256 Pin Number A3P1000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-27 G13 GCC1/IO91PPB1 G14 IO90NPB1 G15 IO88PDB1 G16 IO88NDB1 H1 GFB0/IO208NPB3 H2 GFA0/IO207NDB3 H3 GFB1/IO208PPB3 H4 VCOMPLF H5 GFC0/IO209NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO91NPB1 H13 GCB1/IO92PPB1 H14 GCA0/IO93NPB1 H15 IO96NPB1 H16 GCB0/IO92NPB1 J1 GFA2/IO206PSB3 J2 GFA1/IO207PDB3 J3 VCCPLF J4 IO205NDB3 J5 GFB2/IO205PDB3 J6 VCC J7 GND J8 GND J9 GND J10 GND J11 VCC J12 GCB2/IO95PPB1 J13 GCA1/IO93PPB1 J14 GCC2/IO96PPB1 J15 IO100PPB1 J16 GCA2/IO94PSB1 FG256 Pin Number A3P1000L Function K1 GFC2/IO204PDB3 K2 IO204NDB3 K3 IO203NDB3 K4 IO203PDB3 K5 VCCIB3 K6 VCC K7 GND K8 GND K9 GND K10 GND K11 VCC K12 VCCIB1 K13 IO95NPB1 K14 IO100NPB1 K15 IO102NDB1 K16 IO102PDB1 L1 IO202NDB3 L2 IO202PDB3 L3 IO196PPB3 L4 IO193PPB3 L5 VCCIB3 L6 GND L7 VCC L8 VCC L9 VCC L10 VCC L11 GND L12 VCCIB1 L13 GDB0/IO112NPB1 L14 IO106NDB1 L15 IO106PDB1 L16 IO107PDB1 M1 IO197NSB3 M2 IO196NPB3 M3 IO193NPB3 M4 GEC0/IO190NPB3 FG256 Pin Number A3P1000L Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 IO147RSB2 M9 IO136RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 IO110NDB1 M14 GDB1/IO112PPB1 M15 GDC1/IO111PDB1 M16 IO107NDB1 N1 IO194PSB3 N2 IO192PPB3 N3 GEC1/IO190PPB3 N4 IO192NPB3 N5 GNDQ N6 GEA2/IO187RSB2 N7 IO161RSB2 N8 IO155RSB2 N9 IO141RSB2 N10 IO129RSB2 N11 IO124RSB2 N12 GNDQ N13 IO110PDB1 N14 VJTAG N15 GDC0/IO111NDB1 N16 GDA1/IO113PDB1 P1 GEB1/IO189PDB3 P2 GEB0/IO189NDB3 P3 VMV2 P4 IO179RSB2 P5 IO171RSB2 P6 IO165RSB2 P7 IO159RSB2 P8 IO151RSB2 FG256 Pin Number A3P1000L Function

Pin Number A3P1000L Function T12 GDC2/IO116RSB2 T13 IO120RSB2 T14 GDA2/IO114RSB2 T15 TMS T16 GND FG256 Pin Number A3P1000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-29 FG324 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. 13579111315 246810121416 C E G J L N R D F H K M P T B A 1718 U V A1 Ball Pad Corner

ProASIC3L Low Power Flash FPGAs Revision 13 4-31 F12 IO58PDB1V2 F13 IO94PPB2V1 F14 VCOMPLB F15 GBC2/IO84PDB2V0 F16 IO84NDB2V0 F17 IO92NDB2V1 F18 IO92PDB2V1 G1 GND G2 IO287PDB7V1 G3 IO287NDB7V1 G4 IO283PPB7V1 G5 VCCIB7 G6 IO279PDB7V0 G7 IO291NPB7V2 G8 VCC G9 IO26NDB0V3 G10 IO34NDB0V4 G11 VCC G12 IO94NPB2V1 G13 IO98PDB2V2 G14 VCCIB2 G15 GCC0/IO112NPB2V3 G16 IO104PDB2V2 G17 IO104NDB2V2 G18 GND H1 IO267PDB6V4 H2 VCCIB7 H3 IO283NPB7V1 H4 GFB1/IO274PPB7V0 H5 GND H6 IO279NDB7V0 H7 VCC H8 VCC H9 GND H10 GND FG324 Pin Number A3PE3000L Function H11 VCC H12 VCC H13 IO98NDB2V2 H14 GND H15 GCB1/IO113PDB2V3 H16 GCC1/IO112PPB2V3 H17 VCCIB2 H18 IO108PDB2V3 J1 IO267NDB6V4 J2 GFA0/IO273NDB6V4 J3 VCOMPLF J4 GFA2/IO272PDB6V4 J5 GFB0/IO274NPB7V0 J6 GFC0/IO275NDB7V0 J7 GFC1/IO275PDB7V0 J8 GND J9 GND J10 GND J11 GND J12 GCA2/IO115PDB3V0 J13 GCA1/IO114PDB3V0 J14 GCA0/IO114NDB3V0 J15 GCB0/IO113NDB2V3 J16 VCOMPLC J17 IO120NPB3V0 J18 IO108NDB2V3 K1 IO263PDB6V3 K2 GFA1/IO273PDB6V4 K3 VCCPLF K4 IO272NDB6V4 K5 GFC2/IO270PPB6V4 K6 GFB2/IO271PDB6V4 K7 IO271NDB6V4 K8 GND K9 GND FG324 Pin Number A3PE3000L Function K10 GND K11 GND K12 IO115NDB3V0 K13 GCB2/IO116PDB3V0 K14 IO116NDB3V0 K15 GCC2/IO117PDB3V0 K16 VCCPLC K17 IO124NPB3V1 K18 IO120PPB3V0 L1 IO263NDB6V3 L2 VCCIB6 L3 IO259PDB6V3 L4 IO259NDB6V3 L5 GND L6 IO270NPB6V4 L7 VCC L8 VCC L9 GND L10 GND L11 VCC L12 VCC L13 IO132PDB3V2 L14 GND L15 IO117NDB3V0 L16 IO128NPB3V1 L17 VCCIB3 L18 IO124PPB3V1 M1 GND M2 IO255PDB6V2 M3 IO255NDB6V2 M4 IO251PPB6V2 M5 VCCIB6 M6 GEB0/IO235NDB6V0 M7 GEB1/IO235PDB6V0 M8 VCC FG324 Pin Number A3PE3000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-33 V2 IO218NDB5V3 V3 IO218PDB5V3 V4 IO206NDB5V1 V5 IO206PDB5V1 V6 IO198NPB5V0 V7 GND V8 IO190NDB4V4 V9 IO190PDB4V4 V10 IO182PPB4V3 V11 IO180PPB4V3 V12 GND V13 IO162NDB4V1 V14 IO160NDB4V0 V15 IO160PDB4V0 V16 IO158NDB4V0 V17 IO158PDB4V0 V18 GND FG324 Pin Number A3PE3000L Function

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. A B C D E F G H J K L M N P R T U V W Y AA AB 12345678910111213141516171819202122 A1 Ball Pad Corner

ProASIC3L Low Power Flash FPGAs Revision 13 4-35 FG484 Pin Number A3P600L Function A1 GND A2 GND A3 VCCIB0 A4 NC A5 NC A6 IO09RSB0 A7 IO15RSB0 A8 NC A9 NC A10 IO22RSB0 A11 IO23RSB0 A12 IO29RSB0 A13 IO35RSB0 A14 NC A15 NC A16 IO46RSB0 A17 IO48RSB0 A18 NC A19 NC A20 VCCIB0 A21 GND A22 GND AA1 GND AA2 VCCIB3 AA3 NC AA4 NC AA5 NC AA6 IO135RSB2 AA7 IO133RSB2 AA8 NC AA9 NC AA10 NC AA11 NC AA12 NC AA13 NC AA14 NC AA15 NC AA16 IO101RSB2 AA17 NC AA18 NC AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 NC AB5 NC AB6 IO130RSB2 AB7 IO128RSB2 AB8 IO122RSB2 AB9 IO116RSB2 AB10 NC AB11 NC AB12 IO113RSB2 AB13 IO112RSB2 AB14 NC AB15 NC AB16 IO100RSB2 AB17 IO95RSB2 AB18 NC AB19 NC AB20 VCCIB2 AB21 GND AB22 GND B1 GND B2 VCCIB3 B3 NC B4 NC B5 NC B6 IO08RSB0 FG484 Pin Number A3P600L Function B7 IO12RSB0 B8 NC B9 NC B10 IO17RSB0 B11 NC B12 NC B13 IO36RSB0 B14 NC B15 NC B16 IO47RSB0 B17 IO49RSB0 B18 NC B19 NC B20 NC B21 VCCIB1 B22 GND C1 VCCIB3 C2 NC C3 NC C4 NC C5 GND C6 NC C7 NC C8 VCC C9 VCC C10 NC C11 NC C12 NC C13 NC C14 VCC C15 VCC C16 NC C17 NC C18 GND C19 NC C20 NC FG484 Pin Number A3P600L Function

Pin Number A3P600L Function E13 IO38RSB0 E14 IO42RSB0 E15 GBC1/IO55RSB0 E16 GBB0/IO56RSB0 E17 IO52RSB0 E18 GBA2/IO60PDB1 E19 IO60NDB1 E20 GND E21 NC E22 NC F1 NC F2 NC F3 NC F4 IO173NDB3 F5 IO174NDB3 F6 VMV3 F7 IO07RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO20RSB0 F11 IO24RSB0 F12 IO33RSB0 F13 IO39RSB0 F14 IO44RSB0 F15 GBC0/IO54RSB0 F16 IO51RSB0 F17 VMV0 F18 IO61NPB1 F19 IO63PDB1 F20 NC F21 NC F22 NC G1 IO170NDB3 G2 IO170PDB3 G3 NC G4 IO171NDB3 FG484 Pin Number A3P600L Function G5 IO171PDB3 G6 GAC2/IO172PDB3 G7 IO06RSB0 G8 GNDQ G9 IO10RSB0 G10 IO19RSB0 G11 IO26RSB0 G12 IO30RSB0 G13 IO40RSB0 G14 IO45RSB0 G15 GNDQ G16 IO50RSB0 G17 GBB2/IO61PPB1 G18 IO53RSB0 G19 IO63NDB1 G20 NC G21 NC G22 NC H1 NC H2 NC H3 VCC H4 IO166PDB3 H5 IO167NPB3 H6 IO172NDB3 H7 IO169NDB3 H8 VMV0 H9 VCCIB0 H10 VCCIB0 H11 IO25RSB0 H12 IO31RSB0 H13 VCCIB0 H14 VCCIB0 H15 VMV1 H16 GBC2/IO62PDB1 H17 IO67PPB1 H18 IO64PPB1 FG484 Pin Number A3P600L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-37 H19 IO66PDB1 H20 VCC H21 NC H22 NC J1 NC J2 NC J3 NC J4 IO166NDB3 J5 IO168NPB3 J6 IO167PPB3 J7 IO169PDB3 J8 VCCIB3 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC J14 GND J15 VCCIB1 J16 IO62NDB1 J17 IO64NPB1 J18 IO65PPB1 J19 IO66NDB1 J20 NC J21 IO68PDB1 J22 IO68NDB1 K1 IO157PDB3 K2 IO157NDB3 K3 NC K4 IO165NDB3 K5 IO165PDB3 K6 IO168PPB3 K7 GFC1/IO164PPB3 K8 VCCIB3 K9 VCC K10 GND FG484 Pin Number A3P600L Function K11 GND K12 GND K13 GND K14 VCC K15 VCCIB1 K16 GCC1/IO69PPB1 K17 IO65NPB1 K18 IO75PDB1 K19 IO75NDB1 K20 NC K21 IO76NDB1 K22 IO76PDB1 L1 NC L2 IO155PDB3 L3 NC L4 GFB0/IO163NPB3 L5 GFA0/IO162NDB3 L6 GFB1/IO163PPB3 L7 VCOMPLF L8 GFC0/IO164NPB3 L9 VCC L10 GND L11 GND L12 GND L13 GND L14 VCC L15 GCC0/IO69NPB1 L16 GCB1/IO70PPB1 L17 GCA0/IO71NPB1 L18 IO67NPB1 L19 GCB0/IO70NPB1 L20 IO77PDB1 L21 IO77NDB1 L22 IO78NPB1 M1 NC M2 IO155NDB3 FG484 Pin Number A3P600L Function M3 IO158NPB3 M4 GFA2/IO161PPB3 M5 GFA1/IO162PDB3 M6 VCCPLF M7 IO160NDB3 M8 GFB2/IO160PDB3 M9 VCC M10 GND M11 GND M12 GND M13 GND M14 VCC M15 GCB2/IO73PPB1 M16 GCA1/IO71PPB1 M17 GCC2/IO74PPB1 M18 IO80PPB1 M19 GCA2/IO72PDB1 M20 IO79PPB1 M21 IO78PPB1 M22 NC N1 IO154NDB3 N2 IO154PDB3 N3 NC N4 GFC2/IO159PDB3 N5 IO161NPB3 N6 IO156PPB3 N7 IO129RSB2 N8 VCCIB3 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB1 N16 IO73NPB1 FG484 Pin Number A3P600L Function

Pin Number A3P600L Function R9 VCCIB2 R10 VCCIB2 R11 IO117RSB2 R12 IO110RSB2 R13 VCCIB2 R14 VCCIB2 R15 VMV2 R16 IO94RSB2 R17 GDB1/IO87PPB1 R18 GDC1/IO86PDB1 R19 IO84NDB1 R20 VCC R21 IO81NDB1 R22 IO82PDB1 T1 IO152PDB3 T2 IO152NDB3 T3 NC T4 IO150NDB3 T5 IO147PPB3 T6 GEC1/IO146PPB3 T7 IO140RSB2 T8 GNDQ T9 GEA2/IO143RSB2 T10 IO126RSB2 T11 IO120RSB2 T12 IO108RSB2 T13 IO103RSB2 T14 IO99RSB2 T15 GNDQ T16 IO92RSB2 T17 VJTAG T18 GDC0/IO86NDB1 T19 GDA1/IO88PDB1 T20 NC T21 IO83PDB1 T22 IO82NDB1 FG484 Pin Number A3P600L Function U1 IO149PDB3 U2 IO149NDB3 U3 NC U4 GEB1/IO145PDB3 U5 GEB0/IO145NDB3 U6 VMV2 U7 IO138RSB2 U8 IO136RSB2 U9 IO131RSB2 U10 IO124RSB2 U11 IO119RSB2 U12 IO107RSB2 U13 IO104RSB2 U14 IO97RSB2 U15 VMV1 U16 TCK U17 VPUMP U18 TRST U19 GDA0/IO88NDB1 U20 NC U21 IO83NDB1 U22 NC V1 NC V2 NC V3 GND V4 GEA1/IO144PDB3 V5 GEA0/IO144NDB3 V6 IO139RSB2 V7 GEC2/IO141RSB2 V8 IO132RSB2 V9 IO127RSB2 V10 IO121RSB2 V11 IO114RSB2 V12 IO109RSB2 V13 IO105RSB2 V14 IO98RSB2 FG484 Pin Number A3P600L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-39 V15 IO96RSB2 V16 GDB2/IO90RSB2 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 NC W1 NC W2 IO148PDB3 W3 NC W4 GND W5 IO137RSB2 W6 FF/GEB2/IO142RSB2 W7 IO134RSB2 W8 IO125RSB2 W9 IO123RSB2 W10 IO118RSB2 W11 IO115RSB2 W12 IO111RSB2 W13 IO106RSB2 W14 IO102RSB2 W15 GDC2/IO91RSB2 W16 IO93RSB2 W17 GDA2/IO89RSB2 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB3 Y2 IO148NDB3 Y3 NC Y4 NC Y5 GND Y6 NC FG484 Pin Number A3P600L Function Y7 NC Y8 VCC Y9 VCC Y10 NC Y11 NC Y12 NC Y13 NC Y14 VCC Y15 VCC Y16 NC Y17 NC Y18 GND Y19 NC Y20 NC Y21 NC Y22 VCCIB1 FG484 Pin Number A3P600L Function

Pin Number A3P1000L Function A1 GND A2 GND A3 VCCIB0 A4 IO07RSB0 A5 IO09RSB0 A6 IO13RSB0 A7 IO18RSB0 A8 IO20RSB0 A9 IO26RSB0 A10 IO32RSB0 A11 IO40RSB0 A12 IO41RSB0 A13 IO53RSB0 A14 IO59RSB0 A15 IO64RSB0 A16 IO65RSB0 A17 IO67RSB0 A18 IO69RSB0 A19 NC A20 VCCIB0 A21 GND A22 GND AA1 GND AA2 VCCIB3 AA3 NC AA4 IO181RSB2 AA5 IO178RSB2 AA6 IO175RSB2 AA7 IO169RSB2 AA8 IO166RSB2 AA9 IO160RSB2 AA10 IO152RSB2 AA11 IO146RSB2 AA12 IO139RSB2 AA13 IO133RSB2 AA14 NC AA15 NC AA16 IO122RSB2 AA17 IO119RSB2 AA18 IO117RSB2 AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 IO180RSB2 AB5 IO176RSB2 AB6 IO173RSB2 AB7 IO167RSB2 AB8 IO162RSB2 AB9 IO156RSB2 AB10 IO150RSB2 AB11 IO145RSB2 AB12 IO144RSB2 AB13 IO132RSB2 AB14 IO127RSB2 AB15 IO126RSB2 AB16 IO123RSB2 AB17 IO121RSB2 AB18 IO118RSB2 AB19 NC AB20 VCCIB2 AB21 GND AB22 GND B1 GND B2 VCCIB3 B3 NC B4 IO06RSB0 B5 IO08RSB0 B6 IO12RSB0 FG484 Pin Number A3P1000L Function B7 IO15RSB0 B8 IO19RSB0 B9 IO24RSB0 B10 IO31RSB0 B11 IO39RSB0 B12 IO48RSB0 B13 IO54RSB0 B14 IO58RSB0 B15 IO63RSB0 B16 IO66RSB0 B17 IO68RSB0 B18 IO70RSB0 B19 NC B20 NC B21 VCCIB1 B22 GND C1 VCCIB3 C2 IO220PDB3 C3 NC C4 NC C5 GND C6 IO10RSB0 C7 IO14RSB0 C8 VCC C9 VCC C10 IO30RSB0 C11 IO37RSB0 C12 IO43RSB0 C13 NC C14 VCC C15 VCC C16 NC C17 NC C18 GND C19 NC C20 NC FG484 Pin Number A3P1000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-41 C21 NC C22 VCCIB1 D1 IO219PDB3 D2 IO220NDB3 D3 NC D4 GND D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 D7 GAB0/IO02RSB0 D8 IO16RSB0 D9 IO22RSB0 D10 IO28RSB0 D11 IO35RSB0 D12 IO45RSB0 D13 IO50RSB0 D14 IO55RSB0 D15 IO61RSB0 D16 GBB1/IO75RSB0 D17 GBA0/IO76RSB0 D18 GBA1/IO77RSB0 D19 GND D20 NC D21 NC D22 NC E1 IO219NDB3 E2 NC E3 GND E4 GAB2/IO224PDB3 E5 GAA2/IO225PDB3 E6 GNDQ E7 GAB1/IO03RSB0 E8 IO17RSB0 E9 IO21RSB0 E10 IO27RSB0 E11 IO34RSB0 E12 IO44RSB0 FG484 Pin Number A3P1000L Function E13 IO51RSB0 E14 IO57RSB0 E15 GBC1/IO73RSB0 E16 GBB0/IO74RSB0 E17 IO71RSB0 E18 GBA2/IO78PDB1 E19 IO81PDB1 E20 GND E21 NC E22 IO84PDB1 F1 NC F2 IO215PDB3 F3 IO215NDB3 F4 IO224NDB3 F5 IO225NDB3 F6 VMV3 F7 IO11RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO25RSB0 F11 IO36RSB0 F12 IO42RSB0 F13 IO49RSB0 F14 IO56RSB0 F15 GBC0/IO72RSB0 F16 IO62RSB0 F17 VMV0 F18 IO78NDB1 F19 IO81NDB1 F20 IO82PPB1 F21 NC F22 IO84NDB1 G1 IO214NDB3 G2 IO214PDB3 G3 NC G4 IO222NDB3 FG484 Pin Number A3P1000L Function G5 IO222PDB3 G6 GAC2/IO223PDB3 G7 IO223NDB3 G8 GNDQ G9 IO23RSB0 G10 IO29RSB0 G11 IO33RSB0 G12 IO46RSB0 G13 IO52RSB0 G14 IO60RSB0 G15 GNDQ G16 IO80NDB1 G17 GBB2/IO79PDB1 G18 IO79NDB1 G19 IO82NPB1 G20 IO85PDB1 G21 IO85NDB1 G22 NC H1 NC H2 NC H3 VCC H4 IO217PDB3 H5 IO218PDB3 H6 IO221NDB3 H7 IO221PDB3 H8 VMV0 H9 VCCIB0 H10 VCCIB0 H11 IO38RSB0 H12 IO47RSB0 H13 VCCIB0 H14 VCCIB0 H15 VMV1 H16 GBC2/IO80PDB1 H17 IO83PPB1 H18 IO86PPB1 FG484 Pin Number A3P1000L Function

Pin Number A3P1000L Function K11 GND K12 GND K13 GND K14 VCC K15 VCCIB1 K16 GCC1/IO91PPB1 K17 IO90NPB1 K18 IO88PDB1 K19 IO88NDB1 K20 IO94NPB1 K21 IO98NDB1 K22 IO98PDB1 L1 NC L2 IO200PDB3 L3 IO210NPB3 L4 GFB0/IO208NPB3 L5 GFA0/IO207NDB3 L6 GFB1/IO208PPB3 L7 VCOMPLF L8 GFC0/IO209NPB3 L9 VCC L10 GND L11 GND L12 GND L13 GND L14 VCC L15 GCC0/IO91NPB1 L16 GCB1/IO92PPB1 L17 GCA0/IO93NPB1 L18 IO96NPB1 L19 GCB0/IO92NPB1 L20 IO97PDB1 L21 IO97NDB1 L22 IO99NPB1 M1 NC M2 IO200NDB3 FG484 Pin Number A3P1000L Function M3 IO206NDB3 M4 GFA2/IO206PDB3 M5 GFA1/IO207PDB3 M6 VCCPLF M7 IO205NDB3 M8 GFB2/IO205PDB3 M9 VCC M10 GND M11 GND M12 GND M13 GND M14 VCC M15 GCB2/IO95PPB1 M16 GCA1/IO93PPB1 M17 GCC2/IO96PPB1 M18 IO100PPB1 M19 GCA2/IO94PPB1 M20 IO101PPB1 M21 IO99PPB1 M22 NC N1 IO201NDB3 N2 IO201PDB3 N3 NC N4 GFC2/IO204PDB3 N5 IO204NDB3 N6 IO203NDB3 N7 IO203PDB3 N8 VCCIB3 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB1 N16 IO95NPB1 FG484 Pin Number A3P1000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-43 N17 IO100NPB1 N18 IO102NDB1 N19 IO102PDB1 N20 NC N21 IO101NPB1 N22 IO103PDB1 P1 NC P2 IO199PDB3 P3 IO199NDB3 P4 IO202NDB3 P5 IO202PDB3 P6 IO196PPB3 P7 IO193PPB3 P8 VCCIB3 P9 GND P10 VCC P11 VCC P12 VCC P13 VCC P14 GND P15 VCCIB1 P16 GDB0/IO112NPB1 P17 IO106NDB1 P18 IO106PDB1 P19 IO107PDB1 P20 NC P21 IO104PDB1 P22 IO103NDB1 R1 NC R2 IO197PPB3 R3 VCC R4 IO197NPB3 R5 IO196NPB3 R6 IO193NPB3 R7 GEC0/IO190NPB3 R8 VMV3 FG484 Pin Number A3P1000L Function R9 VCCIB2 R10 VCCIB2 R11 IO147RSB2 R12 IO136RSB2 R13 VCCIB2 R14 VCCIB2 R15 VMV2 R16 IO110NDB1 R17 GDB1/IO112PPB1 R18 GDC1/IO111PDB1 R19 IO107NDB1 R20 VCC R21 IO104NDB1 R22 IO105PDB1 T1 IO198PDB3 T2 IO198NDB3 T3 NC T4 IO194PPB3 T5 IO192PPB3 T6 GEC1/IO190PPB3 T7 IO192NPB3 T8 GNDQ T9 GEA2/IO187RSB2 T10 IO161RSB2 T11 IO155RSB2 T12 IO141RSB2 T13 IO129RSB2 T14 IO124RSB2 T15 GNDQ T16 IO110PDB1 T17 VJTAG T18 GDC0/IO111NDB1 T19 GDA1/IO113PDB1 T20 NC T21 IO108PDB1 T22 IO105NDB1 FG484 Pin Number A3P1000L Function U1 IO195PDB3 U2 IO195NDB3 U3 IO194NPB3 U4 GEB1/IO189PDB3 U5 GEB0/IO189NDB3 U6 VMV2 U7 IO179RSB2 U8 IO171RSB2 U9 IO165RSB2 U10 IO159RSB2 U11 IO151RSB2 U12 IO137RSB2 U13 IO134RSB2 U14 IO128RSB2 U15 VMV1 U16 TCK U17 VPUMP U18 TRST U19 GDA0/IO113NDB1 U20 NC U21 IO108NDB1 U22 IO109PDB1 V1 NC V2 NC V3 GND V4 GEA1/IO188PDB3 V5 GEA0/IO188NDB3 V6 IO184RSB2 V7 GEC2/IO185RSB2 V8 IO168RSB2 V9 IO163RSB2 V10 IO157RSB2 V11 IO149RSB2 V12 IO143RSB2 V13 IO138RSB2 V14 IO131RSB2 FG484 Pin Number A3P1000L Function

Pin Number A3P1000L Function Y7 IO174RSB2 Y8 VCC Y9 VCC Y10 IO154RSB2 Y11 IO148RSB2 Y12 IO140RSB2 Y13 NC Y14 VCC Y15 VCC Y16 NC Y17 NC Y18 GND Y19 NC Y20 NC Y21 NC Y22 VCCIB1 FG484 Pin Number A3P1000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-45 FG484 Pin Number A3PE3000L Function A1 GND A2 GND A3 VCCIB0 A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO16NDB0V1 A7 IO16PDB0V1 A8 IO18PDB0V2 A9 IO24PDB0V2 A10 IO28NDB0V3 A11 IO28PDB0V3 A12 IO46PDB1V0 A13 IO54PDB1V1 A14 IO56NDB1V1 A15 IO56PDB1V1 A16 IO64NDB1V2 A17 IO64PDB1V2 A18 IO72NDB1V3 A19 IO74NDB1V4 A20 VCCIB1 A21 GND A22 GND AA1 GND AA2 VCCIB6 AA3 IO228PDB5V4 AA4 IO224PDB5V3 AA5 IO218NDB5V3 AA6 IO218PDB5V3 AA7 IO212NDB5V2 AA8 IO212PDB5V2 AA9 IO198PDB5V0 AA10 IO198NDB5V0 AA11 IO188PPB4V4 AA12 IO180NDB4V3 AA13 IO180PDB4V3 AA14 IO170NDB4V2 AA15 IO170PDB4V2 AA16 IO166NDB4V1 AA17 IO166PDB4V1 AA18 IO160NDB4V0 AA19 IO160PDB4V0 AA20 IO158NPB4V0 AA21 VCCIB3 AA22 GND AB1 GND AB2 GND AB3 VCCIB5 AB4 IO216NDB5V2 AB5 IO216PDB5V2 AB6 IO210NDB5V2 AB7 IO210PDB5V2 AB8 IO208NDB5V1 AB9 IO208PDB5V1 AB10 IO197NDB5V0 AB11 IO197PDB5V0 AB12 IO174NDB4V2 AB13 IO174PDB4V2 AB14 IO172NDB4V2 AB15 IO172PDB4V2 AB16 IO168NDB4V1 AB17 IO168PDB4V1 AB18 IO162NDB4V1 AB19 IO162PDB4V1 AB20 VCCIB4 AB21 GND AB22 GND B1 GND B2 VCCIB7 B3 IO06PPB0V0 B4 IO08NDB0V0 FG484 Pin Number A3PE3000L Function B5 IO08PDB0V0 B6 IO14NDB0V1 B7 IO14PDB0V1 B8 IO18NDB0V2 B9 IO24NDB0V2 B10 IO34PDB0V4 B11 IO40PDB0V4 B12 IO46NDB1V0 B13 IO54NDB1V1 B14 IO62NDB1V2 B15 IO62PDB1V2 B16 IO68NDB1V3 B17 IO68PDB1V3 B18 IO72PDB1V3 B19 IO74PDB1V4 B20 IO76NPB1V4 B21 VCCIB2 B22 GND C1 VCCIB7 C2 IO303PDB7V3 C3 IO305PDB7V3 C4 IO06NPB0V0 C5 GND C6 IO12NDB0V1 C7 IO12PDB0V1 C8 VCC C9 VCC C10 IO34NDB0V4 C11 IO40NDB0V4 C12 IO48NDB1V0 C13 IO48PDB1V0 C14 VCC C15 VCC C16 IO70NDB1V3 C17 IO70PDB1V3 FG484 Pin Number A3PE3000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-47 H13 VCCIB1 H14 VCCIB1 H15 VMV1 H16 GBC2/IO84PDB2V0 H17 IO83NDB2V0 H18 IO100NDB2V2 H19 IO100PDB2V2 H20 VCC H21 VMV2 H22 IO105PDB2V2 J1 IO285NDB7V1 J2 IO285PDB7V1 J3 VMV7 J4 IO279PDB7V0 J5 IO283PDB7V1 J6 IO281PDB7V0 J7 IO287NDB7V1 J8 VCCIB7 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC J14 GND J15 VCCIB2 J16 IO84NDB2V0 J17 IO104NDB2V2 J18 IO104PDB2V2 J19 IO106PPB2V3 J20 GNDQ J21 IO109PDB2V3 J22 IO107PDB2V3 K1 IO277NDB7V0 K2 IO277PDB7V0 K3 GNDQ FG484 Pin Number A3PE3000L Function K4 IO279NDB7V0 K5 IO283NDB7V1 K6 IO281NDB7V0 K7 GFC1/IO275PPB7V0 K8 VCCIB7 K9 VCC K10 GND K11 GND K12 GND K13 GND K14 VCC K15 VCCIB2 K16 GCC1/IO112PPB2V3 K17 IO108NDB2V3 K18 IO108PDB2V3 K19 IO110NPB2V3 K20 IO106NPB2V3 K21 IO109NDB2V3 K22 IO107NDB2V3 L1 IO257PSB6V2 L2 IO276PDB7V0 L3 IO276NDB7V0 L4 GFB0/IO274NPB7V0 L5 GFA0/IO273NDB6V4 L6 GFB1/IO274PPB7V0 L7 VCOMPLF L8 GFC0/IO275NPB7V0 L9 VCC L10 GND L11 GND L12 GND L13 GND L14 VCC L15 GCC0/IO112NPB2V3 L16 GCB1/IO113PPB2V3 FG484 Pin Number A3PE3000L Function L17 GCA0/IO114NPB3V0 L18 VCOMPLC L19 GCB0/IO113NPB2V3 L20 IO110PPB2V3 L21 IO111NDB2V3 L22 IO111PDB2V3 M1 GNDQ M2 IO255NPB6V2 M3 IO272NDB6V4 M4 GFA2/IO272PDB6V4 M5 GFA1/IO273PDB6V4 M6 VCCPLF M7 IO271NDB6V4 M8 GFB2/IO271PDB6V4 M9 VCC M10 GND M11 GND M12 GND M13 GND M14 VCC M15 GCB2/IO116PPB3V0 M16 GCA1/IO114PPB3V0 M17 GCC2/IO117PPB3V0 M18 VCCPLC M19 GCA2/IO115PDB3V0 M20 IO115NDB3V0 M21 IO126PDB3V1 M22 IO124PSB3V1 N1 IO255PPB6V2 N2 IO253NDB6V2 N3 VMV6 N4 GFC2/IO270PPB6V4 N5 IO261PPB6V3 N6 IO263PDB6V3 N7 IO263NDB6V3 FG484 Pin Number A3PE3000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-49 V3 GND V4 GEA1/IO234PDB6V0 V5 GEA0/IO234NDB6V0 V6 GNDQ V7 GEC2/IO231PDB5V4 V8 IO222NPB5V3 V9 IO204NDB5V1 V10 IO204PDB5V1 V11 IO195NDB5V0 V12 IO195PDB5V0 V13 IO178NDB4V3 V14 IO178PDB4V3 V15 IO155NDB4V0 V16 GDB2/IO155PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 IO146PDB3V4 V22 IO142NDB3V3 W1 IO239NDB6V0 W2 IO237PDB6V0 W3 IO230PSB5V4 W4 GND W5 IO232NDB5V4 W6 FF/GEB2/IO232PDB5V4 W7 IO231NDB5V4 W8 IO214NDB5V2 W9 IO214PDB5V2 W10 IO200NDB5V0 W11 IO192NDB4V4 W12 IO184NDB4V3 W13 IO184PDB4V3 W14 IO156NDB4V0 W15 GDC2/IO156PDB4V0 FG484 Pin Number A3PE3000L Function W16 IO154NDB4V0 W17 GDA2/IO154PDB4V0 W18 TMS W19 GND W20 IO150NDB3V4 W21 IO146NDB3V4 W22 IO148PPB3V4 Y1 VCCIB6 Y2 IO237NDB6V0 Y3 IO228NDB5V4 Y4 IO224NDB5V3 Y5 GND Y6 IO220NDB5V3 Y7 IO220PDB5V3 Y8 VCC Y9 VCC Y10 IO200PDB5V0 Y11 IO192PDB4V4 Y12 IO188NPB4V4 Y13 IO187PSB4V4 Y14 VCC Y15 VCC Y16 IO164NDB4V1 Y17 IO164PDB4V1 Y18 GND Y19 IO158PPB4V0 Y20 IO150PDB3V4 Y21 IO148NPB3V4 Y22 VCCIB3 FG484 Pin Number A3PE3000L Function

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view. A1 Ball Pad Corner A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 123456789101112131415161718192021222324252627282930 AG AH AJ AK

ProASIC3L Low Power Flash FPGAs Revision 13 4-51 FG896 Pin Number A3PE3000L Function A2 GND A3 GND A4 IO14NPB0V1 A5 GND A6 IO07NPB0V0 A7 GND A8 IO09NDB0V1 A9 IO17NDB0V2 A10 IO17PDB0V2 A11 IO21NDB0V2 A12 IO21PDB0V2 A13 IO33NDB0V4 A14 IO33PDB0V4 A15 IO35NDB0V4 A16 IO35PDB0V4 A17 IO41NDB1V0 A18 IO43NDB1V0 A19 IO43PDB1V0 A20 IO45NDB1V0 A21 IO45PDB1V0 A22 IO57NDB1V2 A23 IO57PDB1V2 A24 GND A25 IO69PPB1V3 A26 GND A27 GBC1/IO79PPB1V4 A28 GND A29 GND AA1 IO256PDB6V2 AA2 IO248PDB6V1 AA3 IO248NDB6V1 AA4 IO246NDB6V1 AA5 GEA1/IO234PDB6V0 AA6 GEA0/IO234NDB6V0 AA7 IO243PPB6V1 AA8 IO245NDB6V1 AA9 GEB1/IO235PPB6V0 AA10 VCC AA11 IO226PPB5V4 AA12 VCCIB5 AA13 VCCIB5 AA14 VCCIB5 AA15 VCCIB5 AA16 VCCIB4 AA17 VCCIB4 AA18 VCCIB4 AA19 VCCIB4 AA20 IO174PDB4V2 AA21 VCC AA22 IO142NPB3V3 AA23 IO144NDB3V3 AA24 IO144PDB3V3 AA25 IO146NDB3V4 AA26 IO146PDB3V4 AA27 IO147PDB3V4 AA28 IO139NDB3V3 AA29 IO139PDB3V3 AA30 IO133NDB3V2 AB1 IO256NDB6V2 AB2 IO244PDB6V1 AB3 IO244NDB6V1 AB4 IO241PDB6V0 AB5 IO241NDB6V0 AB6 IO243NPB6V1 AB7 VCCIB6 AB8 VCCPLE AB9 VCC AB10 IO222PDB5V3 AB11 IO218PPB5V3 AB12 IO206NDB5V1 FG896 Pin Number A3PE3000L Function AB13 IO206PDB5V1 AB14 IO198NDB5V0 AB15 IO198PDB5V0 AB16 IO192NDB4V4 AB17 IO192PDB4V4 AB18 IO178NDB4V3 AB19 IO178PDB4V3 AB20 IO174NDB4V2 AB21 IO162NPB4V1 AB22 VCC AB23 VCCPLD AB24 VCCIB3 AB25 IO150PDB3V4 AB26 IO148PDB3V4 AB27 IO147NDB3V4 AB28 IO145PDB3V3 AB29 IO143PDB3V3 AB30 IO137PDB3V2 AC1 IO254PDB6V2 AC2 IO254NDB6V2 AC3 IO240PDB6V0 AC4 GEC1/IO236PDB6V0 AC5 IO237PDB6V0 AC6 IO237NDB6V0 AC7 VCOMPLE AC8 GND AC9 IO226NPB5V4 AC10 IO222NDB5V3 AC11 IO216NPB5V2 AC12 IO210NPB5V2 AC13 IO204NDB5V1 AC14 IO204PDB5V1 AC15 IO194NDB5V0 AC16 IO188NDB4V4 AC17 IO188PDB4V4 FG896 Pin Number A3PE3000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-53 AF29 GNDQ AF30 GND AG1 IO238NPB6V0 AG2 VCC AG3 IO232NPB5V4 AG4 GND AG5 IO220PPB5V3 AG6 IO228PDB5V4 AG7 IO231NDB5V4 AG8 GEC2/IO231PDB5V4 AG9 IO225NPB5V3 AG10 IO223NPB5V3 AG11 IO221PDB5V3 AG12 IO221NDB5V3 AG13 IO205NPB5V1 AG14 IO199NDB5V0 AG15 IO199PDB5V0 AG16 IO187NDB4V4 AG17 IO187PDB4V4 AG18 IO181NDB4V3 AG19 IO171PPB4V2 AG20 IO165NPB4V1 AG21 IO161NPB4V0 AG22 IO159NDB4V0 AG23 IO159PDB4V0 AG24 IO158PPB4V0 AG25 GDB2/IO155PDB4V0 AG26 GDA2/IO154PPB4V0 AG27 GND AG28 VJTAG AG29 VCC AG30 IO149NDB3V4 AH1 GND AH2 IO233NPB5V4 AH3 VCC FG896 Pin Number A3PE3000L Function AH4 FF/GEB2/IO232PPB5V4 AH5 VCCIB5 AH6 IO219NDB5V3 AH7 IO219PDB5V3 AH8 IO227NDB5V4 AH9 IO227PDB5V4 AH10 IO225PPB5V3 AH11 IO223PPB5V3 AH12 IO211NDB5V2 AH13 IO211PDB5V2 AH14 IO205PPB5V1 AH15 IO195NDB5V0 AH16 IO185NDB4V3 AH17 IO185PDB4V3 AH18 IO181PDB4V3 AH19 IO177NDB4V2 AH20 IO171NPB4V2 AH21 IO165PPB4V1 AH22 IO161PPB4V0 AH23 IO157NDB4V0 AH24 IO157PDB4V0 AH25 IO155NDB4V0 AH26 VCCIB4 AH27 TDI AH28 VCC AH29 VPUMP AH30 GND AJ1 GND AJ2 GND AJ3 GEA2/IO233PPB5V4 AJ4 VCC AJ5 IO217NPB5V2 AJ6 VCC AJ7 IO215NPB5V2 AJ8 IO213NDB5V2 FG896 Pin Number A3PE3000L Function AJ9 IO213PDB5V2 AJ10 IO209NDB5V1 AJ11 IO209PDB5V1 AJ12 IO203NDB5V1 AJ13 IO203PDB5V1 AJ14 IO197NDB5V0 AJ15 IO195PDB5V0 AJ16 IO183NDB4V3 AJ17 IO183PDB4V3 AJ18 IO179NPB4V3 AJ19 IO177PDB4V2 AJ20 IO173NDB4V2 AJ21 IO173PDB4V2 AJ22 IO163NDB4V1 AJ23 IO163PDB4V1 AJ24 IO167NPB4V1 AJ25 VCC AJ26 IO156NPB4V0 AJ27 VCC AJ28 TMS AJ29 GND AJ30 GND AK2 GND AK3 GND AK4 IO217PPB5V2 AK5 GND AK6 IO215PPB5V2 AK7 GND AK8 IO207NDB5V1 AK9 IO207PDB5V1 AK10 IO201NDB5V0 AK11 IO201PDB5V0 AK12 IO193NDB4V4 AK13 IO193PDB4V4 AK14 IO197PDB5V0 FG896 Pin Number A3PE3000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-55 E1 GND E2 IO303NPB7V3 E3 VCCIB7 E4 IO305PPB7V3 E5 VCC E6 GAC0/IO02NDB0V0 E7 VCCIB0 E8 IO06PPB0V0 E9 IO24NDB0V2 E10 IO24PDB0V2 E11 IO13NDB0V1 E12 IO13PDB0V1 E13 IO34NDB0V4 E14 IO34PDB0V4 E15 IO40NDB0V4 E16 IO49NDB1V1 E17 IO49PDB1V1 E18 IO50PDB1V1 E19 IO58PDB1V2 E20 IO60NDB1V2 E21 IO77PDB1V4 E22 IO68NDB1V3 E23 IO68PDB1V3 E24 VCCIB1 E25 IO74PDB1V4 E26 VCC E27 GBB1/IO80PPB1V4 E28 VCCIB2 E29 IO82NPB2V0 E30 GND F1 IO296PPB7V2 F2 VCC F3 IO306PDB7V4 F4 IO297PDB7V2 F5 VMV7 FG896 Pin Number A3PE3000L Function F5 VMV7 F6 GND F7 GNDQ F8 IO12NDB0V1 F9 IO12PDB0V1 F10 IO10PDB0V1 F11 IO16PDB0V1 F12 IO22NDB0V2 F13 IO30NDB0V3 F14 IO30PDB0V3 F15 IO36PDB0V4 F16 IO48NDB1V0 F17 IO48PDB1V0 F18 IO50NDB1V1 F19 IO58NDB1V2 F20 IO60PDB1V2 F21 IO77NDB1V4 F22 IO72NDB1V3 F23 IO72PDB1V3 F24 GNDQ F25 GND F26 VMV2 F26 VMV2 F27 IO86PDB2V0 F28 IO92PDB2V1 F29 VCC F30 IO100NPB2V2 G1 GND G2 IO296NPB7V2 G3 IO306NDB7V4 G4 IO297NDB7V2 G5 VCCIB7 G6 GNDQ G6 GNDQ G7 VCC FG896 Pin Number A3PE3000L Function G8 VMV0 G9 VCCIB0 G10 IO10NDB0V1 G11 IO16NDB0V1 G12 IO22PDB0V2 G13 IO26PPB0V3 G14 IO38NPB0V4 G15 IO36NDB0V4 G16 IO46NDB1V0 G17 IO46PDB1V0 G18 IO56NDB1V1 G19 IO56PDB1V1 G20 IO66NDB1V3 G21 IO66PDB1V3 G22 VCCIB1 G23 VMV1 G24 VCC G25 GNDQ G25 GNDQ G26 VCCIB2 G27 IO86NDB2V0 G28 IO92NDB2V1 G29 IO100PPB2V2 G30 GND H1 IO294PDB7V2 H2 IO294NDB7V2 H3 IO300NDB7V3 H4 IO300PDB7V3 H5 IO295PDB7V2 H6 IO299PDB7V3 H7 VCOMPLA H8 GND H9 IO08NDB0V0 H10 IO08PDB0V0 H11 IO18PDB0V2 FG896 Pin Number A3PE3000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-57 L27 IO97PDB2V1 L28 IO101PDB2V2 L29 IO103PDB2V2 L30 IO119NDB3V0 M1 IO282NDB7V1 M2 IO282PDB7V1 M3 IO292NDB7V2 M4 IO292PDB7V2 M5 IO283NDB7V1 M6 IO285PDB7V1 M7 IO287PDB7V1 M8 IO289PDB7V1 M9 IO289NDB7V1 M10 VCCIB7 M11 VCC M12 GND M13 GND M14 GND M15 GND M16 GND M17 GND M18 GND M19 GND M20 VCC M21 VCCIB2 M22 NC M23 IO104PPB2V2 M24 IO102PDB2V2 M25 IO102NDB2V2 M26 IO95PDB2V1 M27 IO97NDB2V1 M28 IO101NDB2V2 M29 IO103NDB2V2 M30 IO119PDB3V0 N1 IO276PDB7V0 FG896 Pin Number A3PE3000L Function N2 IO278PDB7V0 N3 IO280PDB7V0 N4 IO284PDB7V1 N5 IO279PDB7V0 N6 IO285NDB7V1 N7 IO287NDB7V1 N8 IO281NDB7V0 N9 IO281PDB7V0 N10 VCCIB7 N11 VCC N12 GND N13 GND N14 GND N15 GND N16 GND N17 GND N18 GND N19 GND N20 VCC N21 VCCIB2 N22 IO106NDB2V3 N23 IO106PDB2V3 N24 IO108PDB2V3 N25 IO108NDB2V3 N26 IO95NDB2V1 N27 IO99NDB2V2 N28 IO99PDB2V2 N29 IO107PDB2V3 N30 IO107NDB2V3 P1 IO276NDB7V0 P2 IO278NDB7V0 P3 IO280NDB7V0 P4 IO284NDB7V1 P5 IO279NDB7V0 P6 GFC1/IO275PDB7V0 FG896 Pin Number A3PE3000L Function P7 GFC0/IO275NDB7V0 P8 IO277PDB7V0 P9 IO277NDB7V0 P10 VCCIB7 P11 VCC P12 GND P13 GND P14 GND P15 GND P16 GND P17 GND P18 GND P19 GND P20 VCC P21 VCCIB2 P22 GCC1/IO112PDB2V3 P23 IO110PDB2V3 P24 IO110NDB2V3 P25 IO109PPB2V3 P26 IO111NPB2V3 P27 IO105PDB2V2 P28 IO105NDB2V2 P29 GCC2/IO117PDB3V0 P30 IO117NDB3V0 R1 GFC2/IO270PDB6V4 R2 GFB1/IO274PPB7V0 R3 VCOMPLF R4 GFA0/IO273NDB6V4 R5 GFB0/IO274NPB7V0 R6 IO271NDB6V4 R7 GFB2/IO271PDB6V4 R8 IO269PDB6V4 R9 IO269NDB6V4 R10 VCCIB7 R11 VCC FG896 Pin Number A3PE3000L Function

ProASIC3L Low Power Flash FPGAs Revision 13 4-59 V27 IO129NDB3V1 V28 IO127NDB3V1 V29 IO125NDB3V1 V30 IO123PDB3V1 W1 IO266NDB6V4 W2 IO262NDB6V3 W3 IO260NDB6V3 W4 IO252NDB6V2 W5 IO251NDB6V2 W6 IO251PDB6V2 W7 IO255NDB6V2 W8 IO249PPB6V1 W9 IO253PDB6V2 W10 VCCIB6 W11 VCC W12 GND W13 GND W14 GND W15 GND W16 GND W17 GND W18 GND W19 GND W20 VCC W21 VCCIB3 W22 IO134PDB3V2 W23 IO138PDB3V3 W24 IO132NDB3V2 W25 IO136NPB3V2 W26 IO130NPB3V2 W27 IO141PDB3V3 W28 IO135PDB3V2 W29 IO131PDB3V2 W30 IO123NDB3V1 Y1 IO266PDB6V4 FG896 Pin Number A3PE3000L Function Y2 IO250PDB6V2 Y3 IO250NDB6V2 Y4 IO246PDB6V1 Y5 IO247NDB6V1 Y6 IO247PDB6V1 Y7 IO249NPB6V1 Y8 IO245PDB6V1 Y9 IO253NDB6V2 Y10 GEB0/IO235NPB6V0 Y11 VCC Y12 VCC Y13 VCC Y14 VCC Y15 VCC Y16 VCC Y17 VCC Y18 VCC Y19 VCC Y20 VCC Y21 IO142PPB3V3 Y22 IO134NDB3V2 Y23 IO138NDB3V3 Y24 IO140NDB3V3 Y25 IO140PDB3V3 Y26 IO136PPB3V2 Y27 IO141NDB3V3 Y28 IO135NDB3V2 Y29 IO131NDB3V2 Y30 IO133PDB3V2 FG896 Pin Number A3PE3000L Function

5 – Datasheet Information List of Changes The following table lists critical changes that were made in each version of the ProASIC3L datasheet. Revision Changes Page Revision 13 (January 2013) The "ProASIC3L Ordering Information" section has been updated to mention "Y" as "Blank" mentioning "Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43221). 1-III Added following notes to Table 2-2 • Recommended Operating Conditions 1: "All ProASIC3L devices must be programmed with the VCC core voltage at 1.5 V" (SAR 39910) and "The programming temperature range supported is Tambient = 0°C to 85°C" (SAR 43645). 2-2 The note in Table 2-212 • ProASIC3L CCC/PLL Specification and Table 2-213 • ProASIC3L CCC/PLL Specification referring the reader to SmartGen was revised to refer instead to the online help associated with the core (SAR 42572). 2-132, 2-133 Signal names have been made consistent (SAR 38910). NA Libero Integrated Design Environment (I DE) was changed to Libero System-on-Chip (SoC) throughout the document (SAR 40286). Live at Power-Up (LAPU) has been replaced with ’Instant On’. NA Revision 12 (September 2012) The "Security" section was modified to clarify that Microsemi does not support read- back of programmed data. 1-2 Revision 11 (August 2012) Added a Note stating " VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information." to Table 2-1 • Absolute Maximum Ratings and Table 2-2 • Recommended Operating Conditions 1 (SAR 38316). 2-1 2-2 The "Quiescent Supply Current" section was updated. Table 2-7 • Power Supply State per Mode is new, and Table 2-9 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode* and Table 2-11 • Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 were updated for Core Voltage 1.2 V. Notes were also updated for Table 2-9, Table 2-10, and Table 2-11 (SAR 34746). 2-7 2-8 The drive strength, IOL, and IOH value for 3.3 V GTL and 2.5 V GTL was changed from 25 mA to 20 mA in the following tables (SAR 37364): Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings Table 2-36 • I/O Output Buffer Maximum Resistances1 Table 2-40 • I/O Short Currents IOSH/IOSL Table 2-134 • Minimum and Maximum DC Input and Output Levels Table 2-138 • Minimum and Maximum DC Input and Output Levels Also added note stating "Output drive strength is below JEDEC specification." for Tables Table 2-29, Table 2-32, Table 2-36, and Table 2-40. Additionally, the IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were corrected from 51 to 35 (for 3.3 V GTL+) and from 40 to 33 (for 2.5 V GTL+) in table Table 2-23 (SAR 39715). 2-22 2-27 2-30 2-34 2-38 2-83 2-85

Figure 2-12 • AC Loading in the "3.3 V PCI, 3.3 V PCI-X" section was updated to match Table 2-127 • AC Waveforms, Measuring Points, and Capacitive Loads (SAR 34890). 2-81 In Table 2-180 • Minimum and Maximum DC Input and Output Levels, VIL and VIH were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR 37690). 2-103 The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" section in the "Pin Descriptions and Packaging" chapter: "Within the package, the VMV plane is decoupled from the simultaneous s witching noise originating from the output buffer VCCI domain" and replaced with “Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks” (SAR 38316). The datasheet mentions that "VMV pins must be connected to t he corresponding VCCI pins" for an ESD enhancement. 3-1 Pin K15 of the "FG484" pin table for A3P600L was corrected from VvB1 to VCCIB1 (SAR 38788). 4-35 Revision 10 (May 2012) The "In-System Programming (ISP) and Security" section and "Security" section were revised to clarify that although no existi ng security measures can give an absolute guarantee, Microsemi FPGAs im plement the best security available in the industry (SAR 34670). 1-2 The Y security option and Licensed DPA Logo were added to the "ProASIC3L Ordering Information" section. The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures licen se from Cryptography Research (SAR 34728). III The "ProASIC3L Device Status" table was updated to show that all ProASIC3L devices have changed in status from Advance to Production (SAR 38198). IV The opening sentence of the "General Description" section was revised for clarity to "The ProASIC3L family of Microsemi flash FPGAs dramatically reduces dynamic power consumption by 40% and static power by 50% compared to the equivalent ProASIC3 device" (SAR 22661). 1-1 The following sentence was removed from the "Advanced Architecture" section: "In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of ProASIC3L devices via an IEEE 1532 JT AG interface" (SAR 34690). 1-3 The "Specifying I/O States During Programming" section is new (SAR 34700). 1-8 Table 1-1 • I/O Standards Supported is new. The "I/Os with Advanced I/O Standards" section was revised to add definitions of hot-swap and cold-sparing (SAR 37732). 1-7 In Table 2-2 • Recommended Operating Conditions 1, VPUMP programming voltage for operation was changed from "0 to 3.45 V" to "0 to 3.6 V" (SAR 32257). 2-2 Values for 1.5 V were added to Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* and Table 2-11 • Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 (SAR 30578). 2-7, 2-8 The reference to guidelines for global spines and VersaTile rows, given in the "Global Clock Contribution—PCLOCK" section , was corrected to t he "Spine Architecture" section of the Global Re sources chapter in the ProASIC3L FPGA Fabric User's Guide (SAR 34737). 2-15 tDOUT was corrected to t DIN in Figure 2-4 • Input Buffer Timing Model and Delays (example) (SAR 37110). 2-19 Revision Changes Page

(continued) Package names used in the "Package Pin Assignments" section were revised to match standards given in Package Mechanical Drawings (SAR 34773). 4-1 July 2010 The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "ProASIC3L Device Status" table on page IV indicates the status for each device in the device family. N/A Revision Changes Page

ProASIC3L Low Power Flash FPGAs Revision 13 5-5 Revision Changes Page Revision 9 (Feb 2009) Product Brief v1.3 The "I/Os Per Package 1" table was revised to change the number of differential I/O pairs for A3PE3000L from 300 to 310. II Table 2 • ProASIC3L FPGAs Package Sizes Dimensions is new. II Revision 8 (Feb 2009) Product Brief v1.2 The "Advanced and Pro (Professional) I/Os" section was revised to add two bullets regarding wide range power supply voltage support. I

3.0 V wide range was added to the list of supported voltages in the "I/Os with

Advanced I/O Standards" section. The "Wide Range I/O Support" section is new. 1-7 Revision 7 (Aug 2008) DC and Switching Characteristics Advance v0.6

3.0 V LVCMOS wide range support data was added to Table 2-2 • Recommended

Operating Conditions 1. 2-2

3.3 V LVCMOS wide range support data was added to Table 2-23 • Summary of

Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings to Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings . 2-22 to 2-24

3.3 V LVCMOS wide range support data was added to Table 2-27 • Summary of

AC Measuring Points. 2-26 3.3 V LVCMOS wide range support text was added to the "3.3 V LVTTL / 3.3 V LVCMOS" section. 2-42 Table 2-62 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range is new. 2-50 Revision 6 (Aug 2008) DC and Switching Characteristics Advance v0.5 Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays was updated to add several new rows of values. 2-7 Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* through Table 2-11 • Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 were updated to add 1.5 V core voltage. 2-7 to 2-8 Table 2-19 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.5 V VCC is new. 2-14 Table 2-20 • Different Components Contributing to the Static Power Consumption in ProASIC3L Devices was updated to add the static PLL contribution at 1.5 V core operation. 2-14 Timing tables were updated to include tables for 1.5 V core voltage. N/A Table 2-212 • ProASIC3L CCC/PLL Specification was updated for core voltage 1.2 V and Table 2-213 • ProASIC3L CCC/PLL Specification for 1.5 V is new. 2-132, 2-133 Revision 5 (Jul 2008) Product Brief v1.1 DC and Switching Characteristics Advance v0.4 As a result of the Libero IDE v8.4 rel ease, Actel now offers a wide range of core voltage support. The document was u pdated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A

Revision 4 (June 2008) DC and Switching Characteristics Advance v0.3 Tables have been updated to include the LVCMOS 1.2 V I/O set. DDR Tables have two additional data points added to reflect both edges for Input DDR setup and hold time. Power data table has been updated to match SmartPower data rather then simulation values. N/A Table 2-1 • Absolute Maximum Ratings was updated to add VMV to the VCCI parameter row and to remove the word "o utput" from the parameter description for VCCI. Table note 3 was added. 2-1 Table 2-2 • Recommended Operating Conditions 1 was updated to add table note references and rearrange the order of notes. VMV was added to the VCCI parameter row. A new row was added for VCC, 1.5 V DC core supply voltage. The table note stating that 1.5 V data will be released at a later date is new. The table note on VMV pins is new. 2-2 Table 2-4 • Overshoot and Undershoot Limits 1. The title was revised to remove "as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 wa s revised to remove "refers only to overshoot/undershoot limits for simultaneous switching I/Os. 2-3 EQ 2 was updated. The temperature was changed to 100°C, and therefore the end result changed. 2-6 The table notes for Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* and Table 2-9 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Sleep Mode* were updated to remove VMV and include PDC6 and PDC7. The table note for Table 2-8 • Quiescent Supply Current (IDD) Characteristics, ProASIC3L Flash*Freeze Mode* was updated to include VJTAG. 2-7 Table 2-10 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode is new. 2-8 Note 2 of Table 2-11 • Quiescent Supply Current (IDD) Characteristics, No Flash*Freeze Mode1 was updated to include VCCPLL. Note 4 was updated to include PDC6 and PDC7. 2-8 Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings through Table 2-17 • Summary of I/O Outp ut Buffer Power (per pin) – Default I/O Software Settings 1 were updated to change PDC2 to PDC6 and PDC3 to PDC7. The table notes were updated to reflect that power was measured on VCCI. The subtitle of the table was changed from "Applicable to Advanced I/O Banks" to "Applicable to Pro I/O Banks." 2-9 through 2-12 The word "input" in the titles of Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 and Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 , was changed to "output." 2-11, 2-12 The value of C LOAD for single-ended 3.3 V PCI was changed to 10 from 5 in Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 through Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1. 2-11 through 2-12 Revision Changes Page

ProASIC3L Low Power Flash FPGAs Revision 13 5-7 Revision 4 (cont’d) The last section of Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.2 V VCC was made into a new table: Table 2-19 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.5 V VCC . The table numbers referenced for device-specific dynamic power for P AC9 and PAC10 were changed in Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.2 V VCC . The definition of P DC5 was updated and parameters P DC6 and P DC7 were added to Table 2-20 • Different Components Contributing to the Static Power Consumption in ProASIC3L Devices. 2-13 The "Total Static Power Consumption—PSTAT" section was updated to revise the calculation of PSTAT, including PDC6 and PDC7. 2-15 Footnote 1 was updated to include information about PAC13. 2-16 Table 2-43 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers was updated to include the hysteresis value for 1.2 V LVCMOS. 2-40 The "1.2 V LVCMOS (JESD8-12A)" section is new. 2-76 Revision 3 (Apri2008) Product Brief v1.0 The product brief was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. N/A Packaging v1.1 The "FG324" package diagram was replaced. 4-29 Revision 2 (Apr 2008) Product Brief rev. 1 Reference to M1A3P250L was removed from Table 1 • ProASIC3 Low-Power Product Family , the "I/Os Per Package 1" table, the "ProASIC3L Ordering Information" section, and the "Temperature Grade Offerings" table. The table note regarding M1A3P250L was removed from the "I/Os Per Package 1" table. I, II, III, IV Revision 1 (Feb 2008) The "PLL Behavior at Brownout Condition" section is new. 2-4 DC and Switching Characteristics Advance v0.2 Table 2-204 • A3P250L Global Resource – Applies to 1.5 V DC Core Voltage , Table 2-206 • A3P600L Global Resource – Applies to 1.5 V DC Core Voltage , Table 2-208 • A3P1000L Global Resource – Applies to 1.5 V DC Core Voltage , and Table 2-210 • A3PE3000L Global Resource – Applies to 1.5 V DC Core Voltage were updated with values for tRCKL, tRCKH, and tRCKSW. 2-128 – 2-131 The worst-case commercial conditions were added to Table 2-221 • Embedded FlashROM Access Time– Applies to 1.2 V DC Core Voltage. 2-148 Table 2-18 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at 1.2 V VCC was updated to revise the value for P AC14 and add parameters PDC1 through PDC5 to the table. 2-13 Revision Changes Page

In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "ProASIC3L Device Status" table on page IV , is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a data sheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, bu t not for production. This label only applies to the DC and Switching Characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subj ect to the Export Administ ration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information.

51700100-13/01.13 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquarter ed in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996