A3P250

A3P1000-FG484I MICROSEMI | Alldatasheet

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© 2011 Microsemi Corporation Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Military Temperature Tested and Qualified

• Each Device Tested from –55°C to 125°C Firm-Error Immune
• Not Susceptible to Neutron-Induced Configuration Loss Low Power
• Dramatic Reduction in Dynamic and Static Power
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power†
• Low Power Consumption in Flash*Freeze Mode Allows for Instantaneous Entry To / Exit From Low-Power Flash*Freeze Modeƒ
• Supports Single-Voltage System Operation
• Low-Impedance Switches High Capacity
• 250K to 3M System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off High Performance
• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System Performance
• 3.3 V, 66 MHz, 64-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit PCI (1.2 V systems) In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock ® to Secure FPGA Contents High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization Advanced and Pro (Professional) I/Os††
• 700 Mbps DDR, LVDS-Capable I/Os
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / LVCMOS 2.5 V / 5.0 V Input†
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II (A3PE3000L only)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay (A3PE3000L only)
• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the Military ProASIC ®3EL Family Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks—One Block with Integrated PLL in ProASIC3 and All Blocks with Integrated PLL in ProASIC3EL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V systems) and 350 MHz (1.5 V systems) SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous Operation: – 250 MHz: For 1.2 V Systems – 350 MHz: For 1.5 V Systems ARM® Processor Support in ProASIC3/EL FPGAs
• ARM Cortex™-M1 Soft Processor Available with or without Debug † A3P250 and A3P1000 support only 1.5 V core operation. ƒ Flash*Freeze technology is not available for A3P250 or A3P1000. ††Pro I/Os are not available on A3P250 or A3P1000. Table 1 • Military ProASIC3/EL Low-Power Devices ProASIC3/EL Devices A3P250 A3PE600L A3P1000 A3PE3000L ARM Cortex-M1 Devices1 M1A3P1000 M1A3PE3000L System Gates 250,000 600,000 1M 3M VersaTiles (D-flip-flops) 6,144 13,824 24,576 75,264 RAM kbits (1,024 bits) 36 108 144 504 4,608-Bit Blocks 8 24 32 112 FlashROM Kbits 1 1 1 1 Secure (AES) ISP

2 Yes Yes Yes Yes

Integrated PLL in CCCs 1 6 1 6 VersaNet Globals 18 18 18 18 I/O Banks 4 8 4 8 Maximum User I/Os 68 270 154 620 Package Pins VQFP PQFP FBGA VQ100 FG484 PQ208 FG144, FG484 FG484, FG896 Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. AES is not available for ARM-enabled ProASIC3/EL devices. Revision 3

Military ProASIC3/EL Low Power Flash FPGAs I/Os Per Package 1 Military ProASIC3/EL Device Status ProASIC3/EL Low Power Devices A3P250 A3PE600L A3P1000 A3PE3000L ARM Cortex-M1 Devices M1A3P1000 M1A3PE3000L Package Single- Ended I/O2 Differential I/O Pairs Single- Ended I/O2 Differential I/O Pairs Single- Ended I/O2 Differential I/O Pairs Single- Ended I/O2 Differential I/O Pairs FG484 – – 270 135 300 74 341 168 Notes: 1. When considering migrating your design to a lower- or higher- density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. "G" indicates RoHS-compliant packages. Refer to "Military ProASIC3/EL Ordering Information" on page III for the location of the "G" in the part number. 4. For A3PE3000L devices, the usage of cert ain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 5. When the Flash*Freeze pin is used to directly enable Flash*Fr eeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. Military ProASIC3/EL Devices Status M1 Military ProASIC3/EL Devices Status A3P250 Production A3PE600L Production A3P1000 Production M1A3P1000 Production A3PE3000L Production M1A3PE3000L Production

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 III Military ProASIC3/EL Ordering Information Speed Grade Blank = Standard 1 = 15% Faster than Standard A3P1000 FG_ Part Number Military ProASIC3/EL Devices Package Type

144 M Y

G Lead-Free Packaging Application (Temperature Range) M = Military ( –55°C to 125°C Junction Temperature) Blank = Standard Packaging G = RoHS-Compliant (Green) Packaging 600,000 System GatesA3PE600L= 250,000 System GatesA3P250 = 1,000,000 System GatesA3P1000 = 3,000,000 System GatesA3PE3000L= Military ProASIC3/EL Devices with ARM Cortex-M1 1,000,000 System GatesM1A3P1000 = 3,000,000 System GatesM1A3PE3000L = FG = Fine Pitch Ball Grid Array (1.0 mm pitch) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio

Military ProASIC3/EL Low Power Flash FPGAs Temperature Grade Offerings Speed Grade and Temperature Grade Matrix Contact your local Microsemi SoC Products Group (formerly Actel) representative for device availability: http://www.actel.com/contact/default.aspx. Package A3P250 A3PE600L A3P1000 A3PE3000L ARM Cortex-M1 Devices M1A3P1000 M1A3PE3000L VQ100 M – – – PQ208 – – M – FG144 – – M – FG484 – M M M FG896 – – – M Note: M = Military temperature range: –55°C to 125°C junction temperature Temperature Grade Std. –1 M Note: M = Military temperature range: –55°C to 125°C junction temperature

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 V Table of Contents Military ProASIC3/EL Device Family Overview Military ProASIC3/EL DC and Switching Characteristics Pin Descriptions and Packaging Package Pin Assignments Datasheet Information

1 – Military ProASIC3/EL Device Family Overview General Description The military ProASIC3/EL family of flash FPGAs dramatically reduc es dynamic power consumption by 40% and static power by 50%. These power savings ar e coupled with performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability, and advanced features. Microsemi’s proven Flash*Freeze technology enables military ProASIC3EL device users to shut off dynamic power instantaneously and switch the device to static mode without the need to switch off clocks or power supplies, and retaining internal states of the device. This greatly simplifies power management. In addition, optimized software tools using powe r-driven layout provide instant push-button power reduction. Nonvolatile flash technology gives military ProASIC3/EL devices the advantage of being a secure, low- power, single-chip solution that is live at power-up (LAPU). Military ProASIC3/EL devices offer dramatic dynamic power savings, giving FPGA users flexibility to combine low power with high performance. These features e nable designers to create high -density systems using existing ASIC or FPGA design flows and tools. Military ProASIC3/EL devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop (PLL). Military ProASIC3/EL devices support devices from 250K system gates to 3 million system gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os. M1 military ProASIC3/EL devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that of fers a good balance between low-power consumption and speed when implemented in an M1 military ProASIC3/EL device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. ARM Cortex-M1 is available at no cost from Microsemi for use in M1 military ProASIC3/EL FPGAs. The ARM-enabled devices have ordering numbers that begin with M1 and do not support AES decryption. Flash*Freeze Technology† Military ProASIC3EL devices offer Flash*Freeze tech nology, which allows instantaneous switching from an active state to a static state. When Flash*Freez e mode is activated, military ProASIC3EL devices enter a static state while retaining the contents of registers and SRAM. Power is conserved without the need for additional external components to turn off I/Os or clocks. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in t he field. The ability of military ProASIC3EL devices to support a 1.2 V core voltage allows for an even gr eater reduction in power consumption, which enables low total system power. When the military ProASIC3EL device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined wit h a reprogrammable, single-chip, single-voltage solution, make military ProASIC3EL devices suitable for low-power data transfer and manipulation in military-temperature applic ations where available power may be limited (e.g., in battery-powered equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced cooling). † Flash*Freeze technology is not supported on A3P1000.

Military ProASIC3/EL Device Family Overview Flash Advantages Low Powerƒ The military ProASIC3EL family of flash-based FPGAs provides a low-power advantage, and when coupled with high performance, enables designers to make power-smart choices using a single-chip, reprogrammable, and live-at-power-up device. Military ProASIC3EL devices offer 40% dynamic power and 50% static power savings by reducing the core operating voltage to 1.2 V. In addition, the power-driven layout (PDL) feature in Libero ® Integrated Design Environment (IDE) offers up to 30% additional power reduction. With Flash*Freeze technology, military ProASIC3EL device is able to retain device SRAM and logic while dynamic power is reduced to a minimum, without the need to stop clock or power s upplies. Combining these fe atures provides a low- power, feature-rich, and high-performance solution. Security Nonvolatile, flash-based military ProASIC3/EL devi ces do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. Military ProASIC3/EL devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. Military ProASIC3/EL devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In additi on, all FlashROM data in military ProASIC3/EL devices can be encryp ted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. Military ProASIC3/EL devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device securi ty solution available today. Military ProASIC3/EL devices with AES- based security allow for secure, remote field upda tes over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. Security, built into the FPGA fabric, is an inherent component of the military ProASIC3/EL family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The military ProASIC3/EL family, with FlashLock and AES security, is unique in being highly resistan t to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. A military ProASIC3/EL device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration informati on in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based military ProASIC3/EL FPGAs do not require system c onfiguration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up Flash-based military ProASIC3/EL devices support Lev el 0 of the LAPU classification standard. This feature helps in system component in itialization, execution of critic al tasks before the processor wakes up, setup and configuration of memory blocks, cl ock generation, and bus activity management. The LAPU feature of flash-based military ProASIC3/EL devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the milita ry ProASIC3/EL device's flash configuration, and unlike SRAM-b ased FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock g enerator devices from the PCB design. Flash-based military ProASIC3/EL devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. ƒ A3P1000 only supports 1.5 V core operation.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 1-3 Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM- based FPGAs, flash-based military ProASIC3/EL devices allow all functionality to be live at power-up; no external boot PROM is required. On-board securi ty mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgra des with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The military ProASIC3/EL family device architecture mitigates the need for ASIC migration at higher volumes. This makes the military ProASIC3/EL family a cost-effective ASIC replacement. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configurati on memory of military ProASIC3/EL flash-based FPGAs. Once it is programmed, the flash cell configuration element of military ProASIC3/EL FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FP GA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The military ProASIC3/EL family offers many benef its, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with 7 layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant fl ash switches allows for very high logic utilization without compromising device routability or perform ance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary military ProASIC3/EL architecture provides granularity comparable to standard-cell ASICs. The military ProASIC3/EL device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4 and Figure 1-2):

• FPGA VersaTiles
• Dedicated FlashROM
• Dedicated SRAM/FIFO memory
• Extensive CCCs and PLLs
• I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by progr amming the appropriate flash switch interconnections. The versatility of the military ProASIC3/EL core tile, as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC fami ly of third-generation-ar chitecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, re configurable interconnect programming. Maximum core utilization is possible for virtually any design.

Military ProASIC3/EL Device Family Overview User Nonvolatile FlashROM Military ProASIC3/EL devices have 1 kbit of on- chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)
• System calibration settings
• Device serialization and/or inventory control
• Subscription-based business models (for example, set-top boxes)
• Secure key storage for secure communications algorithms
• Asset management/tracking
• Date stamping
• Version management FlashROM is written using the standard military ProASIC3/EL IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or vi a direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being re ad. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. Microsemi military ProASIC3/EL development softwa re solutions, Libero IDE and Designer, have extensive support for the FlashROM. One such feat ure is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO Military ProASIC3/EL devices have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FI FO control unit. The contro l unit allows the SRAM block to be configured as a synchronous FIFO with out using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also feat ures programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the norma l Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generati on of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC Military ProASIC3 devices provide designers with flex ible clock conditioning circuit (CCC) capabilities. Each member of the military ProASI C3 family contains six CCCs, lo cated at the four corners and the centers of the east and west sides. One CCC (cen ter west side) has a PLL. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. Military ProASIC3EL devices also contain six CCCs; however, all six are equipped with a PLL. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 1-7 The CCC block has these key features:

• Wide input frequency range (f IN_CCC) = 1.5 MHz up to 250 MHz
• Output frequency range (f OUT_CCC) = 0.75 MHz up to 250 MHz
• 2 programmable delay types for clock skew minimization
• Clock frequency synthesis Additional CCC specifications:
• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration.
• Output duty cycle = 50% ± 1.5% or better
• Low output jitter: worst case < 2.5% × clock per iod peak-to-peak period jitter when single global network used
• Maximum acquisition time is 300 µs
• Exceptional tolerance to input period jitter —allowable input jitter is up to 1.5 ns
• Four precise phases; maximum misalignment bet ween adjacent phases of 40 ps × 250 MHz / fOUT_CCC Global Clocking Military ProASIC3/EL devices have extensive support fo r multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The military ProASIC3/EL family of FPGAs features a flexible I/O structure, supporting a range of ProASIC3EL devices. Military ProASIC3/EL FPGAs support different I/O standards, including single- ended, differential, and voltage-referenced (military ProASIC3EL). The I/Os are organized into banks, with two, four, or eight (military ProASIC3EL only) banks per device. The configuration of these banks determines the I/O standards supported. For military ProASIC3EL, each I/O bank is subdivided into V REF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common V REF line. Therefore, if any I/O in a given V REF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following:
• Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
• Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II). Military ProASIC3EL banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads.

2 – Military ProASIC3/EL DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Reco mmended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings1 Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V VCCI DC I/O buffer supply voltage for A3PE600/3000L DC output buffer supply voltage for A3P250/A3P1000 –0.3 to 3.75 V VMV DC input buffer supply voltage for A3P250/A3P1000 –0.3 to 3.75 V VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) V T STG

2 Storage temperature –65 to +150 °C

2 Junction temperature +150 °C

Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-7. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for recommended operating limits, refer to Table 2-2 on page 2-2.

Military ProASIC3/EL DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions 1 Symbol Parameter Military Units TA Ambient temperature –55 to 125 °C TJ Junction temperature –55 to 125 °C VCC 1.5 V DC core supply voltage 2 1.425 to 1.575 V 1.2 V – 1.5 V wide range DC core supply voltage 3 1.14 to 1.575 V VJTAG JTAG DC voltage 1.4 to 3.6 V VPUMP4 Programming voltage Programming mode 3.15 to 3.45 V Operation 5 0 to 3.6 V VCCPLL4 Analog power supply (PLL) 1.5 V DC core supply voltage 2 1.425 to 1.575 V 1.2 V – 1.5 V DC core supply voltage3 1.14 to 1.575 V VCCI and VMV4 1.2 V DC supply voltage3 1.14 to 1.26 V 1.2 V wide range DC supply voltage3 1.14 to 1.575 V 1.5 V DC supply voltage 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 V

3.0 V DC supply voltage

6 2.7 to 3.6 V 3.3 V DC supply voltage 3.0 to 3.6 V LVDS differential I/O 2.375 to 2.625 V LVPECL differential I/O 3.0 to 3.6 V Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. For A3P250 and A3P1000 3. For A3PE600L and A3PE3000L devices only, operating at VCCI  VCC. 4. See the "Pin Descriptions and Packaging" section on page 3-1 for instructions and recommendations on tie-off and supply grouping. 5. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-24 on page 2-24. VCCI should be at the same voltage within a given I/O bank. 6. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation. 7. To ensure targeted reliability standards are met across am bient and junction operating temperatures, Microsemi recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-3 Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage. Figure 2-1 • High-Temperature Data Retention (HTR) Table 2-3 • Overshoot and Undershoot Limits1 VCCI and VMV Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot (125°C)2 2.7 V or less 10% 0.72 V 5% 0.82 V 3 V 10% 0.72 V 5% 0.82 V 3.3 V 10% 0.69 V 5% 0.79 V

3.6 V 10% N/A

5% N/A Notes: 1. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 2. This table does not provide PCI overshoot/undershoot limits. 100 110 70 85 100 105 110 115 120 125 130 135 140 145 150 Temperature (ºC) Years Tj (°C) HTR Lifetime (yrs) 70 102.7 85 43.8 100 20.0 105 15.6 110 12.3 115 9.7 120 7.7 125 6.2 130 5.0 135 4.0 140 3.3 145 2.7 150 2.2

Military ProASIC3/EL DC and Switching Characteristics I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Military) Sophisticated power-up management circui try is designed into every ProASIC ®3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6. There are five regions to consider during power-up. Military ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points ( Figure 2-2 on page 2-5 and Figure 2-3 on page 2-6). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.
• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-5 PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplie s or voltage regulators to ensure proper power- up behavior. Power ramp-up should be monotonic, at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-2 and Figure 2- 3 on page 2-6 for more details). When PLL power supply voltage and/or VCC leve ls drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or t he output clock is lost. Refer to the "Power-Up/- Down Behavior of Low-Power Flash Devices" chapter of the Military ProASIC3/EL FPGA Fabric User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. Figure 2-2 • Devices Operating at 1.5 V Core – I/O State as a Function of VCCI and VCC Voltage Levels Region 1: I/O buffers are OFF Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCC VCC = 1.425 V Region 1: I/O Buffers are OFF Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc. Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCCI Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. VCC = VCCI + VT

Military ProASIC3/EL DC and Switching Characteristics Figure 2-3 • Device Operating at 1.2 V Core Voltage – I/O State as a Function of VCCI and VCC Voltage Levels; Only A3PE600L and A3PE3000L Devices Operate at 1.2 V Core Voltage Region 1: I/O buffers are OFF Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Min VCCI datasheet specification voltage at a selected I/O 2.3 V, or 3.0 V VCC VCC = 1.14 V Region 1: I/O Buffers are OFF Activation trip point: Va = 0.85 V ± 0.2 V Deactivation trip point: Vd = 0.75 V ± 0.2 V Activation trip point: Va = 0.9 V ± 0.15 V Deactivation trip point: Vd = 0.8 V ± 0.15 V VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCCI Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. VCC = VCCI + VT

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-7 Thermal Characteristics Introduction The temperature variable in the Designer software re fers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and st atic power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: T A = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-4. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The recommended maximum junction temperature is 125°C. EQ 2 shows a sample calculation of the recommended maximum power dissipation allowed for a 484-pin FBGA package at military temperature and in still air. EQ 2 Maximum Power Allowed Max. junction temp. (C) Max. ambient temp. ( C)– Table 2-4 • Package Thermal Resistivities Package Type Device Pin Count jc ja UnitsStill Air 200 ft./min. 500 ft./min. Very Thin Quad Flat Pack (VQ100) A3P250 100 10.0 35.3 29.4 27.1 C/W Plastic Quad Flat Pack (PQ208)* A3P1000 208 3.8 16.2 13.3 11.9 C/W Fine Pitch Ball Grid Array (FBGA) A3P1000 144 6.3 31.6 26.2 24.2 C/W A3PE600L 484 9.5 27.5 21.9 20.2 C/W A3PE3000L 484 4.7 20.6 15.7 14.0 C/W A3PE3000L 896 2.4 13.6 10.4 9.4 C/W * Embedded heatspreader

Military ProASIC3/EL DC and Switching Characteristics Temperature and Voltage Derating Factors Table 2-5 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 125°C, VCC = 1.14 V) Applicable to A3PE600L and A3PE3000L Only Junction Temperature Array Voltage VCC (V) –55°C –40°C 0°C 25°C 70°C 85°C 125°C Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T J = 125°C, VCC = 1.425 V) Applicable to A3P250 and A3P1000 Devices Only Junction Temperature Array Voltage VCC (V) –55°C –40°C 0°C 25°C 70°C 85°C 125°C

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-9 Calculating Power Dissipation Quiescent Supply Current Table 2-7 • Power Supply State Per Mode Power Supply Configurations Modes/Power Supplies VCC VCCPLL VCCI VJTAG VPUMP Flash*Freeze On On On On On/off/floating Sleep Off Off On Off Off Shutdown Off Off Off Off Off Static and Active On On On On On/off/floating Table 2-8 • Quiescent Supply Current (IDD) Characteristics, Flash*Freeze Mode* Core Voltage A3PE600L A3PE3000L Units Nominal (25°C) 1.2 V 0.55 2.75 mA 1.5 V 0.83 4.2 mA Typical maximum (25ºC) 1.2 V 9 17 mA

1.5 V 12 20 mA

Military maximum (125ºC) 1.2 V 65 165 mA

1.5 V 85 185 mA

Note: *IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-9 • Quiescent Supply Current (IDD) Characteristics, Sleep Mode (VCC = 0 V)* Core Voltage A3PE600L A3PE3000L Units VCCI / VJTAG = 1.2 V (per bank) Typical (25°C) 1.2 V 1.7 1.7 µA VCCI / VJTAG = 1.5 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.8 1.8 µA VCCI / VJTAG = 1.8 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.9 1.9 µA VCCI / VJTAG = 2.5 V (per bank) Typical (25°C) 1.2 V / 1.5 V 2.2 2.2 µA VCCI / VJTAG = 3.3 V (per bank) Typical (25°C) 1.2 V / 1.5 V 2.5 2.5 µA Note: *IDD = NBANKS × ICCI. Values do not include I/O static contribution, which is shown in Table 2-21 on page 2-16 (PDC6 and PDC7). Table 2-10 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode* Core Voltage A3P250 A3P1000 A3PE600L A3PE3000L Units Nominal (25°C) 1.2 V / 1.5 V N/A 0 µA Military (125ºC) 1.2 V / 1.5 V N/A 0 µA Note: *This is applicable to A3PE600L and A3PE3000L only for cold-sparable I/O devices. Not available on A3P250 or A3P1000.

Military ProASIC3/EL DC and Switching Characteristics Table 2-11 • Quiescent Supply Current (IDD), Static Mode and Active Mode 1 Core Voltage A3PE600L A3PE3000L Units ICCA Current2 Nominal (25°C) 1.2 V 0.55 2.75 mA 1.5 V 0.83 4.2 mA Typical maximum (25°C) 1.2 V 9 17 mA Military maximum (125°C) 1.2 V 65 165 mA VCCI / VJTAG = 1.2 V (per bank) Typical (25°C) 1.2 V 1.7 1.7 µA VCCI / VJTAG = 1.5 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.8 1.8 µA VCCI / VJTAG = 1.8 V (per bank) Typical (25°C) 1.2 V / 1.5 V 1.9 1.9 µA VCCI / VJTAG = 2.5 V (per bank) Typical (25°C) 1.2 V / 1.5 V 2.2 2.2 µA VCCI / VJTAG = 3.3 V (per bank) Typical (25°C) 1.2 V / 1.5 V 2.5 2.5 µA Notes: 1. IDD = N BANKS × ICCI + ICCA. JTAG counts as one bank when powered. 2. Includes VCC , VCCPLL, and VPUMP currents. 3. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-12 • Quiescent Supply Current (IDD) Characteristics for A3P250 and A3P1000 Core Voltage A3P250 A3P1000 Units Nominal (25°C) 1.5 V 3 8 mA Typical maximum (25°C) 1.5 V 15 30 mA Military maximum (125°C) 1.5 V 65 150 mA Note: IDD includes VCC , VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution (PDC6 and PDC7), which is shown in Table 2-21 on page 2-16.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-11 Power per I/O Pin Table 2-13 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Pro I/Os for A3PE600L and A3PE3000L Only VCCI (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended 3.3 V LVTTL/LVCMOS 3.3 – 16.34 3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 24.49 3.3 V LVCMOS Wide Range 3.3 – 16.34 3.3 V LVCMOS – Schmitt trigger Wide Range 3.3 – 24.49 2.5 V LVCMOS 2.5 – 4.71 2.5 V LVCMOS – Schmitt trigger 2.5 – 6.13 1.8 V LVCMOS 1.8 – 1.66 1.8 V LVCMOS – Schmitt trigger 1.8 – 1.78 1.5 V LVCMOS (JESD8-11) 1.5 – 1.01 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 0.97 1.2 V LVCMOS 1.2 – 0.60 1.2 V LVCMOS (JESD8-11) – Schmitt trigger 1.2 – 0.53 1.2 V LVCMOS Wide Range 1.2 – 0.60 1.2 V LVCMOS Schmitt trigger Wide Range 1.2 – 0.53 3.3 V PCI 3.3 – 17.76 3.3 V PCI – Schmitt trigger 3.3 – 19.10 3.3 V PCI-X 3.3 – 17.76 3.3 V PCI-X – Schmitt trigger 3.3 – 19.10 Voltage-Referenced 3.3 V GTL 3.3 2.90 7.14 2.5 V GTL 2.5 2.13 3.54 3.3 V GTL+ 3.3 2.81 2.91 2.5 V GTL+ 2.5 2.57 2.61 HSTL (I) 1.5 0.17 0.79 HSTL (II) 1.5 0.17 0.79 SSTL2 (I) 2.5 1.38 3.26 SSTL2 (II) 2.5 1.38 3.26 SSTL3 (I) 3.3 3.21 7.97 SSTL3 (II) 3.3 3.21 7.97 Differential LVDS 2.5 2.26 0.89 LVPECL 3.3 5.71 1.94 Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI.

Military ProASIC3/EL DC and Switching Characteristics Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only VMV (V) Static Power PDC6 (mW)1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.22 3.3 V LVCMOS – Wide Range 3.3 – 16.22 2.5 V LVCMOS 2.5 – 4.65 1.8 V LVCMOS 1.8 – 1.65 1.5 V LVCMOS (JESD8-11) 1.5 – 0.98 3.3 V PCI 3.3 – 17.64 3.3 V PCI-X 3.3 – 17.64 Differential LVDS 2.5 2.26 0.83 LVPECL 3.3 5.72 1.81 Notes: 1. PDC6 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VMV. Table 2-15 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only VMV (V) Static Power PDC6 (mW) 1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.23 3.3 V LVCMOS – Wide Range 3.3 – 16.23 2.5 V LVCMOS 2.5 – 4.66 1.8 V LVCMOS 1.8 – 1.64 1.5 V LVCMOS (JESD8-11) 1.5 – 0.99 3.3 V PCI 3.3 – 17.64 3.3 V PCI-X 3.3 – 17.64 Notes: 1. PDC6 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VMV.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-13 Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 Applicable to Pro I/Os for A3PE600L and A3PE3000L Only CLOAD (pF) VCCI (V) Static Power PDC7 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Single-Ended 3.3 V LVTTL/LVCMOS 5 3.3 – 148.00 3.3 V LVCMOS Wide Range 5 3.3 – 148.00 2.5 V LVCMOS 5 2.5 – 83.23 1.8 V LVCMOS 5 1.8 – 54.58 1.5 V LVCMOS (JESD8-11) 5 1.5 – 37.05 1.2 V LVCMOS 5 1.2 – 17.94 1.2 V LVCMOS Wide Range 5 1.2 – 17.94 3.3 V PCI 10 3.3 – 204.61 3.3 V PCI-X 10 3.3 – 204.61 Voltage-Referenced 3.3 V GTL 10 3.3 – 24.08 2.5 V GTL 10 2.5 – 13.52 3.3 V GTL+ 10 3.3 – 24.10 2.5 V GTL+ 10 2.5 – 13.54 HSTL (I) 20 1.5 7.08 26.22 HSTL (II) 20 1.5 13.88 27.18 SSTL2 (I) 30 2.5 16.69 105.56 SSTL2 (II) 30 2.5 25.91 116.48 SSTL3 (I) 30 3.3 26.02 114.67 SSTL3 (II) 30 3.3 42.21 131.69 Differential LVDS – 2.5 7.70 89.58 LVPECL – 3.3 19.42 167.86 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI.

Military ProASIC3/EL DC and Switching Characteristics Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only CLOAD (pF) VCCI (V) Static Power PDC7 (mW) 2 Dynamic Power PAC10 (µW/MHz) 3 Single-Ended

3.3 V LVTTL /

3.3 V LVCMOS

5 3.3 – 141.97 3.3 V LVCMOS Wide Range 5 3.3 – 141.97 2.5 V LVCMOS 5 2.5 – 79.98 1.8 V LVCMOS 5 1.8 – 52.26 1.5 V LVCMOS (JESD8-11) 5 1.5 – 35.62 3.3 V PCI 10 3.3 – 201.02 3.3 V PCI-X 10 3.3 – 201.02 Differential LVDS – 2.5 7.74 89.82 LVPECL – 3.3 19.54 167.55 Notes: 1. Dynamic Power consumption is given for software default drive strength and output slew. Output load is lower than the software default. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. Table 2-18 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only CLOAD (pF) VCCI (V) Static Power PDC7 (mW) 2 Dynamic Power PAC10 (µW/MHz) 3 Single-Ended 5 3.3 – 125.97 3.3 V LVCMOS – Wide Range 5 3.3 – 125.97 2.5 V LVCMOS 5 2.5 – 70.82 1.8 V LVCMOS 5 1.8 – 36.39 1.5 V LVCMOS (JESD8-11) 5 1.5 – 25.34 3.3 V PCI 10 3.3 – 184.92 3.3 V PCI-X 10 3.3 – 184.92 Notes: 1. Dynamic Power consumption is given for software default drive strength and output slew. Output load is lower than the software default. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-15 Power Consumption of Various Internal Resources Table 2-19 • Different Components Contributing to Dynamic Power Consumption in Military ProASIC3/EL Devices Operating at 1.2 V VCC Parameter Definition Device-Specific Dynamic Power (µW/MHz) A3PE3000L A3PE600L PAC1 Clock contribution of a Global Rib 8.34 3.99 PAC2 Clock contribution of a Global Spine 4.28 2.22 PAC3 Clock contribution of a VersaTile row 0.94 0.94 PAC4 Clock contribution of a VersaTile used as a sequential module 0.08 0.08 PAC5 First contribution of a VersaT ile used as a sequential module 0.05 PAC6 Second contribution of a VersaTile used as a sequential module 0.19 PAC7 Contribution of a VersaTile us ed as a combinatorial module 0.11 PAC8 Average contribution of a routing net 0.45 PAC9 Contribution of an I/O in put pin (standard-dependent) See Table 2-13 on page 2-11 through Table 2-15 on page 2-12. PAC10 Contribution of an I/O ou tput pin (standard-dependent) See Table 2-16 on page 2-13 through Table 2-18 on page 2-14. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 1.74

Military ProASIC3/EL DC and Switching Characteristics Table 2-20 • Different Components Contributing to Dynamic Power Consumption in Military ProASIC3 and ProASIC3/EL Devices at 1.5 V VCC Parameter Definition Device-Specific Dynamic Power (µW/MHz) A3PE3000L A3PE600L A3P1000 A3P250 PAC1 Clock contribution of a Global Rib 13.03 6.24 14.50 11.00 PAC2 Clock contribution of a Global Spine 6.69 3.47 2.48 1.58 PAC3 Clock contribution of a VersaTile row 1.46 1.46 0.81 0.81 PAC4 Clock contribution of a VersaTile used as a sequential module 0.13 0.13 0.12 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard- dependent) See Table 2-13 on page 2-11 through Table 2-15 on page 2-12. PAC10 Contribution of an I/O output pin (standard- dependent) See Table 2-16 on page 2-13 through Table 2-18 on page 2-14. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.60 Table 2-21 • Different Components Contributing to the Static Power Consumption in Military ProASIC3/EL Devices Parameter Definition Device-Specific Dynamic Power (µW) A3PE3000L A3PE600L A3P1000 A3P250 PDC0 Array static power in Sleep mode 0 mW 0 mW N/A N/A PDC1 Array static power in Active mode See Table 2-11 on page 2-10. PDC2 Array static power in Static (Idle) mode See Table 2-11 on page 2-10. PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-9. PDC4 Static PLL contributi on at 1.2 V operating core voltage (for A3PE600L and A3PE3000L only) 1.42 mW N/A Static PLL contribution 1.5 V operating core voltage 2.55 mW PDC5 Bank quiescent power (V CCI-dependent) See Table 2-8 on page 2-9, Table 2-9 on page 2-9, Table 2-11 on page 2-10. PDC6 I/O input pin static power (standard-dependent) See Table 2-13 on page 2-11. through Table 2-15 on page 2-12. PDC7 I/O output pin static power (standard-dependent) See Table 2-16 on page 2-13 through Table 2-18 on page 2-14. Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE).

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-17 Power Calculation Methodology This section describes a simplified method to estima te power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero IDE software. The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number a nd the frequency of each output clock generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-22 on page 2-19.
• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-23 on page 2-19.
• Read rate and write rate to the memory—guidel ines are provided for typical applications in Table 2-23 on page 2-19. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—P TOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—P STAT PSTAT = (PDC0 or PDC1 or PDC2 or PDC3) + NBANKS* PDC5 + NINPUTS* PDC6 + NOUTPUTS* PDC7 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption—P DYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—P CLOCK PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in Table 2-22 on page 2-19. NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 2-22 on page 2-19. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—P S-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on page 2-19. FCLK is the global clock signal frequency.

Military ProASIC3/EL DC and Switching Characteristics Combinatorial Cells Contribution—P C-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on page 2-19. FCLK is the global clock signal frequency. Routing Net Contribution—P NET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on page 2-19. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—P INPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-22 on page 2-19. FCLK is the global clock signal frequency. I/O Output Buffer Contribution—P OUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-22 on page 2-19. 1 is the I/O buffer enable rate—guidelines are provided in Table 2-23 on page 2-19. FCLK is the global clock signal frequency. RAM Contribution—P MEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations—guidelines are provided in Table 2-23 on page 2-19. PLL Contribution—P PLL PPLL = PDC4 + PAC13 * FCLKOUT FCLKOUT is the output clock frequency.1 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-19 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic elem ent relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency.
• The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – Bit 7 (MSB) = 0.78125% Enable Rate Definition Output enable rate is the average percentage of ti me during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-22 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Guideline 1 Toggle rate of VersaTile outputs 10% 2 I/O buffer toggle rate 10% Table 2-23 • Enable Rate Guidelines Recommended for Power Calculation Component Definition Guideline 1 I/O output buffer enable rate 100% 2 RAM enable rate for read operations 12.5% 3 RAM enable rate for write operations 12.5%

Military ProASIC3/EL DC and Switching Characteristics User I/O Characteristics Timing Model Figure 2-4 • Timing Model Operating Conditions: –1 Speed, Military Temperature Range (TJ = 125°C), Worst-Case VCC = 1.14 V (example for A3PE3000L and A3PE600L) DQ Y Y DQDQ DQY Combinational Cell Combinational Cell Combinational Cell I/O Module (Registered) I/O Module (Non-Registered) Register Cell Register Cell I/O Module (Registered) I/O Module (Non-Registered) LVPECL LVPECL LVDS, B-LVDS, M-LVDS LVTTL 3.3 V Output Drive Strength = 12 mA High Slew Rate Y Combinational Cell Y Combinational Cell Y Combinational Cell I/O Module (Non-Registered) LVTTL Output Drive Strength = 8 mA High Slew Rate I/O Module (Non-Registered) LVCMOS 1.5 V Output Drive Strength = 4 mA High Slew Rate LVTTL Output Drive Strength = 12 mA High Slew Rate I/O Module (Non-Registered) Input LVTTL Clock Input LVTTL Clock Input LVTTL Clock tPD = 0.78 ns tPD = 0.67 ns tDP = 1.51 ns tPD = 1.21 ns tDP = 2.09 ns tPD = 0.70 ns tDP = 2.38 ns tPD = 0.65 ns tDP = 2.84 ns tPD = 0.65 ns tPY = 1.49 ns tCLKQ = 0.76 ns tOCLKQ = 0.81 ns tSUD = 0.9 ns tOSUD = 0.43 ns tDP = 2.09 ns tPY = 1.49 ns tPY = 2.11 ns tCLKQ = 0.76 ns tSUD = 0.59 ns tPY = 1.49 ns tICLKQ = 0.33 ns tISUD = 0.36 ns tPY = 1.84 ns

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-21 Figure 2-5 • Input Buffer Timing Model and Delays (example) tPY (R) PAD Y Vtrip GND tPY (F) Vtrip 50%50% VIH VCC VIL tDOUT (R) DIN GND tDOUT (F) 50%50% VCC PAD Y tPY D CLK Q I/O Interface DIN tDIN To Array tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F))

Military ProASIC3/EL DC and Switching Characteristics Figure 2-6 • Output Buffer Model and Delays (example) tDP (R) PAD VOL tDP (F) VtripVtrip VOH VCC D 50% 50% VCC 0 V DOUT 50% 50% 0 V tDOUT (R) tDOUT (F) From Array PAD tDP Std Load D CLK Q I/O Interface DOUT D tDOUT tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F))

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-23 Figure 2-7 • Tristate Output Buffer Timing Model and Delays (example) D CLK Q D CLK Q 10% VCCI tZL Vtrip 50% tHZ 90% VCCI tZH Vtrip 50% 50% tLZ 50% EOUT PAD D E 50% tEOUT (R) 50% tEOUT (F) PAD DOUT EOUT D I/O Interface E tEOUT tZLS Vtrip 50% tZHS Vtrip 50%EOUT PAD D E 50% 50%tEOUT (R) tEOUT (F) 50% VCC VCC VCC VCCI VCC VCC VCC VOH VOL VOL tZL, tZH, tHZ, tLZ, tZLS, tZHS tEOUT = MAX(tEOUT(r), tEOUT(f))

Military ProASIC3/EL DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military Conditions—Software De fault Settings Applicable to Pro I/Os for A3PE600L and A3PE3000L Only I/O Standard Drive Strength Equiv. Software Default Drive Strength Option1 Slew Rate VIL VIH VOL VOH I OL

2 IOH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A 3.3 V LVTTL / 3.3 V LVCMOS Wide Range1,3

1.2 V LVCMOS

Wide Range1,4,5

3.3 V PCI Per PCI Specification

3.3 V PCI-X Per PCI-X Specification

HSTL (II) 15 mA Notes: 1. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength These values are for normal ranges only. 2. Currents are measured at 125°C junction temperature. 3. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification. 4. Applicable to A3PE600L and A3PE3000L devices operating at VCCI VCC. 5. All LVCMOS 1.2 V software macros support LVCMOS 1. 2 V wide range as specified in the JESD8-12 specification. 6. Output drive strength is below JEDEC specification. 7. Output slew rate can be extracted using the IBIS Models.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-25 Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military Conditions—Software Default Settings Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only I/O Standard Drive Strength Equiv. Software Default Drive Strength Option Slew Rate VIL VIH VOL VOH I OL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Wide Range1,3

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PC I-X specifications

Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. Currents are measured at 125°C junction temperature. 3. Output slew rate can be extracted using the IBIS Models. 4. Output drive strength is below JEDEC specification. 5. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification. Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military Conditions—Software Default Settings Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only I/O Standard Drive Strength Equiv. Software Default Drive Strength Option1 Slew Rate VIL VIH VOL VOH I OL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Wide Range1,3

3.3 V PCI-X Per PCI-X specifications

Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. Currents are measured at 125°C junction temperature. 3. Output slew rate can be extracted using the IBIS Models. 4. Output drive strength is below JEDEC specification. 5. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification.

Military ProASIC3/EL DC and Switching Characteristics Table 2-27 • Summary of Maximum and Minimum DC Input Levels Applicable to Military Conditions DC I/O Standard Military1 IIL

2 IIH

µA µA 3.3 V LVTTL / 3.3 V LVCMOS 15 15

3.3 V LVCMOS Wide Range 15 15

2.5 V LVCMOS 15 15

1.8 V LVCMOS 15 15

1.5 V LVCMOS 15 15

1.2 V LVCMOS Wide Range4 15 15

3.3 V PCI 15 15

3.3 V PCI-X 15 15

3.3 V GTL 15 15

2.5 V GTL 15 15

3.3 V GTL+ 15 15

2.5 V GTL+ 15 15

HSTL (I) 15 15 HSTL (II) 15 15 SSTL2 (I) 15 15 SSTL2 (II) 15 15 SSTL3 (I) 15 15 SSTL3 (II) 15 15 Notes: 1. Military temperature range: –55°C to 125°C. 2. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. Applicable to Military A3PE600L and A3PE3000L devices operating at VCCI ≥ VCC.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-27 Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-28 • Summary of AC Measuring Points Standard Input/Output Supply Voltage Input Reference Voltage (VREF_TYP) Board Termination Voltage (VTT_REF) Measuring Trip Point (Vtrip) 3.30 V – – 1.4 V 3.3 V LVCMOS Wide Range 3.30 V – – 1.4 V 2.5 V LVCMOS 2.50 V – – 1.2 V 1.8 V LVCMOS 2.50 V – – 0.90 V 1.5 V LVCMOS 1.80 V – – 0.75 V 1.2 V LVCMOS* 1.50 V – – 0.6 V 1.2 V LVCMOS Wide Range* 1.20 V – – 0.6 V 3.3 V PCI 1.20 V – – 0.285 * VCCI (RR) 3.3 V PCI-X 3.30 V – – 0.285 * VCCI (RR) 3.30 V – – 0.615 * VCCI (FF) 3.3 V GTL 2.50 V 0.8 V 1.2 V VREF 2.5 V GTL 3.30 V 0.8 V 1.2 V VREF 3.3 V GTL+ 2.50 V 1.0 V 1.5 V VREF 2.5 V GTL+ 1.50 V 1.0 V 1.5 V VREF HSTL (I) 1.50 V 0.75 V 0.75 V VREF HSTL (II) 3.30 V 0.75 V 0.75 V VREF SSTL2 (I) 3.30 V 1.25 V 1.25 V VREF SSTL2 (II) 2.50 V 1.25 V 1.25 V VREF SSTL3 (I) 2.50 V 1.5 V 1.485 V VREF SSTL3 (II) 2.50 V 1.5 V 1.485 V VREF LVDS 3.30 V – – Cross point LVPECL – – Cross point Note: *Applicable to A3PE600L and A3PE3000L devices operating at 1.2 V core regions only. Table 2-29 • I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer—High to Z tZH Enable to Pad delay through the Output Buffer—Z to High tLZ Enable to Pad delay through the Output Buffer—Low to Z tZL Enable to Pad delay through the Output Buffer—Z to Low tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to High tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

Military ProASIC3/EL DC and Switching Characteristics

1.2 V Core Operating Voltage

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Military-Case Conditions: TJ = 125°C, Worst Case VCC = 1.14 V, Worst Case VCCI Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Standard Drive Strength (mA) Equivalent Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF)2 External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tPYS (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns)

1.2 V LVCOMS

3.3 V PCI Per PCI

3.3 V PCI-X Per PCI-X

HSTL (II) 15 mA Notes: 1. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are a pplicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a specific output load, refer to Designer software. 3. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 4. All LVCMOS 1.2 V software macros s upport LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 5. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-15 on page 2-73 for connectivity. This resistor is not required during normal operation. 6. Output drive strength is below JEDEC specification. 7. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-29

1.5 V Core Voltage

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst Case VCCI Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Standard Drive Strength (mA) Equivalent Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF)2 External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tPYS (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns)

3.3 V LVCOMS

HSTL (II) 15 mA Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA dr ive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a specific output load, refer to Designer software. 3. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD8-B specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-15 on page 2-73 for connectivity. This resistor is not required during normal operation. 5. Output drive strength is below JEDEC specification. 6. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Military-Case Conditions: TJ = 125°C, Worst Case VCC = 1.425 V, Worst Case VCCI Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only I/O Standard Drive Strength (mA) Equivalent Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF)2 External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) spec. spec. LVDS 24 mA High – – 0.54 1.76 0.04 1.55 – – – – – – – LVPECL 24 mA High – – 0.54 1.68 0.04 1.31 – – – – – – – Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a specific output load, refer to Designer software. Software default load is higher. 3. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-15 on page 2-73 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-31 Detailed I/O DC Characteristics Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Military-Case Conditions: TJ = 125°C, Worst Case VCC = 1.425 V, Worst Case VCCI Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only I/O Standard Drive Strength (mA) Equivalent Software Default Drive Strength Option Slew Rate Capacitive Load (pF)2 External Resistor tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) spec. spec. Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a specific output load, refer to Designer software. Software default load is higher. 3. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-15 on page 2-73 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-34 • Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Military ProASIC3/EL DC and Switching Characteristics Table 2-35 • I/O Output Buffer Maximum Resistances 1 Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Standard Drive Strength R PULL-DOWN () 2 R PULL-UP () 3 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 4 mA 100 200

1.8 V LVCMOS 2 mA 200 225

1.5 V LVCMOS 2 mA 200 224

1.2 V LVCMOS Wide Range4 100 µA 158 158

3.3 V PCI/PCI-X Per PCI/ PCI-X specification 25 75

3.3 V GTL 20 mA 5 11 –

2.5 V GTL 20 mA 5 14 –

3.3 V GTL+ 35 mA 12 –

2.5 V GTL+ 33 mA 15 –

HSTL (I) 8 mA 50 50 HSTL (II) 15 mA 5 25 25 SSTL2 (I) 15 mA 27 31 SSTL2 (II) 18 mA 13 15 SSTL3 (I) 14 mA 44 69 SSTL3 (II) 21 mA 18 32 Notes: 1. These maximum values are provided for informational reas ons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.actel.com/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec. 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec. 4. Applicable to A3PE600L and A3PE3000L devices operating in the 1.2 V core range only. 5. Output drive strength is below JEDEC specification.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-33 Table 2-36 • I/O Output Buffer Maximum Resistances 1 Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only Standard Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 100 300

1.8 V LVCMOS 2 mA 100 200

3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75

Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.actel.com/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

Military ProASIC3/EL DC and Switching Characteristics Table 2-37 • I/O Output Buffer Maximum Resistances 1 Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only Standard Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 25 75 3.3 V LVCMOS Wide Range 100 µA Same as regular 3.3 V LVCMOS

2.5 V LVCMOS 2 mA 100 200

3.3 V PCI/PCI-X Per PCI/PC I-X specification 25 75

Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.actel.com/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec Table 2-38 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values VCCI R(WEAK PULL-UP) () R(WEAK PULL-DOWN) () Min. Max. Min. Max.

3.3 V 10 k 95 k 13 k 45 k

3.3 V (wide range I/Os) 10 k 95 k 13 k 45 k

2.5 V 11 k 100 k 17 k 74 k

1.8 V 19 k 85 k 23 k 110 k

1.5 V 20 k 120 k 17 k 156 k

1.2 V 30 k 450 k 25 k 300 k

1.2 V (wide range I/Os) 20 k 450 k 17 k 300 k

Notes: 1. R (WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) 2. R (WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-35 Table 2-39 • I/O Short Currents IOSH/IOSL Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength I OSL (mA)1 IOSH (mA)1 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 3.3 V LVCMOS Wide Range 100 µA Same s pecification as regular LVCMOS 3.3 V

2.5 V LVCMOS 4 mA 16 18

1.8 V LVCMOS 2 mA 9 11

1.5 V LVCMOS 2 mA 13 16

1.2 V LVCMOS 2 mA TBD TBD

1.2 V LVCMOS Wide Range 100 µA TBD TBD

3.3 V PCI/PCIX Per PCI/PCI-X specification Per PCI Curves

3.3 V GTL 20 mA

2.5 V GTL 20 mA 2 169 124

3.3 V GTL+ 35 mA 268 181

2.5 V GTL+ 33 mA 169 124

HSTL (I) 8 mA 32 39 HSTL (II) 15 mA 2 66 55 SSTL2 (I) 15 mA 83 87 SSTL2 (II) 18 mA 169 124 SSTL3 (I) 14 mA 51 54 SSTL3 (II) 21 mA 103 109 Notes: 1. T J = 100°C 2. Output drive strength is below JEDEC specification.

Military ProASIC3/EL DC and Switching Characteristics Table 2-40 • I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only Drive Strength I OSL (mA)* I OSH (mA)* 3.3 V LVTTL / 3.3V LVCMOS 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181 3.3 V LVCMOS Wide Range 100 µA Same s pecification as regular LVCMOS 3.3 V

2.5 V LVCMOS 2 mA 16 18

3.3 V PCI/PCI-X Per PCI/PCI-X specification 103 109

Note: *TJ = 100°C

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-37 The length of time an I/O can withstand I OSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. Table 2-41 • I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only Drive Strength I OSL (mA)* I OSH (mA)* 3.3 V LVTTL / 3.3V LVCMOS 2mA 25 27 4mA 25 27 6mA 51 54 8mA 51 54 12mA 103 109 16mA 103 109 3.3 V LVCMOS Wide Range 100 µA Same specification as regular LVCMOS 3.3 V

2.5 V LVCMOS 2mA 16 18

1.8 V LVCMOS 2mA 9 11

1.5V LVCMOS 2mA 13 16 4mA 25 33 Note: *TJ = 100°C Table 2-42 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers Applicable to A3PE600L and A3PE3000L Only Input Buffer Configuration Hysteresis Value (typical)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

1.2 V LVCMOS (Schmitt trigger mode) 40 mV

Military ProASIC3/EL DC and Switching Characteristics For example, at 110°C, the short current conditi on would have to be sustained for more than three months to cause a reliability conc ern. The I/O design does not contai n any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-43 • Duration of Short Circuit Event before Failure Temperature Time before Failure –50ºC > 20 years –40°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months 110°C 3 months 125°C 1 month Table 2-44 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C) LVDS/B-LVDS/ M-LVDS/LVPECL No requirement 10 ns * 10 years (100°C) Note: *The maximum input rise/fall time is related to the noise induced in the input buffer trace. If the noise is low, the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-39 Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-45 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray. Table 2-46 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL I OSH IIL

1 IIH

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray.

Military ProASIC3/EL DC and Switching Characteristics Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only

3.3 V LVCMOS VIL VIH VOL VOH I OL IOH IOSL IOSH IIL

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-8 • AC Loading Table 2-48 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measu ring Point* (V) VREF (Typ) (V) C LOAD (pF) 03 . 3 1 . 4 – 5 Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-41 Timing Characteristics

1.2 V DC Core Voltage

Table 2-49 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics

1.5 V DC Core Voltage

Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-43 Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-45

3.3 V LVCMOS Wide Range

Table 2-57 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only 3.3 V LVCMOS Wide Range Equiv. Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 2 IIH3 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V µA µA Max. mA Max. mA4 µA5 µA5 Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA dr ive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 125°C junction temperature. 5. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-A specification. 6. Software default selection highlighted in gray. Table 2-58 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks Equiv. Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 2 IIH3 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA4 Max. mA4 µA5 µA5 Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µ A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 2. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 125°C junction temperature. 5. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-A specification. 6. Software default selection highlighted in gray.

Military ProASIC3/EL DC and Switching Characteristics Table 2-59 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVCMOS Wide Range Equiv. Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 2 IIH3 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA Max. mA4 µA µA Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 125°C junction temperature. 5. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-A specification. 6. Software default selection highlighted in gray. Figure 2-9 • AC Loading Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measu ring Point* (V) VREF (Typ) (V) C LOAD (pF) 03 . 3 1 . 4 – 5 Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-47 Timing Characteristics Table 2-61 • 3.3 V LVCMOS Wide Range Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA dr ive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-62 • 3.3 V LVCMOS Wide Range High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. For specific junction temperature and voltage supply levels, refer to the Table 2-5 on page 2-8 for derating values. 3. Software default selection highlighted in gray.

Military ProASIC3/EL DC and Switching Characteristics Table 2-63 • 3.3 V LVCMOS Wide Range Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA dr ive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-64 • 3.3 V LVCMOS Wide Range High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-49 Table 2-65 • 3.3 V LVCMOS Wide Range Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Advanced I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-66 • 3.3 V LVCMOS Wide Range High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Advanced I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-67 • 3.3 V LVCMOS Wide Range Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Standard Plus I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-68 • 3.3 V LVCMOS Wide Range High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Standard Plus I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-51

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-69 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

2.5 V LVCMOS VIL VIH VOL VOH I OL IOH IOSL IOSH IIL

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray. Table 2-70 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray.

Military ProASIC3/EL DC and Switching Characteristics Table 2-71 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only 2.5 V LVCMOS VIL VIH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA5 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-10 • AC Loading Table 2-72 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measu ring Point* (V) VREF (Typ) (V) C LOAD (pF) 02 . 5 1 . 2 – 5 Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-53 Timing Characteristics Table 2-73 • 2.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-74 • 2.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-75 • 2.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-76 • 2.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-55 Table 2-77 • 2.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-78 • 2.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-79 • 2.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-80 • 2.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-57

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standa rd (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-81 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os for A3PE600L and A3PE3000L Only 1.8 V LVCMOS VIL VIH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray. Table 2-82 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS VIL VIH VOL V OH IOL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray.

Military ProASIC3/EL DC and Switching Characteristics Table 2-83 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-11 • AC Loading Table 2-84 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measu ring Point* (V) VREF (Typ) (V) C LOAD (pF) 01 . 8 0 . 9 – 5 Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-59 Timing Characteristics Table 2-85 • 1.8 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-86 • 1.8 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-87 • 1.8 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-88 • 1.8 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-61 Table 2-89 • 1.8 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-90 • 1.8 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-91 • 1.8 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-92 • 1.8 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-63

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-93 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/Os for A3PE600L and A3PE3000L Only 1.5 V LVCMOS VIL VIH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray. Table 2-94 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only 1.5 V LVCMOS VIL VIH V OL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray.

Military ProASIC3/EL DC and Switching Characteristics Table 2-95 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-12 • AC Loading Table 2-96 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measu ring Point* (V) VREF (Typ) (V) C LOAD (pF) 0 1.5 0.75 – 5 Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-65 Timing Characteristics Table 2-97 • 1.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-98 • 1.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-99 • 1.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-100 • 1.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-67 Table 2-101 • 1.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-102 • 1.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-103 • 1.5 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-104 • 1.5 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-69

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-105 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only 1.2 V LVCMOS1 VIL VIH VOL VOH I OL IOH IOSH IOSL IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max.4 mA Max.4 mA µA 5 µA5 Notes: 1. Applicable to A3PE600L and A3PE3000L devices only. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 100°C junction temperature and maximum voltage. 5. Currents are measured at 125°C junction temperature. 6. Software default selection highlighted in gray. Figure 2-13 • AC Loading Table 2-106 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measu ring Point* (V) VREF (Typ) (V) C LOAD (pF) 01 . 2 0 . 6 – 5 Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-107 • 1.2 V LVCMOS Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-108 • 1.2 V LVCMOS High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Unit s Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-71

1.2 V LVCMOS Wide Range

Table 2-109 • Minimum and Maximum DC Input and Output Levels Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Operating at 1.2 V Core Voltage 1.2 V LVCMOS Wide Range1 Equiv. Software Default Drive Strength Option2 VIL VIH VOL VOH I OL IOH IOSH IOSL IIL

3 IIH

Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA5 Max. mA5 µA6 µA6 Notes: 1. Applicable to A3PE600L and A3PE3000L devices only. 2. Note that 1.2 V LVCMOS wide range is applicable to 100 µA dr ive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 3. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 4. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 5. Currents are measured at 100°C junction temperature and maximum voltage. 6. Currents are measured at 125°C junction temperature. 7. Software default selection highlighted in gray. Figure 2-14 • AC Loading Table 2-110 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measu ring Point* (V) VREF (Typ) (V) C LOAD (pF) 01 . 2 0 . 6 – 5 Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-111 • 1.2 V LVCMOS Wide Range Low Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-112 • 1.2 V LVCMOS Wide Range High Slew Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Only Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Unit s Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-73 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. AC loadings are defined per the PCI/PCI-X specifications for the database; Microsemi loadings for enable path characterization are described in Figure 2-15. AC loadings are defined per PCI/PC I-X specifications for the datapath; Microsemi loading for tristate is described in Table 2-114. Table 2-113 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH I OL IOH IOSL IOSH IIL

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Per PCI specification Per PCI curves 15 15 Notes: 1. I IL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. Figure 2-15 • AC Loading Test Point Enable Path R to VCCI for tLZ / tZL / tZLS 10 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ R to GND for tHZ / tZH / tZHS R = 1 k Test Point Datapath R = 25 R to VCCI for tDP (F) R to GND for tDP (R) 10 pF Table 2-114 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (Typ) (V) C LOAD (pF) 0 3.3 0.285 * VCCI for t DP(R) 0.615 * VCCI for tDP(F) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-115 • 3.3 V PCI/PCI-X Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-116 • 3.3 V PCI/PCI-X Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-117 • 3.3 V PCI/PCI-X Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-118 • 3.3 V PCI/PCI-X Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-75 Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Timing Characteristics Table 2-119 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL VIL VIH VOL VOH I OL IOH IOSL IOSH IIL

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Output drive strength is below JEDEC specification. Figure 2-16 • AC Loading Table 2-120 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 10 pF 25GTL VTT Table 2-121 • 3.3 V GTL Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-122 • 3.3 V GTL Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-77

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Timing Characteristics Table 2-123 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL VIL VIH VOL VOH I OL IOH IOSL IOSH IIL

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Output drive strength is below JEDEC specification. Figure 2-17 • AC Loading Table 2-124 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 10 pF 25GTL VTT Table 2-125 • 2.5 V GTL Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-126 • 2.5 V GTL Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Timing Characteristics Table 2-127 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+ VIL VIH VOL VOH I OL IOH IOSL IOSH IIL

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. Figure 2-18 • AC Loading Table 2-128 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 10 pF 25GTL+ VTT Table 2-129 • 3.3 V GTL+ Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-130 • 3.3 V GTL+ Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-79

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Timing Characteristics Table 2-131 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+ VIL VIH VOL VOH I OL IOH IOSL IOSH IIL

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. Figure 2-19 • AC Loading Table 2-132 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 10 pF 25GTL+ VTT Table 2-133 • 2.5 V GTL+ Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-134 • 2.5 V GTL+ Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpo se high-speed 1.5 V bus standard (EIA/JESD8-6). Military ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push- pull output buffer. Timing Characteristics Table 2-135 • Minimum and Maximum DC Input and Output Levels HSTL Class I VIL VIH VOL V OH IOL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. Figure 2-20 • AC Loading Table 2-136 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 20 pF HSTL Class I VTT Table 2-137 • HSTL Class I Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-138 • HSTL Class I Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-81 HSTL Class II High-Speed Transceiver Logic is a general-purpo se high-speed 1.5 V bus standard (EIA/JESD8-6). Military ProASIC3E devices support Class II. This pr ovides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-139 • Minimum and Maximum DC Input and Output Levels HSTL Class II VIL VIH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. 5. Output drive strength is below JEDEC specification. Figure 2-21 • AC Loading Table 2-140 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 20 pF HSTL Class II VTT Table 2-141 • HSTL Class II Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-142 • HSTL Class II Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-83 SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Military ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-143 • Minimum and Maximum DC Input and Output Levels SSTL2 Class I VIL VIH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. Figure 2-22 • AC Loading Table 2-144 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 30 pF SSTL2 Class I VTT Table 2-145 • SSTL2 Class I Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-146 • SSTL2 Class I Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Military ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-147 • Minimum and Maximum DC Input and Output Levels SSTL2 Class II VIL VIH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. Figure 2-23 • AC Loading Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 30 pF SSTL2 Class II VTT Table 2-149 • SSTL2 Class II Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-150 • SSTL2 Class II Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-85 SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Military ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-151 • Minimum and Maximum DC Input and Output Levels SSTL3 Class I VIL V IH VOL VOH I OL IOH IOSL IOSH IIL Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. I IL is the input leakage current per I/O pin over recommended operating conditions where –0.3 V < VIN < VIL. 2. II H is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 125°C junction temperature. Figure 2-24 • AC Loading Table 2-152 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 30 pF SSTL3 Class I VTT Table 2-153 • SSTL3 Class I Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-154 • SSTL3 Class I Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Military ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-155 • Minimum and Maximum DC Input and Output Levels SSTL3 Class II VIL VIH VOL VOH I OL IOH IOSL IOSH IIL IIH Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 125°C junction temperature. Figure 2-25 • AC Loading Table 2-156 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points. Test Point 30 pF SSTL3 Class II VTT Table 2-157 • SSTL3 Class II Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-158 • SSTL3 Class II Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-87 Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjuncti on with the embedded Input R egister (InReg), Output Register (OutReg), Enable Register (EnReg), an d Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644 ) is a high-speed, differential I/O standard. It requires that one data bit be carried through two si gnal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-26. The building blocks of the LVDS transmitter-receiver are one transmitte r macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, military ProASIC3 also suppo rts Bus LVDS structure and Multipoint LVDS (M- LVDS) configuration (up to 40 nodes). Figure 2-26 • LVDS Circuit Diagram and Board-Level Implementation 140  100  Z0 = 50  Z0 = 50  165  165  P N P N INBUF_LVDS OUTBUF_LVDS FPGA FPGA Bourns Part Number: CAT16-LV4F12

Military ProASIC3/EL DC and Switching Characteristics Table 2-159 • Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units VCCI1 Supply Voltage 2.375 2.5 2.625 V VOL Output Low Voltage 0.9 1.075 1.25 V VOH Output High Voltage 1.25 1.425 1.6 V IOL2 Output Lower Current 0.65 0.91 1.16 mA IOH2 Output High Current 0.65 0.91 1.16 mA VI Input Voltage 0 – 2.925 V IIH 3,4 Input High Leakage Current –– 1 0 µ A IIL 3,5 Input Low Leakage Current –– 1 0 µ A VODIFF Differential Output Voltage 250 350 450 mV VOCM Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 V VIDIFF6 Input Differential Voltage 100 350 – mV Notes: 1. ±5% 2. IOL/IOH is defined by VO DIFF/(Resistor Network). 3. Currents are measured at 125°C junction temperature. 4. IIH is the input leakage current per IO pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 6. Differential input voltage = ±350 mV. Table 2-160 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.075 1.325 Cross point Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-89 Timing Characteristics Table 2-161 • LVDS Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY Units –1 0.68 1.59 0.05 2.11 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-162 • LVDS Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY Units –1 0.52 1.48 0.03 1.86 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-163 • LVDS Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only Speed Grade t DOUT tDP tDIN tPY Units –1 0.54 1.76 0.04 1.55 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multid rop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accomm odate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appr opriate terminations. Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-27. The input and output buffer delays are available in the LVDS section in Table 2-159 on page 2-88. Example: For a bus consisting of 20 equidistant lo ads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R S =6 0  and RT =7 0 , given Z0 =5 0  (2") and Zstub =5 0  (~1.5"). Figure 2-27 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers ... RT RT BIBUF_LVDS R + - T + - R + - T + - D + - EN EN EN EN EN Receiver Transceiver Receiver Transceiver Driver RS RS RS RS RS RS RS RSRS RS Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-91 LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differ ential I/O standard. It requires that one data bit be carried through two signal lines . Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-28. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation beca use the output standard specifications are different. Figure 2-28 • LVPECL Circuit Diagram and Board-Level Implementation Table 2-164 • Minimum and Maximum DC Input and Output Levels VCCI Supply Voltage 3.0 3.3 3.6 V VIL, VIH Input Low, Input High Voltages 0 3.3 0 3.6 0 3.9 V V VIDIFF Input Differential Voltage 300 300 300 mV Table 2-165 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.64 1.94 Cross point Note: *Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

187 W 100 

Z0 = 50  Z0 = 50  100  100  P N P N INBUF_LVPECL OUTBUF_LVPECLFPGA FPGA Bourns Part Number: CAT16-PC4F12

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-166 • LVPECL Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY Units –1 0.68 1.51 0.05 1.84 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-167 • LVPECL Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Speed Grade t DOUT tDP tDIN tPY Units –1 0.52 1.40 0.03 1.61 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-168 • LVPECL Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only Speed Grade t DOUT tDP tDIN tPY Units –1 0.54 1.68 0.04 1.31 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-93 I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Figure 2-29 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF INBUF INBUF TRIBUF CLKBUF INBUFINBUFCLKBUF Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered Pad Out CLK Enable Preset Data_out Data EOUT DOUT Enable CLK DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE D_Enable A B C D E E E E F G H I J L K Y Core Array

Military ProASIC3/EL DC and Switching Characteristics Table 2-169 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register H, DOUT tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A * See Figure 2-29 on page 2-93 for more information.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-95 Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Figure 2-30 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Enable CLK Pad Out CLK Enable CLR Data_out Data Y AA EOUT DOUT Core ArrayDQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR D_Enable BB CC DD EE FF GG LL HH JJ KK CLKBUF INBUF INBUF TRIBUF INBUF INBUF CLKBUF INBUF Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered

Military ProASIC3/EL DC and Switching Characteristics Table 2-170 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA * See Figure 2-30 on page 2-95 for more information.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-97 Input Register Figure 2-31 • Input Register Timing Diagram 50% Preset Clear Out_1 CLK Data Enable tISUE 50% 50% tISUD tIHD 50% 50% tICLKQ 1 0 tIHE tIRECPRE tIREMPRE tIRECCLR tIREMCLRtIWCLR tIWPRE tIPRE2Q tICLR2Q tICKMPWH tICKMPWL 50% 50% 50% 50% 50% 50% 50% 50%

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-171 • Input Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.33 0.39 ns tISUD Data Setup Time for the Input Data Register 0.36 0.43 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.51 0.60 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.63 0.74 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.63 0.74 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.31 0.36 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.31 0.36 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 0.36 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-172 • Input Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.25 0.30 ns tISUD Data Setup Time for the Input Data Register 0.28 0.33 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.39 0.46 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.48 0.56 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.48 0.56 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 0.28 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 0.28 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 0.22 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 0.36 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-99 Table 2-173 • Input Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.29 0.34 ns tISUD Data Setup Time for the Input Data Register 0.32 0.37 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.45 0.53 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.55 0.64 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.55 0.64 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.27 0.31 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.27 0.31 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.25 0.30 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.25 0.30 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.41 0.48 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Output Register Figure 2-32 • Output Register Timing Diagram Preset Clear DOUT CLK Data_out Enable tOSUE 50% 50% tOSUD tOHD 50% 50% tOCLKQ 1 0 tOHE tORECPRE tOREMPRE tORECCLR tOREMCLRtOWCLR tOWPRE tOPRE2Q tOCLR2Q tOCKMPWH tOCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50%

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-101 Timing Characteristics Table 2-174 • Output Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.81 0.96 ns tOSUD Data Setup Time for the Output Data Register 0.43 0.51 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.61 0.71 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.11 1.31 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.11 1.31 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.31 0.36 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.31 0.36 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-175 • Output Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.62 0.73 ns tOSUD Data Setup Time for the Output Data Register 0.33 0.39 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.46 0.55 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.85 1.00 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.85 1.00 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 0.28 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 0.28 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 0.22 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 0.36 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-176 • Output Data Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.71 0.83 ns tOSUD Data Setup Time for the Output Data Register 0.38 0.44 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.53 0.62 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.97 1.14 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.97 1.14 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.27 0.31 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.27 0.31 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.25 0.30 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.25 0.30 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.41 0.48 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-103 Output Enable Register Figure 2-33 • Output Enable Register Timing Diagram 50% Preset Clear EOUT CLK D_Enable Enable tOESUE 50% 50% tOESUDtOEHD 50% 50% tOECLKQ 1 0 tOEHE tOERECPRE tOEREMPRE tOERECCLR tOEREMCLRtOEWCLR tOEWPRE tOEPRE2Q tOECLR2Q tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% 50%

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-177 • Output Enable Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.62 0.72 ns tOESUD Data Setup Time for the Output Enable Register 0.43 0.51 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.60 0.71 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.92 1.08 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.92 1.08 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.31 0.36 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.31 0.36 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 0.36 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-178 • Output Enable Register Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.47 0.55 ns tOESUD Data Setup Time for the Output Enable Register 0.33 0.39 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.46 0.54 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.70 0.83 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.70 0.83 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 0.28 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 0.28 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 0.22 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 0.36 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 0.32 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-105 Table 2-179 • Output Enable Register Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.54 0.63 ns tOESUD Data Setup Time for the Output Enable Register 0.38 0.44 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.52 0.62 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.80 0.94 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.80 0.94 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.27 0.31 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.27 0.31 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.25 0.30 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.25 0.30 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.41 0.48 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics DDR Module Specifications Input DDR Module Figure 2-34 • Input DDR Timing Model Table 2-180 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B Input DDR Data CLK CLKBUF INBUF Out_QF (to core) FF2 FF1 INBUF CLR DDR_IN E A B C D Out_QR (to core)

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-107 Timing Characteristics Figure 2-35 • Input DDR Timing Diagram tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRICLR2Q1 12 3 4 5 6 7 8 9 CLK Data CLR Out_QR Out_QF tDDRICLKQ1 2 4 6 3 5 7 tDDRIHDtDDRISUD tDDRICLKQ2 Table 2-181 • Input DDR Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.38 0.45 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.54 0.63 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.39 0.46 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.34 0.40 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.64 0.75 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.79 0.93 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.31 0.36 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 0.22 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 0.36 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 0.32 ns FDDRIMAX Maximum Frequency for Input DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-182 • Input DDR Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for any A3PE600L/A3PE3000L Parameter Description –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.29 0.34 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.41 0.48 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.30 0.35 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.26 0.31 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.49 0.58 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.60 0.71 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.24 0.28 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 0.22 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 0.36 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 0.32 ns FDDRIMAX Maximum Frequency for Input DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-183 • Input DDR Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.33 0.39 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.47 0.55 ns tDDRISUD1 Data Setup for Input DDR (fall) 0.30 0.35 ns tDDRISUD2 Data Setup for Input DDR (rise) 0.30 0.35 ns tDDRIHD1 Data Hold for Input DDR (fall) 0.00 0.00 ns tDDRIHD2 Data Hold for Input DDR (rise) 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.56 0.65 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.69 0.81 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.27 0.31 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.25 0.30 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.41 0.48 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.37 0.43 ns FDDRIMAX Maximum Frequency for Input DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-109 Output DDR Module Figure 2-36 • Output DDR Timing Model Table 2-184 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B Data_F (from core) CLK CLKBUF Out FF2 INBUF CLR DDR_OUT Output DDR FF1 X X X X X X X A B D EC C B OUTBUFData_R (from core)

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Figure 2-37 • Output DDR Timing Diagram 116 91 0 28 3 9 tDDROREMCLR tDDROHD1tDDROREMCLR tDDROHD2tDDROSUD2 tDDROCLKQ tDDRORECCLR CLK Data_R Data_F CLR Out tDDROCLR2Q 71 0 4 Table 2-185 • Output DDR Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.97 1.14 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.52 0.62 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.52 0.62 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.11 1.30 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.31 0.36 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 0.22 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 0.36 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 0.32 ns FDDOMAX Maximum Frequency for the Output DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-111 Table 2-186 • Output DDR Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.74 0.87 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.40 0.47 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.40 0.47 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.85 1.00 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.24 0.28 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 0.22 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 0.36 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 0.32 ns FDDOMAX Maximum Frequency for the Output DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-187 • Output DDR Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.84 0.99 ns tDDRISUD1 Data_F Data Setup for Output DDR 0.46 0.54 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.46 0.54 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.96 1.13 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.27 0.31 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.25 0.30 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.41 0.48 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.37 0.43 ns FDDOMAX Maximum Frequency for the Output DDR TBD TBD MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The military ProASIC3 library offers all combinations of LUT-3 combinatorial func tions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Figure 2-38 • Sample of Combinatorial Cells MAJ3 A C BY MUX2 B A S Y AY B B A XOR2 Y NOR2 B A Y B A YOR2 INV A YAND2 B A Y NAND3B A C XOR3 YB A C NAND2

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-113 Figure 2-39 • Timing Model and Waveforms tPD A B tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell YNAND2 or Any Combinatorial Logic t PD tPD 50% VCC VCC VCC 50% GNDA, B, C 50% 50% 50% (RR) (RF) GND OUT OUT GND 50% (FF) (FR) tPD tPD

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-188 • Combinatorial Cell Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Combinatorial Cell Equation Parameter –1 Std. Units INV Y = !A t PD 0.56 0.65 ns AND2 Y = A · B t PD 0.65 0.77 ns NAND2 Y = !(A · B) t PD 0.65 0.77 ns OR2 Y = A + B t PD 0.67 0.79 ns NOR2 Y = !(A + B) t PD 0.67 0.79 ns XOR2 Y = A Bt PD 1.02 1.20 ns MAJ3 Y = MAJ(A , B, C) t PD 0.97 1.14 ns XOR3 Y = A  B Ct PD 1.21 1.42 ns MUX2 Y = A !S + B S t PD 0.70 0.82 ns AND3 Y = A · B · C t PD 0.78 0.91 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-189 • Combinatorial Cell Propagation Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for any A3PE600L/A3PE3000L Combinatorial Cell Equation Parameter –1 Std. Units INV Y = !A t PD 0.43 0.50 ns AND2 Y = A · B t PD 0.50 0.59 ns NAND2 Y = !(A · B) t PD 0.50 0.59 ns OR2 Y = A + B t PD 0.51 0.61 ns NOR2 Y = !(A + B) t PD 0.51 0.61 ns XOR2 Y = A Bt PD 0.78 0.92 ns MAJ3 Y = MAJ(A , B, C) t PD 0.74 0.87 ns XOR3 Y = A  B Ct PD 0.93 1.09 ns MUX2 Y = A !S + B S t PD 0.54 0.63 ns AND3 Y = A · B · C t PD 0.59 0.70 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-115 Table 2-190 • Combinatorial Cell Propagation Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Combinatorial Cell Equation Parameter –1 Std. Units INV Y = !A t PD 0.48 0.57 ns AND2 Y = A · B t PD 0.57 0.67 ns NAND2 Y = !(A · B) t PD 0.57 0.67 ns OR2 Y = A + B t PD 0.59 0.69 ns NOR2 Y = !(A + B) t PD 0.59 0.69 ns XOR2 Y = A Bt PD 0.89 1.04 ns MAJ3 Y = MAJ(A , B, C) t PD 0.84 0.99 ns XOR3 Y = A  B Ct PD 1.05 1.24 ns MUX2 Y = A !S + B S t PD 0.61 0.72 ns AND3 Y = A · B · C t PD 0.68 0.79 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics VersaTile Specifications as a Sequential Module The military ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide. Figure 2-40 • Sample of Sequential Cells DQ DFN1 Data CLK Out D Q DFN1C1 Data CLK Out CLR DQ DFI1E1P1 Data CLK Out En PRE D Q DFN1E1 Data CLK Out En

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-117 Figure 2-41 • Timing Model and Waveforms PRE CLR Out CLK Data EN tSUE 50% 50% tSUD tHD 50% 50% tCLKQ tHE tRECPRE tREMPRE tRECCLR tREMCLRtWCLR tWPRE tPRE2Q tCLR2Q tCKMPWH tCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50%

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-191 • Register Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.76 0.90 ns tSUD Data Setup Time for the Core Register 0.59 0.70 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.63 0.74 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.55 0.65 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.55 0.65 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.31 0.36 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.31 0.36 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-119 Table 2-192 • Register Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.58 0.69 ns tSUD Data Setup Time for the Core Register 0.45 0.53 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.48 0.57 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.42 0.50 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.42 0.50 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 0.28 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 0.28 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-193 • Register Delays Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.66 0.78 ns tSUD Data Setup Time for the Core Register 0.52 0.61 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.55 0.64 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.48 0.56 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.48 0.56 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.27 0.31 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.27 0.31 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.25 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.25 0.30 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.41 0.48 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-121 Global Resource Characteristics A3P1000 Clock Tree Topology Clock delays are device-specific. Figure 2-42 is an example of a global tree used for clock routing. The global tree presented in Figure 2-42 is driven by a CCC located on the west side of the A3P1000 device. It is used to drive all D-flip-flops in the device. Figure 2-42 • Example of Global Tree Use in an A3P1000 Device for Clock Routing Central Global Rib VersaTile Rows Global Spine CCC

Military ProASIC3/EL DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-125 . Table 2-194 to Table 2-197 on page 2-123 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-194 • A3PE600L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.14 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input LOW Delay for Global Clock 0.95 1.23 1.12 1.44 ns tRCKH Input HIGH Delay for Global Clock 0.94 1.26 1.10 1.48 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.32 0.38 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-195 • A3PE3000L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.14 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input LOW Delay for Global Clock 1.81 2.09 2.13 2.42 ns tRCKH Input HIGH Delay for Global Clock 1.80 2.13 2.12 2.45 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.32 0.38 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-123 Table 2-196 • A3PE600L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 0.82 1.07 0.97 1.26 ns tRCKH Input High Delay for Global Clock 0.81 1.10 0.95 1.30 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.30 0.35 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-197 • A3PE3000L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.62 1.87 1.90 2.20 ns tRCKH Input High Delay for Global Clock 1.61 1.90 1.89 2.24 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.30 0.35 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-198 • A3P250 Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 0.97 1.24 1.14 1.46 ns tRCKH Input High Delay for Global Clock 0.94 1.27 1.11 1.49 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.32 0.38 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values. Table 2-199 • A3P1000 Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.425 V Parameter Description –1 Std. UnitsMin.1 Max.2 Min.1 Max.2 tRCKL Input Low Delay for Global Clock 1.18 1.44 1.39 1.70 ns tRCKH Input High Delay for Global Clock 1.17 1.48 1.37 1.74 ns tRCKMPWH Minimum Pulse Width High for Global Clock ns tRCKMPWL Minimum Pulse Width Low for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.32 0.37 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-125 Clock Conditioning Circuits Timing Characteristics Table 2-200 • Military ProASIC3/EL CCC/PLL Specification For Devices Operating at 1.2 V DC Core Voltage: Applicable to A3PE600L and A3PE3000L Only Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency f IN_CCC 1.5 250 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 250 MHz Delay Increments in Programmable Delay Blocks 1, 2 360 ps Number of Programmable Values in Each Programmable Delay Block 32 Serial Clock (SCLK) for Dynamic PLL 3 100 MHz Input cycle-to-cycle jitter (peak magnitude) 1 ns Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter4 LockControl = 0 25 ns LockControl = 1 1.5 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1,2 1.2 15.65 ns Delay Range in Block: Programmable Delay 2 1,2 0.025 15.65 ns Delay Range in Block: Fixed Delay 1,2 3.5 ns CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max. Peak-to-Peak Period Jitter5,6 SSO  2 SSO  4 SSO  8 SSO  16 50 MHz to 160 MHz 2.50% 4.00% 6.00% 12.00% Notes: 1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings. 2. T J = 25°C, VCC = 1.2 V. 3. Maximum value obtained for a –1 speed grade device in worst-case military conditions. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. 5. Measurements done with LVTTL 3.3 V, 8 mA I/O drive st rength and high slew rate. VCC/VCCPLL = 1.14V, VQ/PQ/TQ type of packages, 20 pF load. 6. Switching I/Os are placed outside of the PLL bank.

Military ProASIC3/EL DC and Switching Characteristics Table 2-201 • Military ProASIC3/EL CCC/PLL Specification For Devices Operating at 1.5 V DC Core Voltage Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz Delay Increments in Programmable Delay Blocks 1, 2 160 ps Number of Programmable Values in Each Programmable Delay Block 32 Serial Clock (SCLK) for Dynamic PLL3 110 MHz Input cycle-to-cycle jitter (peak magnitude) 1.5 ns Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter LockControl = 0 1.6 ns LockControl = 1 0.8 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1,2 0.6 5.56 ns Delay Range in Block: Programmable Delay 2 1,2 0.025 5.56 ns Delay Range in Block: Fixed Delay 1,2 2.2 ns CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max. Peak-to-Peak Period Jitter 5,6 SSO  2 SSO  4 SSO  8 SSO  16 50 MHz to 250 MHz 1.00% 3.00% 5.00% 9.00% 250 MHz to 350 MHz 2.50% 4.00% 6.00% 12.00% Notes: 1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings. 2. T J = 25°C, VCC = 1.5 V. 3. Maximum value obtained for a -1 speed grade device in worst-case military conditions. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. 5. Measurements done with LVTTL 3.3 V, 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VQ/PQ/TQ type of packages, 20 pF load. 6. Switching I/Os are placed outside of the PLL bank. Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-43 • Peak-to-Peak Jitter Definition Tperiod_max Tperiod_min Output Signal

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-127 Embedded SRAM and FIFO Characteristics SRAM Figure 2-44 • RAM Models ADDRA11 DOUTA8 DOUTA7 DOUTA0 DOUTB8 DOUTB7 DOUTB0 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RAM4K9 RADDR8 RD17 RADDR7 RD16 RADDR0 RD0 WD17 WD16 WD0 WW1 WW0 RW1 RW0 PIPE REN RCLK RAM512X18 WADDR8 WADDR7 WADDR0 WEN WCLK RESETRESET

Military ProASIC3/EL DC and Switching Characteristics Figure 2-49 • RAM Reset CLK RESET_B DO Dn tCYC tCKH tCKL tRSTBQ Dm

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-131 Timing Characteristics Table 2-202 • RAM4K9 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tAS Address setup time 0.35 0.41 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.20 0.23 ns tENH REN_B, WEN_B hold time 0.13 0.16 ns tBKS BLK_B setup time 0.32 0.38 ns tBKH BLK_B hold time 0.03 0.03 ns tDS Input data (DI) setup time 0.25 0.30 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 3.26 3.84 ns Clock High to new data valid on DO (flow-through, WMODE = 1) 2.47 2.91 ns tCKQ2 Clock High to new data valid on DO (pipelined) 1.24 1.46 ns tC2CWWL Address collision clk-to-clk delay for reliable write after write on same address – applicable to closing edge 0.25 0.30 ns tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same address – applicable to opening edge 0.27 0.32 ns tC2CRWH Address collision clk-to-clk delay for re liable write access after read on same address – applicable to opening edge 0.37 0.44 ns tRSTBQ RESET_B Low to data out Low on DO (flow-through) 1.28 1.50 ns RESET_B Low to data out Low on DO (pipelined) 1.28 1.50 ns tREMRSTB RESET_B removal 0.40 0.47 ns tRECRSTB RESET_B recovery 2.08 2.44 ns tMPWRSTB RESET_B minimum pulse width 0.66 0.76 ns tCYC Clock cycle time 6.08 6.99 ns FMAX Maximum frequency 164 143 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-203 • RAM4K9 Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tAS Address setup time 0.26 0.31 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.15 0.18 ns tENH REN_B, WEN_B hold time 0.10 0.12 ns tBKS BLK_B setup time 0.25 0.29 ns tBKH BLK_B hold time 0.02 0.02 ns tDS Input data (DI) setup time 0.19 0.23 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.50 2.93 ns Clock HIGH to new data valid on DO (flow-through, WMODE = 1) 1.89 2.22 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 0.95 1.11 ns tC2CWWL Address collision clk-to-clk delay for reliable write after write on same address – applicable to closing edge 0.24 0.29 ns tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same address – applicable to opening edge 0.20 0.24 ns tC2CRWH Address collision clk-to-clk delay for re liable write access after read on same address – applicable to opening edge 0.25 0.30 ns tRSTBQ RESET_B Low to data out Low on DO (flow-through) 0.98 1.15 ns RESET_B Low to data out Low on DO (pipelined) 0.98 1.15 ns tREMRSTB RESET_B removal 0.30 0.36 ns tRECRSTB RESET_B recovery 1.59 1.87 ns tMPWRSTB RESET_B minimum pulse width 0.59 0.67 ns tCYC Clock cycle time 5.39 6.20 ns FMAX Maximum frequency 185 161 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-133 Table 2-204 • RAM4K9 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tAS Address setup time 0.30 0.35 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.17 0.20 ns tENH REN_B, WEN_B hold time 0.12 0.14 ns tBKS BLK_B setup time 0.28 0.33 ns tBKH BLK_B hold time 0.02 0.03 ns tDS Input data (DI) setup time 0.22 0.26 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 2.84 2.53 ns Clock High to new data valid on DO (flow-through, WMODE = 1) 2.15 3.33 ns tCKQ2 Clock High to new data valid on DO (pipelined) 1.08 1.27 ns tC2CWWL Address collision clk-to-clk delay for reliable write after write on same address – applicable to closing edge 0.28 0.33 ns tC2CWWH Address collision clk-to-clk delay for reliable write after write on same address – applicable to rising edge 0.26 0.30 ns tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same address – applicable to opening edge 0.38 0.45 ns tC2CWRH Address collision clk-to-clk delay for re liable write access after read on same address – applicable to opening edge 0.42 0.49 ns tRSTBQ RESET_B Low to data out Low on DO (flow-through) 1.11 1.31 ns RESET_B Low to data out Low on DO (pipelined) 1.11 1.31 ns tREMRSTB RESET_B removal 0.34 0.40 ns tRECRSTB RESET_B recovery 1.81 2.12 ns tMPWRSTB RESET_B minimum pulse width 0.26 0.30 ns tCYC Clock cycle time 3.89 4.57 ns FMAX Maximum frequency 257 219 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-205 • RAM512X18 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tAS Address setup time 0.35 0.41 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.13 0.15 ns tENH REN_B, WEN_B hold time 0.08 0.09 ns tDS Input data (DI) setup time 0.25 0.30 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 2.99 3.52 ns tCKQ2 Clock High to new data valid on DO (pipelined) 1.24 1.46 ns tC2CRWH Address collision clk-to-clk delay for re liable read access after write on same address – applicable to opening edge 0.25 0.29 ns tC2CWRH Address collision clk-to-clk delay for re liable write access after read on same address – applicable to opening edge 0.31 0.36 ns tRSTBQ RESET_B Low to data out Low on DO (flow through) 1.28 1.50 ns RESET_B Low to data out Low on DO (pipelined) 1.28 1.50 ns tREMRSTB RESET_B removal 0.40 0.47 ns tRECRSTB RESET_B recovery 2.08 2.44 ns tMPWRSTB RESET_B minimum pulse width 0.66 0.76 ns tCYC Clock cycle time 6.08 6.99 ns FMAX Maximum frequency 164 143 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-135 Table 2-206 • RAM512X18 Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tAS Address setup time 0.26 0.31 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.10 0.11 ns tENH REN_B, WEN_B hold time 0.06 0.07 ns tDS Input data (DI) setup time 0.19 0.23 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 2.29 2.69 ns tCKQ2 Clock High to new data valid on DO (pipelined) 0.95 1.12 ns tC2CRWH Address collision clk-to-clk delay for re liable read access after write on same address – applicable to opening edge 0.18 0.21 ns tC2CWRH Address collision clk-to-clk delay for re liable write access after read on same address – applicable to opening edge 0.21 0.25 ns tRSTBQ RESET_B Low to data out Low on DO (flow through) 0.98 1.15 ns RESET_B Low to data out Low on DO (pipelined) 0.98 1.15 ns tREMRSTB RESET_B removal 0.30 0.36 ns tRECRSTB RESET_B recovery 1.59 1.87 ns tMPWRSTB RESET_B minimum pulse width 0.59 0.67 ns tCYC Clock cycle time 5.39 6.20 ns FMAX Maximum frequency 185 161 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-207 • RAM512X18 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tAS Address setup time 0.30 0.35 ns tAH Address hold time 0.00 0.00 ns tENS REN_B, WEN_B setup time 0.11 0.13 ns tENH REN_B, WEN_B hold time 0.07 0.08 ns tDS Input data (DI) setup time 0.22 0.26 ns tDH Input data (DI) hold time 0.00 0.00 ns tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 2.60 3.06 ns tCKQ2 Clock High to new data valid on DO (pipelined) 1.08 1.27 ns tC2CRWH Address collision clk-to-clk delay for re liable read access after write on same address – applicable to opening edge 0.43 0.50 ns tC2CWRH Address collision clk-to-clk delay for re liable write access after read on same address – applicable to opening edge 0.50 0.59 ns tRSTBQ RESET_B Low to data out Low on DO (flow through) 1.11 1.31 ns RESET_B Low to data out Low on DO (pipelined) 1.11 1.31 ns tREMRSTB RESET_B removal 0.34 0.40 ns tRECRSTB RESET_B recovery 1.81 2.12 ns tMPWRSTB RESET_B minimum pulse width 0.26 0.30 ns tCYC Clock cycle time 3.89 4.57 ns FMAX Maximum frequency 257 219 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-137 FIFO Figure 2-50 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 WW0 RD0 ESTOP FSTOP FULL AFULL EMPTY AFVAL11 AEMPTY AFVAL10 AFVAL0 AEVAL11 AEVAL10 AEVAL0 REN RBLK RCLK WEN WBLK WCLK RPIPE WD17 WD16 WD0 RESET

Military ProASIC3/EL DC and Switching Characteristics Timing Characteristics Table 2-208 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tENS REN_B, WEN_B Setup Time 1.91 2.24 ns tENH REN_B, WEN_B Hold Time 0.03 0.03 ns tBKS BLK_B Setup Time 0.40 0.47 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.25 0.30 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 3.26 3.84 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.24 1.46 ns tRCKEF RCLK HIGH to Empty Flag Valid 2.38 2.80 ns tWCKFF WCLK HIGH to Full Flag Valid 2.26 2.66 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 8.57 10.08 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 2.34 2.76 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 8.48 9.97 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 1.28 1.50 ns RESET_B LOW to Data Out LOW on DO (pipelined) 1.28 1.50 ns tREMRSTB RESET_B Removal 0.40 0.47 ns tRECRSTB RESET_B Recovery 2.08 2.44 ns tMPWRSTB RESET_B Minimum Pulse Width 0.66 0.76 ns tCYC Clock Cycle Time 6.08 6.99 ns FMAX Maximum Frequency for FIFO 164 143 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-141 Table 2-209 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tENS REN_B, WEN_B Setup Time 1.46 1.71 ns tENH REN_B, WEN_B Hold Time 0.02 0.02 ns tBKS BLK_B Setup Time 0.40 0.47 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.19 0.23 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.50 2.93 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.95 1.11 ns tRCKEF RCLK HIGH to Empty Flag Valid 1.82 2.14 ns tWCKFF WCLK HIGH to Full Flag Valid 1.73 2.03 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.56 7.71 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.79 2.11 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.49 7.63 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.98 1.15 ns RESET_B LOW to Data Out LOW on DO (pipelined) 0.98 1.15 ns tREMRSTB RESET_B Removal 0.30 0.36 ns tRECRSTB RESET_B Recovery 1.59 1.87 ns tMPWRSTB RESET_B Minimum Pulse Width 0.59 0.67 ns tCYC Clock Cycle Time 5.39 6.20 ns FMAX Maximum Frequency for FIFO 185 161 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-210 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3P1000 Parameter Description –1 Std. Units tENS REN_B, WEN_B Setup Time 1.66 1.95 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 ns tBKS BLK_B Setup Time 1.66 1.95 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.22 0.26 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.84 3.33 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.08 1.27 ns tRCKEF RCLK HIGH to Empty Flag Valid 2.07 2.43 ns tWCKFF WCLK HIGH to Full Flag Valid 1.96 2.31 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 7.45 8.76 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 2.04 2.40 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 7.38 8.67 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 1.11 1.31 ns RESET_B LOW to Data Out LOW on DO (pipelined) 1.11 1.31 ns tREMRSTB RESET_B Removal 0.34 0.40 ns tRECRSTB RESET_B Recovery 1.81 2.12 ns tMPWRSTB RESET_B Minimum Pulse Width 0.26 0.30 ns tCYC Clock Cycle Time 3.89 4.57 ns FMAX Maximum Frequency for FIFO 257 219 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-143 Table 2-211 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3P250 (256×16) Parameter Description –1 Std. Units tENS REN_B, WEN_B Setup Time 3.92 4.61 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 ns tBKS BLK_B Setup Time 1.66 1.95 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.22 0.26 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.61 3.06 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.14 1.34 ns tRCKEF RCLK HIGH to Empty Flag Valid 2.07 2.43 ns tWCKFF WCLK HIGH to Full Flag Valid 1.96 2.31 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 7.45 8.76 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 2.04 2.40 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 7.38 8.67 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 1.11 1.31 ns RESET_B LOW to Data Out LOW on DO (pipelined) 1.11 1.31 ns tREMRSTB RESET_B Removal 0.34 0.40 ns tRECRSTB RESET_B Recovery 1.81 2.12 ns tMPWRSTB RESET_B Minimum Pulse Width 0.26 0.30 ns tCYC Clock Cycle Time 3.89 4.57 ns FMAX Maximum Frequency for FIFO 257 219 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-212 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3P250 (512×8) Parameter Description –1 Std. Units tENS REN_B, WEN_B Setup Time 4.52 5.31 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 ns tBKS BLK_B Setup Time 1.66 1.95 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.22 0.26 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.61 3.06 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.14 1.34 ns tRCKEF RCLK HIGH to Empty Flag Valid 2.07 2.43 ns tWCKFF WCLK HIGH to Full Flag Valid 1.96 2.31 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 7.45 8.76 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 2.04 2.40 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 7.38 8.67 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 1.11 1.31 ns RESET_B LOW to Data Out LOW on DO (pipelined) 1.11 1.31 ns tREMRSTB RESET_B Removal 0.34 0.40 ns tRECRSTB RESET_B Recovery 1.81 2.12 ns tMPWRSTB RESET_B Minimum Pulse Width 0.26 0.30 ns tCYC Clock Cycle Time 3.89 4.57 ns FMAX Maximum Frequency for FIFO 257 219 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-145 Table 2-213 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3P250 (1k×4) Parameter Description –1 Std. Units tENS REN_B, WEN_B Setup Time 4.88 5.73 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 ns tBKS BLK_B Setup Time 1.66 1.95 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.22 0.26 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.84 3.33 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.08 1.27 ns tRCKEF RCLK HIGH to Empty Flag Valid 2.07 2.43 ns tWCKFF WCLK HIGH to Full Flag Valid 1.96 2.31 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 7.45 8.76 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 2.04 2.40 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 7.38 8.67 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 1.11 1.31 ns RESET_B LOW to Data Out LOW on DO (pipelined) 1.11 1.31 ns tREMRSTB RESET_B Removal 0.34 0.40 ns tRECRSTB RESET_B Recovery 1.81 2.12 ns tMPWRSTB RESET_B Minimum Pulse Width 0.26 0.30 ns tCYC Clock Cycle Time 3.89 4.57 ns FMAX Maximum Frequency for FIFO 257 219 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Table 2-214 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3P250 (2k×2) Parameter Description –1 Std. Units tENS REN_B, WEN_B Setup Time 5.28 6.21 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 ns tBKS BLK_B Setup Time 1.66 1.95 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.22 0.26 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.84 3.33 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.08 1.27 ns tRCKEF RCLK HIGH to Empty Flag Valid 2.07 2.43 ns tWCKFF WCLK HIGH to Full Flag Valid 1.96 2.31 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 7.45 8.76 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 2.04 2.40 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 7.38 8.67 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 1.11 1.31 ns RESET_B LOW to Data Out LOW on DO (pipelined) 1.11 1.31 ns tREMRSTB RESET_B Removal 0.34 0.40 ns tRECRSTB RESET_B Recovery 1.81 2.12 ns tMPWRSTB RESET_B Minimum Pulse Width 0.26 0.30 ns tCYC Clock Cycle Time 3.89 4.57 ns FMAX Maximum Frequency for FIFO 257 219 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-147 Table 2-215 • FIFO Worst Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3P250 (4k×1) Parameter Description –1 Std. Units tENS REN_B, WEN_B Setup Time 5.85 6.87 ns tENH REN_B, WEN_B Hold Time 0.00 0.00 ns tBKS BLK_B Setup Time 1.66 1.95 ns tBKH BLK_B Hold Time 0.00 0.00 ns tDS Input Data (DI) Setup Time 0.22 0.26 ns tDH Input Data (DI) Hold Time 0.00 0.00 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.84 3.33 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.08 1.27 ns tRCKEF RCLK HIGH to Empty Flag Valid 2.07 2.43 ns tWCKFF WCLK HIGH to Full Flag Valid 1.96 2.31 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 7.45 8.76 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 2.04 2.40 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 7.38 8.67 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 1.11 1.31 ns RESET_B LOW to Data Out LOW on DO (pipelined) 1.11 1.31 ns tREMRSTB RESET_B Removal 0.34 0.40 ns tRECRSTB RESET_B Recovery 1.81 2.12 ns tMPWRSTB RESET_B Minimum Pulse Width 0.26 0.30 ns tCYC Clock Cycle Time 3.89 4.57 ns FMAX Maximum Frequency for FIFO 257 219 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL DC and Switching Characteristics Embedded FlashROM Characteristics Timing Characteristics Figure 2-56 • Timing Diagram A0 A1 tSU tHOLD tSU tHOLD tSU tHOLD tCKQ2 tCKQ2 tCKQ2 CLK Address Data D0 D0 D1 Table 2-216 • Embedded FlashROM Access Time Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tSU Address Setup Time 0.74 0.87 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 16.18 19.02 ns FMAX Maximum Clock Frequency 15 15 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-217 • Embedded FlashROM Access Time Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tSU Address Setup Time 0.58 0.68 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 12.77 15.01 ns FMAX Maximum Clock Frequency 15 15 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-218 • Embedded FlashROM Access Time Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000 Parameter Description –1 Std. Units tSU Address Setup Time 0.64 0.75 ns tHOLD Address Hold Time 0.00 0.00 ns tCK2Q Clock to Out 19.54 22.97 ns FMAX Maximum Clock Frequency 15 15 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-149 JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-20 for more details. Timing Characteristics Table 2-219 • JTAG 1532 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tDISU Test Data Input Setup Time 0.80 0.94 ns tDIHD Test Data Input Hold Time 1.60 1.88 ns tTMSSU Test Mode Select Setup Time 0.80 0.94 ns tTMDHD Test Mode Select Hold Time 1.60 1.88 ns tTCK2Q Clock to Q (data out) 6.39 7.52 ns tRSTB2Q Reset to Q (data out) 26.63 31.33 ns FTCKMAX TCK Maximum Frequency 18.70 15.90 MHz tTRSTREM ResetB Removal Time 0.48 0.56 ns tTRSTREC ResetB Recovery Time 0.00 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-220 • JTAG 1532 Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for All Dies Parameter Description –1 Std. Units tDISU Test Data Input Setup Time 0.60 0.71 ns tDIHD Test Data Input Hold Time 1.21 1.42 ns tTMSSU Test Mode Select Setup Time 0.60 0.71 ns tTMDHD Test Mode Select Hold Time 1.21 1.42 ns tTCK2Q Clock to Q (data out) 6.04 7.10 ns tRSTB2Q Reset to Q (data out) 24.15 28.41 ns FTCKMAX TCK Maximum Frequency 22.00 19.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.24 0.28 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

3 – Pin Descriptions and Packaging Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise orig inated from the output buffer ground domain. This minimizes the noise transfer within the package and im proves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V for A3P250 and A3P100 devices and 1.2 V or 1.5 V for A3PE600L and A3PE3000L devices. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. For A3PE600L and A3PE3000L devices, VCC can be switched dynamically from 1.2 V to 1.5 V or vice versa. This allows in-system prog ramming (ISP) when VCC is at 1. 5 V and the benefit of low power operation when VCC is at 1.2 V. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane is decoupled from the simultaneous swit ching noise originating fr om the output buffer V CCI domain. This minimizes the noise transfer within t he package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V, depending on the device.

• 1.5 V for A3P250 and A3P1000 devices
• 1.2 V or 1.5 V for A3PE600L or A3PE3000L devices When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the Miliary ProASIC3/EL Device Family User’s Guide for a complete board solution for the PLL analog power supply and ground.
• There is one VCCPLF pin on A3P250 and A3P1000 devices.
• There are six VCCPLX pins on A3PE600L and A3PE3000L devices.

Pin Descriptions and Packaging VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Microsemi Designer place-and- route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground.

• There is one VCOMPLF pin on A3P250 and A3P1000 devices.
• There are six VCOMPL pins (PLL ground) on A3PE600L and A3PE3000L devices. VJTAG JTAG Supply Voltage Military ProASIC3/EL devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and si mplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage A3P250 and A3P1000 devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. Duri ng normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in Table 2-2 on page 2-2. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User-Defined Supply Pins VREF I/O Voltage Reference Reference voltage for I/O minibanks in A3PE600L and A3PE3000L devices. VREF pins are configured by the user from regular I/Os, and any I/O in a ba nk, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards require a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its minibank. User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows:
• Output buffer is disabled (with tristate value of high impedance)
• Input buffer is disabled (with tristate value of high impedance)
• Weak pull-up is programmed

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 3-3 GL Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed Signal FPGAs " chapter of the Military ProASIC3/EL FPGA Fabric User’s Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the ch ip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the "I/O Structures in IGLOO and ProASIC3 Devices" chapter (for A3P250 and A3P1000) or "I/O Structures in IGLOOe and ProASIC3E Device s" (for A3PE600L and A3PE3000L) of the Military ProASIC3/EL FPGA Fabric User’s Guide for an explanation of the naming of global pins. FF Flash*Freeze Mode Activation Pin Flash*Freeze is available on A3PE600L and A3PE3000L devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pi n is active low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. The FF pin c an be configured as a Schmitt trigger input. When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single- ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signa l. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pul l-up. This default config uration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. Table 3-1 shows the Flash*Freeze pin location on t he available packages for Military ProASIC3/EL devices. The Flash*Freeze pin location is independent of device, allowing migration to larger or smaller devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology and Low Power Modes" chapter of the Military ProASIC3/EL FPGA Fabric User’s Guide for more information on I/O states during Flash*Freeze mode. Table 3-1 • Flash*Freeze Pin Location in Military ProASIC3/EL Packages (device-independent) Military ProASIC3/EL Packages Flash*Freeze Pin FG484 W6 FG896 AH4

Pin Descriptions and Packaging JTAG Pins Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VC C must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in s upply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull- up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-2 for more information. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP , and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull- down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 3-2 and must satisfy the parallel re sistance value requirement. The values in Table 3-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circui t could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200  to 1 k VJTAG at 2.5 V 200  to 1 k VJTAG at 1.8 V 500  to 1 k VJTAG at 1.5 V 500  to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 3-5 Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability an d performance. Microsemi IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Microsemi offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. Related Documents User’s Guides Military ProASIC3/EL Device Family User’s Guide http://www.actel.com/documents/Mil_PA3_EL_UG.pdf Packaging The following documents provide packaging information and device selection for low power flash devices. Product Catalog http://www.actel.com/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.actel.com/documents/PckgMechDrwngs.pdf This document contains the package mechanical dr awings for all packages currently or previously supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials are at http://www.actel.com/products/solutions/package/docs.aspx.

4 – Package Pin Assignments VQ100 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Note: This is the top view of the package. 100

VQ100* Pin Number A3P250 Function 1G N D

2 GAA2/IO118UDB3

3 IO118VDB3

4 GAB2/IO117UDB3

5 IO117VDB3

6 GAC2/IO116UDB3

7 IO116VDB3

8 IO112PSB3

10 GFB1/IO109PDB3

11 GFB0/IO109NDB3

12 VCOMPLF

13 GFA0/IO108NPB3

14 VCCPLF

15 GFA1/IO108PPB3

16 GFA2/IO107PSB3

17 VCC

18 VCCIB3

19 GFC2/IO105PSB3

20 GEC1/IO100PDB3

21 GEC0/IO100NDB3

22 GEA1/IO98PDB3

23 GEA0/IO98NDB3

24 VMV3

25 GNDQ

26 GEA2/IO97RSB2

27 GEB2/IO96RSB2

28 GEC2/IO95RSB2

29 IO93RSB2

30 IO92RSB2

31 IO91RSB2

32 IO90RSB2

33 IO88RSB2

34 IO86RSB2

35 IO85RSB2

36 IO84RSB2

37 VCC

38 GND

39 VCCIB2

40 IO77RSB2

41 IO74RSB2

42 IO71RSB2

43 GDC2/IO63RSB2

44 GDB2/IO62RSB2

45 GDA2/IO61RSB2

46 GNDQ

47 TCK

48 TDI

49 TMS

50 VMV2

51 GND

52 VPUMP

54 TDO

55 TRST

56 VJTAG

57 GDA1/IO60USB1

58 GDC0/IO58VDB1

59 GDC1/IO58UDB1

60 IO52NDB1

61 GCB2/IO52PDB1

62 GCA1/IO50PDB1

63 GCA0/IO50NDB1

64 GCC0/IO48NDB1

65 GCC1/IO48PDB1

66 VCCIB1

67 GND

68 VCC

69 IO43NDB1

70 GBC2/IO43PDB1

71 GBB2/IO42PSB1

72 IO41NDB1

VQ100* Pin Number A3P250 Function

73 GBA2/IO41PDB1

74 VMV1

75 GNDQ

76 GBA1/IO40RSB0

77 GBA0/IO39RSB0

78 GBB1/IO38RSB0

79 GBB0/IO37RSB0

80 GBC1/IO36RSB0

81 GBC0/IO35RSB0

82 IO29RSB0

83 IO27RSB0

84 IO25RSB0

85 IO23RSB0

86 IO21RSB0

87 VCCIB0

88 GND

89 VCC

90 IO15RSB0

91 IO13RSB0

92 IO11RSB0

93 GAC1/IO05RSB0

94 GAC0/IO04RSB0

95 GAB1/IO03RSB0

96 GAB0/IO02RSB0

97 GAA1/IO01RSB0

98 GAA0/IO00RSB0

99 GNDQ

100 VMV0

VQ100* Pin Number A3P250 Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-3 PQ208 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Note: This is the top view of the package. 208-Pin PQFP 1 208

Pin Number A3P1000 Function 1G N D

2 GAA2/IO225PDB3

3 IO225NDB3

4 GAB2/IO224PDB3

5 IO224NDB3

6 GAC2/IO223PDB3

7 IO223NDB3

8 IO222PDB3

9 IO222NDB3

10 IO220PDB3

11 IO220NDB3

12 IO218PDB3

13 IO218NDB3

14 IO216PDB3

15 IO216NDB3

16 VCC

17 GND

19 IO212PDB3

20 IO212NDB3

21 GFC1/IO209PDB3

22 GFC0/IO209NDB3

23 GFB1/IO208PDB3

24 GFB0/IO208NDB3

25 VCOMPLF

26 GFA0/IO207NPB3

27 VCCPLF

28 GFA1/IO207PPB3

29 GND

30 GFA2/IO206PDB3

31 IO206NDB3

32 GFB2/IO205PDB3

33 IO205NDB3

34 GFC2/IO204PDB3

35 IO204NDB3

36 VCC

37 IO199PDB3

38 IO199NDB3

39 IO197PSB3

40 VCCIB3

41 GND

42 IO191PDB3

43 IO191NDB3

44 GEC1/IO190PDB3

45 GEC0/IO190NDB3

46 GEB1/IO189PDB3

47 GEB0/IO189NDB3

48 GEA1/IO188PDB3

49 GEA0/IO188NDB3

50 VMV3

51 GNDQ

52 GND

53 VMV2

54 GEA2/IO187RSB2

55 GEB2/IO186RSB2

56 GEC2/IO185RSB2

57 IO184RSB2

58 IO183RSB2

59 IO182RSB2

60 IO181RSB2

61 IO180RSB2

62 VCCIB2

63 IO178RSB2

64 IO176RSB2

65 GND

66 IO174RSB2

67 IO172RSB2

68 IO170RSB2

69 IO168RSB2

70 IO166RSB2

71 VCC

72 VCCIB2

Pin Number A3P1000 Function

73 IO162RSB2

74 IO160RSB2

75 IO158RSB2

76 IO156RSB2

77 IO154RSB2

78 IO152RSB2

79 IO150RSB2

80 IO148RSB2

81 GND

82 IO143RSB2

83 IO141RSB2

84 IO139RSB2

85 IO137RSB2

86 IO135RSB2

87 IO133RSB2

88 VCC

89 VCCIB2

90 IO128RSB2

91 IO126RSB2

92 IO124RSB2

93 IO122RSB2

94 IO120RSB2

95 IO118RSB2

96 GDC2/IO116RSB2

97 GND

98 GDB2/IO115RSB2

99 GDA2/IO114RSB2

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV2

105 GND

106 VPUMP

107 GNDQ

108 TDO

Pin Number A3P1000 Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-5

109 TRST

110 VJTAG

111 GDA0/IO113NDB1

112 GDA1/IO113PDB1

113 GDB0/IO112NDB1

114 GDB1/IO112PDB1

115 GDC0/IO111NDB1

116 GDC1/IO111PDB1

117 IO109NDB1

118 IO109PDB1

119 IO106NDB1

120 IO106PDB1

121 IO104PSB1

122 GND

123 VCCIB1

124 IO99NDB1

125 IO99PDB1

127 IO96NDB1

128 GCC2/IO96PDB1

129 GCB2/IO95PSB1

130 GND

131 GCA2/IO94PSB1

132 GCA1/IO93PDB1

133 GCA0/IO93NDB1

134 GCB0/IO92NDB1

135 GCB1/IO92PDB1

136 GCC0/IO91NDB1

137 GCC1/IO91PDB1

138 IO88NDB1

139 IO88PDB1

140 VCCIB1

141 GND

142 VCC

143 IO86PSB1

144 IO84NDB1

Pin Number A3P1000 Function

145 IO84PDB1

146 IO82NDB1

147 IO82PDB1

148 IO80NDB1

149 GBC2/IO80PDB1

150 IO79NDB1

151 GBB2/IO79PDB1

152 IO78NDB1

153 GBA2/IO78PDB1

154 VMV1

155 GNDQ

156 GND

157 VMV0

158 GBA1/IO77RSB0

159 GBA0/IO76RSB0

160 GBB1/IO75RSB0

161 GBB0/IO74RSB0

162 GND

163 GBC1/IO73RSB0

164 GBC0/IO72RSB0

165 IO70RSB0

166 IO67RSB0

167 IO63RSB0

168 IO60RSB0

169 IO57RSB0

170 VCCIB0

171 VCC

172 IO54RSB0

173 IO51RSB0

174 IO48RSB0

175 IO45RSB0

176 IO42RSB0

177 IO40RSB0

178 GND

179 IO38RSB0

180 IO35RSB0

Pin Number A3P1000 Function

181 IO33RSB0

182 IO31RSB0

183 IO29RSB0

184 IO27RSB0

185 IO25RSB0

186 VCCIB0

187 VCC

188 IO22RSB0

189 IO20RSB0

190 IO18RSB0

191 IO16RSB0

192 IO15RSB0

193 IO14RSB0

194 IO13RSB0

195 GND

196 IO12RSB0

197 IO11RSB0

198 IO10RSB0

199 IO09RSB0

200 VCCIB0

201 GAC1/IO05RSB0

202 GAC0/IO04RSB0

203 GAB1/IO03RSB0

204 GAB0/IO02RSB0

205 GAA1/IO01RSB0

206 GAA0/IO00RSB0

207 GNDQ

208 VMV0

Pin Number A3P1000 Function

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. 123456789101112 A B C D E F G H J K L M A1 Ball Pad Corner

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-7 FG144 Pin Number A3P1000 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 A8 VCC A9 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO13RSB0 B6 IO26RSB0 B7 IO35RSB0 B8 IO60RSB0 B9 GBB0/IO74RSB0 B10 GBB1/IO75RSB0 B11 GND B12 VMV1 C1 IO224NDB3 C2 GFA2/IO206PPB3 C3 GAC2/IO223PDB3 C4 VCC C5 IO16RSB0 C6 IO29RSB0 C7 IO32RSB0 C8 IO63RSB0 C9 IO66RSB0 C10 GBA2/IO78PDB1 C11 IO78NDB1 C12 GBC2/IO80PPB1 D1 IO213PDB3 D2 IO213NDB3 D3 IO223NDB3 D4 GAA2/IO225PPB3 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO72RSB0 D8 GBC1/IO73RSB0 D9 GBB2/IO79PDB1 D10 IO79NDB1 D11 IO80NPB1 D12 GCB1/IO92PPB1 E1 VCC E2 GFC0/IO209NDB3 E3 GFC1/IO209PDB3 E4 VCCIB3 E5 IO225NPB3 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO91PDB1 E9 VCCIB1 E10 VCC E11 GCA0/IO93NDB1 E12 IO94NDB1 F1 GFB0/IO208NPB3 F2 VCOMPLF F3 GFB1/IO208PPB3 F4 IO206NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO91NDB1 F9 GCB0/IO92NPB1 F10 GND F11 GCA1/IO93PDB1 F12 GCA2/IO94PDB1 FG144 Pin Number A3P1000 Function G1 GFA1/IO207PPB3 G2 GND G3 VCCPLF G4 GFA0/IO207NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO111PPB1 G9 IO96NDB1 G10 GCC2/IO96PDB1 G11 IO95NDB1 G12 GCB2/IO95PDB1 H1 V CC H2 GFB2/IO205PDB3 H3 GFC2/IO204PSB3 H4 GEC1/IO190PDB3 H5 VCC H6 IO105PDB1 H7 IO105NDB1 H8 GDB2/IO115RSB2 H9 GDC0/IO111NPB1 H10 VCCIB1 H11 IO101PSB1 H12 VCC J1 GEB1/IO189PDB3 J2 IO205NDB3 J3 VCCIB3 J4 GEC0/IO190NDB3 J5 IO160RSB2 J6 IO157RSB2 J7 VCC J8 TCK J9 GDA2/IO114RSB2 J10 TDO J11 GDA1/IO113PDB1 J12 GDB1/IO112PDB1 FG144 Pin Number A3P1000 Function

Pin Number A3P1000 Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-9 FG484 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. A B C D E F G H J K L M N P R T U V W Y AA AB 12345678910111213141516171819202122 A1 Ball Pad Corner

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-11 E18 GBA2/IO36PDB2V0 E19 IO42NDB2V0 E20 GND E21 NC E22 NC F1 NC F2 IO131NDB7V1 F3 IO131PDB7V1 F4 IO133NDB7V1 F5 IO134NDB7V1 F6 VMV7 F7 VCCPLA F8 GAC0/IO02NDB0V0 F9 GAC1/IO02PDB0V0 F10 IO15NDB0V2 F11 IO15PDB0V2 F12 IO20PDB1V0 F13 IO25NDB1V0 F14 IO27PDB1V0 F15 GBC0/IO33NDB1V1 F16 VCCPLB F17 VMV2 F18 IO36NDB2V0 F19 IO42PDB2V0 F20 NC F21 NC F22 NC G1 IO127NDB7V1 G2 IO127PDB7V1 G3 NC G4 IO128PDB7V1 G5 IO129PDB7V1 G6 GAC2/IO132PDB7V1 G7 VCOMPLA G8 GNDQ FG484 Pin Number A3PE600L Function G9 IO09NDB0V1 G10 IO09PDB0V1 G11 IO13PDB0V2 G12 IO21PDB1V0 G13 IO25PDB1V0 G14 IO27NDB1V0 G15 GNDQ G16 VCOMPLB G17 GBB2/IO37PDB2V0 G18 IO39PDB2V0 G19 IO39NDB2V0 G20 IO43PDB2V0 G21 IO43NDB2V0 G22 NC H1 NC H2 NC H3 VCC H4 IO128NDB7V1 H5 IO129NDB7V1 H6 IO132NDB7V1 H7 IO130PDB7V1 H8 VMV0 H9 VCCIB0 H10 VCCIB0 H11 IO13NDB0V2 H12 IO21NDB1V0 H13 VCCIB1 H14 VCCIB1 H15 VMV1 H16 GBC2/IO38PDB2V0 H17 IO37NDB2V0 H18 IO41NDB2V0 H19 IO41PDB2V0 H20 VCC H21 NC FG484 Pin Number A3PE600L Function H22 NC J1 IO123NDB7V0 J2 IO123PDB7V0 J3 NC J4 IO124PDB7V0 J5 IO125PDB7V0 J6 IO126PDB7V0 J7 IO130NDB7V1 J8 VCCIB7 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC J14 GND J15 VCCIB2 J16 IO38NDB2V0 J17 IO40NDB2V0 J18 IO40PDB2V0 J19 IO45PDB2V1 J20 NC J21 IO48PDB2V1 J22 IO46PDB2V1 K1 IO121NDB7V0 K2 IO121PDB7V0 K3 NC K4 IO124NDB7V0 K5 IO125NDB7V0 K6 IO126NDB7V0 K7 GFC1/IO120PPB7V0 K8 VCCIB7 K9 VCC K10 GND K11 GND K12 GND FG484 Pin Number A3PE600L Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-13 R8 VMV5 R9 VCCIB5 R10 VCCIB5 R11 IO84NDB5V0 R12 IO84PDB5V0 R13 VCCIB4 R14 VCCIB4 R15 VMV3 R16 VCCPLD R17 GDB1/IO66PPB3V1 R18 GDC1/IO65PDB3V1 R19 IO61NDB3V1 R20 VCC R21 IO59NDB3V0 R22 IO62PDB3V1 T1 NC T2 IO110NDB6V0 T3 NC T4 IO105PDB6V0 T5 IO105NDB6V0 T6 GEC1/IO104PPB6V0 T7 VCOMPLE T8 GNDQ T9 GEA2/IO101PPB5V2 T10 IO92NDB5V1 T11 IO90NDB5V1 T12 IO82NDB5V0 T13 IO74NDB4V1 T14 IO74PDB4V1 T15 GNDQ T16 VCOMPLD T17 VJTAG T18 GDC0/IO65NDB3V1 T19 GDA1/IO67PDB3V1 T20 NC FG484 Pin Number A3PE600L Function T21 IO64PDB3V1 T22 IO62NDB3V1 U1 NC U2 IO107PDB6V0 U3 IO107NDB6V0 U4 GEB1/IO103PDB6V0 U5 GEB0/IO103NDB6V0 U6 VMV6 U7 VCCPLE U8 IO101NPB5V2 U9 IO95PPB5V1 U10 IO92PDB5V1 U11 IO90PDB5V1 U12 IO82PDB5V0 U13 IO76NDB4V1 U14 IO76PDB4V1 U15 VMV4 U16 TCK U17 VPUMP U18 TRST U19 GDA0/IO67NDB3V1 U20 NC U21 IO64NDB3V1 U22 IO63PDB3V1 V1 NC V2 NC V3 GND V4 GEA1/IO102PDB6V0 V5 GEA0/IO102NDB6V0 V6 GNDQ V7 GEC2/IO99PDB5V2 V8 IO95NPB5V1 V9 IO91NDB5V1 V10 IO91PDB5V1 V11 IO83NDB5V0 FG484 Pin Number A3PE600L Function V12 IO83PDB5V0 V13 IO77NDB4V1 V14 IO77PDB4V1 V15 IO69NDB4V0 V16 GDB2/IO69PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 IO63NDB3V1 W1 NC W2 NC W3 NC W4 GND W5 IO100NDB5V2 W6 FF/GEB2/IO100PDB5V2 W7 IO99NDB5V2 W8 IO88NDB5V0 W9 IO88PDB5V0 W10 IO89NDB5V0 W11 IO80NDB4V1 W12 IO81NDB4V1 W13 IO81PDB4V1 W14 IO70NDB4V0 W15 GDC2/IO70PDB4V0 W16 IO68NDB4V0 W17 GDA2/IO68PDB4V0 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB6 Y2 NC FG484 Pin Number A3PE600L Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-15 FG484 Pin Number A3P1000 Function A1 GND A2 GND A3 VCCIB0 A4 IO07RSB0 A5 IO09RSB0 A6 IO13RSB0 A7 IO18RSB0 A8 IO20RSB0 A9 IO26RSB0 A10 IO32RSB0 A11 IO40RSB0 A12 IO41RSB0 A13 IO53RSB0 A14 IO59RSB0 A15 IO64RSB0 A16 IO65RSB0 A17 IO67RSB0 A18 IO69RSB0 A19 NC A20 VCCIB0 A21 GND A22 GND B1 GND B2 VCCIB3 B3 NC B4 IO06RSB0 B5 IO08RSB0 B6 IO12RSB0 B7 IO15RSB0 B8 IO19RSB0 B9 IO24RSB0 B10 IO31RSB0 B11 IO39RSB0 B12 IO48RSB0 B13 IO54RSB0 B14 IO58RSB0 B15 IO63RSB0 B16 IO66RSB0 B17 IO68RSB0 B18 IO70RSB0 B19 NC B20 NC B21 VCCIB1 B22 GND C1 VCCIB3 C2 IO220PDB3 C3 NC C4 NC C5 GND C6 IO10RSB0 C7 IO14RSB0 C8 VCC C9 VCC C10 IO30RSB0 C11 IO37RSB0 C12 IO43RSB0 C13 NC C14 VCC C15 VCC C16 NC C17 NC C18 GND C19 NC C20 NC C21 NC C22 VCCIB1 D1 IO219PDB3 D2 IO220NDB3 D3 NC D4 GND FG484 Pin Number A3P1000 Function D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 D7 GAB0/IO02RSB0 D8 IO16RSB0 D9 IO22RSB0 D10 IO28RSB0 D11 IO35RSB0 D12 IO45RSB0 D13 IO50RSB0 D14 IO55RSB0 D15 IO61RSB0 D16 GBB1/IO75RSB0 D17 GBA0/IO76RSB0 D18 GBA1/IO77RSB0 D19 GND D20 NC D21 NC D22 NC E1 IO219NDB3 E2 NC E3 GND E4 GAB2/IO224PDB3 E5 GAA2/IO225PDB3 E6 GNDQ E7 GAB1/IO03RSB0 E8 IO17RSB0 E9 IO21RSB0 E10 IO27RSB0 E11 IO34RSB0 E12 IO44RSB0 E13 IO51RSB0 E14 IO57RSB0 E15 GBC1/IO73RSB0 E16 GBB0/IO74RSB0 E17 IO71RSB0 FG484 Pin Number A3P1000 Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-17 K13 GND K14 VCC K15 VCCIB1 K16 GCC1/IO91PPB1 K17 IO90NPB1 K18 IO88PDB1 K19 IO88NDB1 K20 IO94NPB1 K21 IO98NDB1 K22 IO98PDB1 L1 NC L2 IO200PDB3 L3 IO210NPB3 L4 GFB0/IO208NPB3 L5 GFA0/IO207NDB3 L6 GFB1/IO208PPB3 L7 VCOMPLF L8 GFC0/IO209NPB3 L9 VCC L10 GND L11 GND L12 GND L13 GND L14 VCC L15 GCC0/IO91NPB1 L16 GCB1/IO92PPB1 L17 GCA0/IO93NPB1 L18 IO96NPB1 L19 GCB0/IO92NPB1 L20 IO97PDB1 L21 IO97NDB1 L22 IO99NPB1 M1 NC M2 IO200NDB3 M3 IO206NDB3 FG484 Pin Number A3P1000 Function M4 GFA2/IO206PDB3 M5 GFA1/IO207PDB3 M6 VCCPLF M7 IO205NDB3 M8 GFB2/IO205PDB3 M9 VCC M10 GND M11 GND M12 GND M13 GND M14 VCC M15 GCB2/IO95PPB1 M16 GCA1/IO93PPB1 M17 GCC2/IO96PPB1 M18 IO100PPB1 M19 GCA2/IO94PPB1 M20 IO101PPB1 M21 IO99PPB1 M22 NC N1 IO201NDB3 N2 IO201PDB3 N3 NC N4 GFC2/IO204PDB3 N5 IO204NDB3 N6 IO203NDB3 N7 IO203PDB3 N8 VCCIB3 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB1 N16 IO95NPB1 FG484 Pin Number A3P1000 Function N17 IO100NPB1 N18 IO102NDB1 N19 IO102PDB1 N20 NC N21 IO101NPB1 N22 IO103PDB1 P1 NC P2 IO199PDB3 P3 IO199NDB3 P4 IO202NDB3 P5 IO202PDB3 P6 IO196PPB3 P7 IO193PPB3 P8 VCCIB3 P9 GND P10 VCC P11 VCC P12 VCC P13 VCC P14 GND P15 VCCIB1 P16 GDB0/IO112NPB1 P17 IO106NDB1 P18 IO106PDB1 P19 IO107PDB1 P20 NC P21 IO104PDB1 P22 IO103NDB1 R1 NC R2 IO197PPB3 R3 VCC R4 IO197NPB3 R5 IO196NPB3 R6 IO193NPB3 R7 GEC0/IO190NPB3 FG484 Pin Number A3P1000 Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-19 Y3 NC Y4 IO182RSB2 Y5 GND Y6 IO177RSB2 Y7 IO174RSB2 Y8 VCC Y9 VCC Y10 IO154RSB2 Y11 IO148RSB2 Y12 IO140RSB2 Y13 NC Y14 VCC Y15 VCC Y16 NC Y17 NC Y18 GND Y19 NC Y20 NC Y21 NC Y22 VCCIB1 AA1 GND AA2 VCCIB3 AA3 NC AA4 IO181RSB2 AA5 IO178RSB2 AA6 IO175RSB2 AA7 IO169RSB2 AA8 IO166RSB2 AA9 IO160RSB2 AA10 IO152RSB2 AA11 IO146RSB2 AA12 IO139RSB2 AA13 IO133RSB2 AA14 NC AA15 NC FG484 Pin Number A3P1000 Function AA16 IO122RSB2 AA17 IO119RSB2 AA18 IO117RSB2 AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 IO180RSB2 AB5 IO176RSB2 AB6 IO173RSB2 AB7 IO167RSB2 AB8 IO162RSB2 AB9 IO156RSB2 AB10 IO150RSB2 AB11 IO145RSB2 AB12 IO144RSB2 AB13 IO132RSB2 AB14 IO127RSB2 AB15 IO126RSB2 AB16 IO123RSB2 AB17 IO121RSB2 AB18 IO118RSB2 AB19 NC AB20 VCCIB2 AB21 GND AB22 GND FG484 Pin Number A3P1000 Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-21 C18 GND C19 IO76PPB1V4 C20 IO88NDB2V0 C21 IO94PPB2V1 C22 VCCIB2 D1 IO293PDB7V2 D2 IO303NDB7V3 D3 IO305NDB7V3 D4 GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO20PDB0V2 D9 IO22PDB0V2 D10 IO30PDB0V3 D11 IO38NDB0V4 D12 IO52NDB1V1 D13 IO52PDB1V1 D14 IO66NDB1V3 D15 IO66PDB1V3 D16 GBB1/IO80PDB1V4 D17 GBA0/IO81NDB1V4 D18 GBA1/IO81PDB1V4 D19 GND D20 IO88PDB2V0 D21 IO90PDB2V1 D22 IO94NPB2V1 E1 IO293NDB7V2 E2 IO299PPB7V3 E3 GND E4 GAB2/IO308PDB7V4 E5 GAA2/IO309PDB7V4 E6 GNDQ E7 GAB1/IO01PDB0V0 E8 IO20NDB0V2 FG484 Pin Number A3PE3000L Function E9 IO22NDB0V2 E10 IO30NDB0V3 E11 IO38PDB0V4 E12 IO44NDB1V0 E13 IO58NDB1V2 E14 IO58PDB1V2 E15 GBC1/IO79PDB1V4 E16 GBB0/IO80NDB1V4 E17 GNDQ E18 GBA2/IO82PDB2V0 E19 IO86NDB2V0 E20 GND E21 IO90NDB2V1 E22 IO98PDB2V2 F1 IO299NPB7V3 F2 IO301NDB7V3 F3 IO301PDB7V3 F4 IO308NDB7V4 F5 IO309NDB7V4 F6 VMV7 F7 VCCPLA F8 GAC0/IO02NDB0V0 F9 GAC1/IO02PDB0V0 F10 IO32NDB0V3 F11 IO32PDB0V3 F12 IO44PDB1V0 F13 IO50NDB1V1 F14 IO60PDB1V2 F15 GBC0/IO79NDB1V4 F16 VCCPLB F17 VMV2 F18 IO82NDB2V0 F19 IO86PDB2V0 F20 IO96PDB2V1 F21 IO96NDB2V1 FG484 Pin Number A3PE3000L Function F22 IO98NDB2V2 G1 IO289NDB7V1 G2 IO289PDB7V1 G3 IO291PPB7V2 G4 IO295PDB7V2 G5 IO297PDB7V2 G6 GAC2/IO307PDB7V4 G7 VCOMPLA G8 GNDQ G9 IO26NDB0V3 G10 IO26PDB0V3 G11 IO36PDB0V4 G12 IO42PDB1V0 G13 IO50PDB1V1 G14 IO60NDB1V2 G15 GNDQ G16 VCOMPLB G17 GBB2/IO83PDB2V0 G18 IO92PDB2V1 G19 IO92NDB2V1 G20 IO102PDB2V2 G21 IO102NDB2V2 G22 IO105NDB2V2 H1 IO286PSB7V1 H2 IO291NPB7V2 H3 VCC H4 IO295NDB7V2 H5 IO297NDB7V2 H6 IO307NDB7V4 H7 IO287PDB7V1 H8 VMV0 H9 VCCIB0 H10 VCCIB0 H11 IO36NDB0V4 H12 IO42NDB1V0 FG484 Pin Number A3PE3000L Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-23 N8 VCCIB6 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB3 N16 IO116NPB3V0 N17 IO132NPB3V2 N18 IO117NPB3V0 N19 IO132PPB3V2 N20 GNDQ N21 IO126NDB3V1 N22 IO128PDB3V1 P1 IO247PDB6V1 P2 IO253PDB6V2 P3 IO270NPB6V4 P4 IO261NPB6V3 P5 IO249PPB6V1 P6 IO259PDB6V3 P7 IO259NDB6V3 P8 VCCIB6 P9 GND P10 VCC P11 VCC P12 VCC P13 VCC P14 GND P15 VCCIB3 P16 GDB0/IO152NPB3V4 P17 IO136NDB3V2 P18 IO136PDB3V2 P19 IO138PDB3V3 P20 VMV3 FG484 Pin Number A3PE3000L Function P21 IO130PDB3V2 P22 IO128NDB3V1 R1 IO247NDB6V1 R2 IO245PDB6V1 R3 VCC R4 IO249NPB6V1 R5 IO251NDB6V2 R6 IO251PDB6V2 R7 GEC0/IO236NPB6V0 R8 VMV5 R9 VCCIB5 R10 VCCIB5 R11 IO196NDB5V0 R12 IO196PDB5V0 R13 VCCIB4 R14 VCCIB4 R15 VMV3 R16 VCCPLD R17 GDB1/IO152PPB3V4 R18 GDC1/IO151PDB3V4 R19 IO138NDB3V3 R20 VCC R21 IO130NDB3V2 R22 IO134PDB3V2 T1 IO243PPB6V1 T2 IO245NDB6V1 T3 IO243NPB6V1 T4 IO241PDB6V0 T5 IO241NDB6V0 T6 GEC1/IO236PPB6V0 T7 VCOMPLE T8 GNDQ T9 GEA2/IO233PPB5V4 T10 IO206NDB5V1 T11 IO202NDB5V1 FG484 Pin Number A3PE3000L Function T12 IO194NDB5V0 T13 IO186NDB4V4 T14 IO186PDB4V4 T15 GNDQ T16 VCOMPLD T17 VJTAG T18 GDC0/IO151NDB3V4 T19 GDA1/IO153PDB3V4 T20 IO144PDB3V3 T21 IO140PDB3V3 T22 IO134NDB3V2 U1 IO240PPB6V0 U2 IO238PDB6V0 U3 IO238NDB6V0 U4 GEB1/IO235PDB6V0 U5 GEB0/IO235NDB6V0 U6 VMV6 U7 VCCPLE U8 IO233NPB5V4 U9 IO222PPB5V3 U10 IO206PDB5V1 U11 IO202PDB5V1 U12 IO194PDB5V0 U13 IO176NDB4V2 U14 IO176PDB4V2 U15 VMV4 U16 TCK U17 VPUMP U18 TRST U19 GDA0/IO153NDB3V4 U20 IO144NDB3V3 U21 IO140NDB3V3 U22 IO142PDB3V3 V1 IO239PDB6V0 V2 IO240NPB6V0 FG484 Pin Number A3PE3000L Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-25 FG896 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Note: This is the bottom view. A1 Ball Pad Corner A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 123456789101112131415161718192021222324252627282930 AG AH AJ AK

Pin Number A3PE3000L Function A2 GND A3 GND A4 IO14NPB0V1 A5 GND A6 IO07NPB0V0 A7 GND A8 IO09NDB0V1 A9 IO17NDB0V2 A10 IO17PDB0V2 A11 IO21NDB0V2 A12 IO21PDB0V2 A13 IO33NDB0V4 A14 IO33PDB0V4 A15 IO35NDB0V4 A16 IO35PDB0V4 A17 IO41NDB1V0 A18 IO43NDB1V0 A19 IO43PDB1V0 A20 IO45NDB1V0 A21 IO45PDB1V0 A22 IO57NDB1V2 A23 IO57PDB1V2 A24 GND A25 IO69PPB1V3 A26 GND A27 GBC1/IO79PPB1V4 A28 GND A29 GND AA1 IO256PDB6V2 AA2 IO248PDB6V1 AA3 IO248NDB6V1 AA4 IO246NDB6V1 AA5 GEA1/IO234PDB6V0 AA6 GEA0/IO234NDB6V0 AA7 IO243PPB6V1 AA8 IO245NDB6V1 AA9 GEB1/IO235PPB6V0 AA10 VCC AA11 IO226PPB5V4 AA12 VCCIB5 AA13 VCCIB5 AA14 VCCIB5 AA15 VCCIB5 AA16 VCCIB4 AA17 VCCIB4 AA18 VCCIB4 AA19 VCCIB4 AA20 IO174PDB4V2 AA21 VCC AA22 IO142NPB3V3 AA23 IO144NDB3V3 AA24 IO144PDB3V3 AA25 IO146NDB3V4 AA26 IO146PDB3V4 AA27 IO147PDB3V4 AA28 IO139NDB3V3 AA29 IO139PDB3V3 AA30 IO133NDB3V2 AB1 IO256NDB6V2 AB2 IO244PDB6V1 AB3 IO244NDB6V1 AB4 IO241PDB6V0 AB5 IO241NDB6V0 AB6 IO243NPB6V1 AB7 VCCIB6 AB8 VCCPLE AB9 VCC AB10 IO222PDB5V3 AB11 IO218PPB5V3 AB12 IO206NDB5V1 AB13 IO206PDB5V1 AB14 IO198NDB5V0 FG896 Pin Number A3PE3000L Function AB15 IO198PDB5V0 AB16 IO192NDB4V4 AB17 IO192PDB4V4 AB18 IO178NDB4V3 AB19 IO178PDB4V3 AB20 IO174NDB4V2 AB21 IO162NPB4V1 AB22 VCC AB23 VCCPLD AB24 VCCIB3 AB25 IO150PDB3V4 AB26 IO148PDB3V4 AB27 IO147NDB3V4 AB28 IO145PDB3V3 AB29 IO143PDB3V3 AB30 IO137PDB3V2 AC1 IO254PDB6V2 AC2 IO254NDB6V2 AC3 IO240PDB6V0 AC4 GEC1/IO236PDB6V0 AC5 IO237PDB6V0 AC6 IO237NDB6V0 AC7 VCOMPLE AC8 GND AC9 IO226NPB5V4 AC10 IO222NDB5V3 AC11 IO216NPB5V2 AC12 IO210NPB5V2 AC13 IO204NDB5V1 AC14 IO204PDB5V1 AC15 IO194NDB5V0 AC16 IO188NDB4V4 AC17 IO188PDB4V4 AC18 IO182PPB4V3 AC19 IO170NPB4V2 AC20 IO164NDB4V1 FG896 Pin Number A3PE3000L Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-27 AC21 IO164PDB4V1 AC22 IO162PPB4V1 AC23 GND AC24 VCOMPLD AC25 IO150NDB3V4 AC26 IO148NDB3V4 AC27 GDA1/IO153PDB3V4 AC28 IO145NDB3V3 AC29 IO143NDB3V3 AC30 IO137NDB3V2 AD1 GND AD2 IO242NPB6V1 AD3 IO240NDB6V0 AD4 GEC0/IO236NDB6V0 AD5 VCCIB6 AD6 GNDQ AD6 GNDQ AD7 VCC AD8 VMV5 AD9 VCCIB5 AD10 IO224PPB5V3 AD11 IO218NPB5V3 AD12 IO216PPB5V2 AD13 IO210PPB5V2 AD14 IO202PPB5V1 AD15 IO194PDB5V0 AD16 IO190PDB4V4 AD17 IO182NPB4V3 AD18 IO176NDB4V2 AD19 IO176PDB4V2 AD20 IO170PPB4V2 AD21 IO166PDB4V1 AD22 VCCIB4 AD23 TCK AD24 VCC AD25 TRST FG896 Pin Number A3PE3000L Function AD26 VCCIB3 AD27 GDA0/IO153NDB3V4 AD28 GDC0/IO151NDB3V4 AD29 GDC1/IO151PDB3V4 AD30 GND AE1 IO242PPB6V1 AE2 VCC AE3 IO239PDB6V0 AE4 IO239NDB6V0 AE5 VMV6 AE5 VMV6 AE6 GND AE7 GNDQ AE8 IO230NDB5V4 AE9 IO224NPB5V3 AE10 IO214NPB5V2 AE11 IO212NDB5V2 AE12 IO212PDB5V2 AE13 IO202NPB5V1 AE14 IO200NDB5V0 AE15 IO196PDB5V0 AE16 IO190NDB4V4 AE17 IO184PDB4V3 AE18 IO184NDB4V3 AE19 IO172PDB4V2 AE20 IO172NDB4V2 AE21 IO166NDB4V1 AE22 IO160PDB4V0 AE23 GNDQ AE24 VMV4 AE25 GND AE26 GDB0/IO152NDB3V4 AE27 GDB1/IO152PDB3V4 AE28 VMV3 AE28 VMV3 AE29 VCC FG896 Pin Number A3PE3000L Function AE30 IO149PDB3V4 AF1 GND AF2 IO238PPB6V0 AF3 VCCIB6 AF4 IO220NPB5V3 AF5 VCC AF6 IO228NDB5V4 AF7 VCCIB5 AF8 IO230PDB5V4 AF9 IO229NDB5V4 AF10 IO229PDB5V4 AF11 IO214PPB5V2 AF12 IO208NDB5V1 AF13 IO208PDB5V1 AF14 IO200PDB5V0 AF15 IO196NDB5V0 AF16 IO186NDB4V4 AF17 IO186PDB4V4 AF18 IO180NDB4V3 AF19 IO180PDB4V3 AF20 IO168NDB4V1 AF21 IO168PDB4V1 AF22 IO160NDB4V0 AF23 IO158NPB4V0 AF24 VCCIB4 AF25 IO154NPB4V0 AF26 VCC AF27 TDO AF28 VCCIB3 AF29 GNDQ AF29 GNDQ AF30 GND AG1 IO238NPB6V0 AG2 VCC AG3 IO232NPB5V4 AG4 GND FG896 Pin Number A3PE3000L Function

Pin Number A3PE3000L Function AH10 IO225PPB5V3 AH11 IO223PPB5V3 AH12 IO211NDB5V2 AH13 IO211PDB5V2 AH14 IO205PPB5V1 AH15 IO195NDB5V0 AH16 IO185NDB4V3 AH17 IO185PDB4V3 AH18 IO181PDB4V3 AH19 IO177NDB4V2 AH20 IO171NPB4V2 AH21 IO165PPB4V1 AH22 IO161PPB4V0 AH23 IO157NDB4V0 AH24 IO157PDB4V0 AH25 IO155NDB4V0 AH26 VCCIB4 AH27 TDI AH28 VCC AH29 VPUMP AH30 GND AJ1 GND AJ2 GND AJ3 GEA2/IO233PPB5V4 AJ4 VCC AJ5 IO217NPB5V2 AJ6 VCC AJ7 IO215NPB5V2 AJ8 IO213NDB5V2 AJ9 IO213PDB5V2 AJ10 IO209NDB5V1 AJ11 IO209PDB5V1 AJ12 IO203NDB5V1 AJ13 IO203PDB5V1 AJ14 IO197NDB5V0 AJ15 IO195PDB5V0 FG896 Pin Number A3PE3000L Function AJ16 IO183NDB4V3 AJ17 IO183PDB4V3 AJ18 IO179NPB4V3 AJ19 IO177PDB4V2 AJ20 IO173NDB4V2 AJ21 IO173PDB4V2 AJ22 IO163NDB4V1 AJ23 IO163PDB4V1 AJ24 IO167NPB4V1 AJ25 VCC AJ26 IO156NPB4V0 AJ27 VCC AJ28 TMS AJ29 GND AJ30 GND AK2 GND AK3 GND AK4 IO217PPB5V2 AK5 GND AK6 IO215PPB5V2 AK7 GND AK8 IO207NDB5V1 AK9 IO207PDB5V1 AK10 IO201NDB5V0 AK11 IO201PDB5V0 AK12 IO193NDB4V4 AK13 IO193PDB4V4 AK14 IO197PDB5V0 AK15 IO191NDB4V4 AK16 IO191PDB4V4 AK17 IO189NDB4V4 AK18 IO189PDB4V4 AK19 IO179PPB4V3 AK20 IO175NDB4V2 AK21 IO175PDB4V2 AK22 IO169NDB4V1 FG896 Pin Number A3PE3000L Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-29 AK23 IO169PDB4V1 AK24 GND AK25 IO167PPB4V1 AK26 GND AK27 GDC2/IO156PPB4V0 AK28 GND AK29 GND B1 GND B2 GND B3 GAA2/IO309PPB7V4 B4 VCC B5 IO14PPB0V1 B6 VCC B7 IO07PPB0V0 B8 IO09PDB0V1 B9 IO15PPB0V1 B10 IO19NDB0V2 B11 IO19PDB0V2 B12 IO29NDB0V3 B13 IO29PDB0V3 B14 IO31PPB0V3 B15 IO37NDB0V4 B16 IO37PDB0V4 B17 IO41PDB1V0 B18 IO51NDB1V1 B19 IO59PDB1V2 B20 IO53PDB1V1 B21 IO53NDB1V1 B22 IO61NDB1V2 B23 IO61PDB1V2 B24 IO69NPB1V3 B25 VCC B26 GBC0/IO79NPB1V4 B27 VCC B28 IO64NPB1V2 B29 GND FG896 Pin Number A3PE3000L Function B30 GND C1 GND C2 IO309NPB7V4 C3 VCC C4 GAA0/IO00NPB0V0 C5 VCCIB0 C6 IO03PDB0V0 C7 IO03NDB0V0 C8 GAB1/IO01PDB0V0 C9 IO05PDB0V0 C10 IO15NPB0V1 C11 IO25NDB0V3 C12 IO25PDB0V3 C13 IO31NPB0V3 C14 IO27NDB0V3 C15 IO39NDB0V4 C16 IO39PDB0V4 C17 IO55PPB1V1 C18 IO51PDB1V1 C19 IO59NDB1V2 C20 IO63NDB1V2 C21 IO63PDB1V2 C22 IO67NDB1V3 C23 IO67PDB1V3 C24 IO75NDB1V4 C25 IO75PDB1V4 C26 VCCIB1 C27 IO64PPB1V2 C28 VCC C29 GBA1/IO81PPB1V4 C30 GND D1 IO303PPB7V3 D2 VCC D3 IO305NPB7V3 D4 GND D5 GAA1/IO00PPB0V0 FG896 Pin Number A3PE3000L Function D6 GAC1/IO02PDB0V0 D7 IO06NPB0V0 D8 GAB0/IO01NDB0V0 D9 IO05NDB0V0 D10 IO11NDB0V1 D11 IO11PDB0V1 D12 IO23NDB0V2 D13 IO23PDB0V2 D14 IO27PDB0V3 D15 IO40PDB0V4 D16 IO47NDB1V0 D17 IO47PDB1V0 D18 IO55NPB1V1 D19 IO65NDB1V3 D20 IO65PDB1V3 D21 IO71NDB1V3 D22 IO71PDB1V3 D23 IO73NDB1V4 D24 IO73PDB1V4 D25 IO74NDB1V4 D26 GBB0/IO80NPB1V4 D27 GND D28 GBA0/IO81NPB1V4 D29 VCC D30 GBA2/IO82PPB2V0 E1 GND E2 IO303NPB7V3 E3 VCCIB7 E4 IO305PPB7V3 E5 VCC E6 GAC0/IO02NDB0V0 E7 VCCIB0 E8 IO06PPB0V0 E9 IO24NDB0V2 E10 IO24PDB0V2 E11 IO13NDB0V1 FG896 Pin Number A3PE3000L Function

Pin Number A3PE3000L Function F17 IO48PDB1V0 F18 IO50NDB1V1 F19 IO58NDB1V2 F20 IO60PDB1V2 F21 IO77NDB1V4 F22 IO72NDB1V3 F23 IO72PDB1V3 F24 GNDQ F25 GND F26 VMV2 F26 VMV2 F27 IO86PDB2V0 F28 IO92PDB2V1 F29 VCC F30 IO100NPB2V2 G1 GND G2 IO296NPB7V2 G3 IO306NDB7V4 G4 IO297NDB7V2 G5 VCCIB7 G6 GNDQ G6 GNDQ G7 VCC G8 VMV0 G9 VCCIB0 G10 IO10NDB0V1 G11 IO16NDB0V1 G12 IO22PDB0V2 G13 IO26PPB0V3 G14 IO38NPB0V4 G15 IO36NDB0V4 G16 IO46NDB1V0 G17 IO46PDB1V0 G18 IO56NDB1V1 G19 IO56PDB1V1 G20 IO66NDB1V3 FG896 Pin Number A3PE3000L Function G21 IO66PDB1V3 G22 VCCIB1 G23 VMV1 G24 VCC G25 GNDQ G25 GNDQ G26 VCCIB2 G27 IO86NDB2V0 G28 IO92NDB2V1 G29 IO100PPB2V2 G30 GND H1 IO294PDB7V2 H2 IO294NDB7V2 H3 IO300NDB7V3 H4 IO300PDB7V3 H5 IO295PDB7V2 H6 IO299PDB7V3 H7 VCOMPLA H8 GND H9 IO08NDB0V0 H10 IO08PDB0V0 H11 IO18PDB0V2 H12 IO26NPB0V3 H13 IO28NDB0V3 H14 IO28PDB0V3 H15 IO38PPB0V4 H16 IO42NDB1V0 H17 IO52NDB1V1 H18 IO52PDB1V1 H19 IO62NDB1V2 H20 IO62PDB1V2 H21 IO70NDB1V3 H22 IO70PDB1V3 H23 GND H24 VCOMPLB H25 GBC2/IO84PDB2V0 FG896 Pin Number A3PE3000L Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-31 H26 IO84NDB2V0 H27 IO96PDB2V1 H28 IO96NDB2V1 H29 IO89PDB2V0 H30 IO89NDB2V0 J1 IO290NDB7V2 J2 IO290PDB7V2 J3 IO302NDB7V3 J4 IO302PDB7V3 J5 IO295NDB7V2 J6 IO299NDB7V3 J7 VCCIB7 J8 VCCPLA J9 VCC J10 IO04NPB0V0 J11 IO18NDB0V2 J12 IO20NDB0V2 J13 IO20PDB0V2 J14 IO32NDB0V3 J15 IO32PDB0V3 J16 IO42PDB1V0 J17 IO44NDB1V0 J18 IO44PDB1V0 J19 IO54NDB1V1 J20 IO54PDB1V1 J21 IO76NPB1V4 J22 VCC J23 VCCPLB J24 VCCIB2 J25 IO90PDB2V1 J26 IO90NDB2V1 J27 GBB2/IO83PDB2V0 J28 IO83NDB2V0 J29 IO91PDB2V1 J30 IO91NDB2V1 K1 IO288NDB7V1 FG896 Pin Number A3PE3000L Function K2 IO288PDB7V1 K3 IO304NDB7V3 K4 IO304PDB7V3 K5 GAB2/IO308PDB7V4 K6 IO308NDB7V4 K7 IO301PDB7V3 K8 IO301NDB7V3 K9 GAC2/IO307PPB7V4 K10 VCC K11 IO04PPB0V0 K12 VCCIB0 K13 VCCIB0 K14 VCCIB0 K15 V CCIB0 K16 VCCIB1 K17 VCCIB1 K18 VCCIB1 K19 VCCIB1 K20 IO76PPB1V4 K21 VCC K22 IO78PPB1V4 K23 IO88NDB2V0 K24 IO88PDB2V0 K25 IO94PDB2V1 K26 IO94NDB2V1 K27 IO85PDB2V0 K28 IO85NDB2V0 K29 IO93PDB2V1 K30 IO93NDB2V1 L1 IO286NDB7V1 L2 IO286PDB7V1 L3 IO298NDB7V3 L4 IO298PDB7V3 L5 IO283PDB7V1 L6 IO291NDB7V2 L7 IO291PDB7V2 FG896 Pin Number A3PE3000L Function L8 IO293PDB7V2 L9 IO293NDB7V2 L10 IO307NPB7V4 L11 VCC L12 VCC L13 VCC L14 VCC L15 VCC L16 VCC L17 VCC L18 VCC L19 VCC L20 VCC L21 IO78NPB1V4 L22 IO104NPB2V2 L23 IO98NDB2V2 L24 IO98PDB2V2 L25 IO87PDB2V0 L26 IO87NDB2V0 L27 IO97PDB2V1 L28 IO101PDB2V2 L29 IO103PDB2V2 L30 IO119NDB3V0 M1 IO282NDB7V1 M2 IO282PDB7V1 M3 IO292NDB7V2 M4 IO292PDB7V2 M5 IO283NDB7V1 M6 IO285PDB7V1 M7 IO287PDB7V1 M8 IO289PDB7V1 M9 IO289NDB7V1 M10 VCCIB7 M11 VCC M12 GND M13 GND FG896 Pin Number A3PE3000L Function

Pin Number A3PE3000L Function N20 VCC N21 VCCIB2 N22 IO106NDB2V3 N23 IO106PDB2V3 N24 IO108PDB2V3 N25 IO108NDB2V3 N26 IO95NDB2V1 N27 IO99NDB2V2 N28 IO99PDB2V2 N29 IO107PDB2V3 N30 IO107NDB2V3 P1 IO276NDB7V0 P2 IO278NDB7V0 P3 IO280NDB7V0 P4 IO284NDB7V1 P5 IO279NDB7V0 P6 GFC1/IO275PDB7V0 P7 GFC0/IO275NDB7V0 P8 IO277PDB7V0 P9 IO277NDB7V0 P10 VCCIB7 P11 VCC P12 GND P13 GND P14 GND P15 GND P16 GND P17 GND P18 GND P19 GND P20 VCC P21 VCCIB2 P22 GCC1/IO112PDB2V3 P23 IO110PDB2V3 P24 IO110NDB2V3 P25 IO109PPB2V3 FG896 Pin Number A3PE3000L Function P26 IO111NPB2V3 P27 IO105PDB2V2 P28 IO105NDB2V2 P29 GCC2/IO117PDB3V0 P30 IO117NDB3V0 R1 GFC2/IO270PDB6V4 R2 GFB1/IO274PPB7V0 R3 VCOMPLF R4 GFA0/IO273NDB6V4 R5 GFB0/IO274NPB7V0 R6 IO271NDB6V4 R7 GFB2/IO271PDB6V4 R8 IO269PDB6V4 R9 IO269NDB6V4 R10 VCCIB7 R11 VCC R12 GND R13 GND R14 GND R15 GND R16 GND R17 GND R18 GND R19 GND R20 VCC R21 VCCIB2 R22 GCC0/IO112NDB2V3 R23 GCB2/IO116PDB3V0 R24 IO118PDB3V0 R25 IO111PPB2V3 R26 IO122PPB3V1 R27 GCA0/IO114NPB3V0 R28 VCOMPLC R29 GCB1/IO113PPB2V3 R30 IO115NPB3V0 T1 IO270NDB6V4 FG896 Pin Number A3PE3000L Function

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 4-33 T2 VCCPLF T3 GFA2/IO272PPB6V4 T4 GFA1/IO273PDB6V4 T5 IO272NPB6V4 T6 IO267NDB6V4 T7 IO267PDB6V4 T8 IO265PDB6V3 T9 IO263PDB6V3 T10 VCCIB6 T11 VCC T12 GND T13 GND T14 GND T15 GND T16 GND T17 GND T18 GND T19 GND T20 VCC T21 VCCIB3 T22 IO109NPB2V3 T23 IO116NDB3V0 T24 IO118NDB3V0 T25 IO122NPB3V1 T26 GCA1/IO114PPB3V0 T27 GCB0/IO113NPB2V3 T28 GCA2/IO115PPB3V0 T29 VCCPLC T30 IO121PDB3V0 U1 IO268PDB6V4 U2 IO264NDB6V3 U3 IO264PDB6V3 U4 IO258PDB6V3 U5 IO258NDB6V3 U6 IO257PPB6V2 U7 IO261PPB6V3 FG896 Pin Number A3PE3000L Function U8 IO265NDB6V3 U9 IO263NDB6V3 U10 VCCIB6 U11 VCC U12 GND U13 GND U14 GND U15 GND U16 GND U17 GND U18 GND U19 GND U20 VCC U21 VCCIB3 U22 IO120PDB3V0 U23 IO128PDB3V1 U24 IO124PDB3V1 U25 IO124NDB3V1 U26 IO126PDB3V1 U27 IO129PDB3V1 U28 IO127PDB3V1 U29 IO125PDB3V1 U30 IO121NDB3V0 V1 IO268NDB6V4 V2 IO262PDB6V3 V3 IO260PDB6V3 V4 IO252PDB6V2 V5 IO257NPB6V2 V6 IO261NPB6V3 V7 IO255PDB6V2 V8 IO259PDB6V3 V9 IO259NDB6V3 V10 VCCIB6 V11 VCC V12 GND V13 GND FG896 Pin Number A3PE3000L Function V14 GND V15 GND V16 GND V17 GND V18 GND V19 GND V20 VCC V21 VCCIB3 V22 IO120NDB3V0 V23 IO128NDB3V1 V24 IO132PDB3V2 V25 IO130PPB3V2 V26 IO126NDB3V1 V27 IO129NDB3V1 V28 IO127NDB3V1 V29 IO125NDB3V1 V30 IO123PDB3V1 W1 IO266NDB6V4 W2 IO262NDB6V3 W3 IO260NDB6V3 W4 IO252NDB6V2 W5 IO251NDB6V2 W6 IO251PDB6V2 W7 IO255NDB6V2 W8 IO249PPB6V1 W9 IO253PDB6V2 W10 VCCIB6 W11 VCC W12 GND W13 GND W14 GND W15 GND W16 GND W17 GND W18 GND W19 GND FG896 Pin Number A3PE3000L Function

Pin Number A3PE3000L Function Y26 IO136PPB3V2 Y27 IO141NDB3V3 Y28 IO135NDB3V2 Y29 IO131NDB3V2 Y30 IO133PDB3V2 FG896 Pin Number A3PE3000L Function

5 – Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the datasheet. Revision Changes Page Revision 3 (September 2012) The "Security" section was modified to clarify that Microsemi does not support read-back of programmed data. 1-2 Revision 2 (June 2012) The FG484 package was added for A3P1000 in Table 1 • Military ProASIC3/EL Low- Power Devices, the I/Os Per Package 1 table , and the "Temperature Grade Offerings" table (SAR 39010). I, II, IV The "FG484" pin table for A3P1000 has been added (SAR 39010). 4-15 Revision 1 (June 2011) In the "High Performance" section, 66-Bit PCI was corrected to 64-Bit PCI (SAR 31977). I The A3P250 device and VQ100 package were added to product tables in the "Military ProASIC3/EL Low Power Flash FPGAs" chapter (SAR 30526). I The Y security option and Licensed DPA Logo were added to the "Military ProASIC3/EL Ordering Information" section . The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 32151). III The A3P250 device was added to applicable tables in the "Military ProASIC3/EL DC and Switching Characteristics" chapter (SAR 30526). 2-1 The VPUMP voltage for operation mode was changed from "0 to 3.45 V" to "0 to 3.6 V" in Table 2-2 • Recommended Operating Conditions 1(SAR 25220). 2-2 3.3 V LVCMOS wide range and 1.2 V LVCMOS wide range were added to applicable tables in the following sections (SAR 28061): Table 2-2 • Recommended Operating Conditions 1 "Power per I/O Pin" "Overview of I/O Performance" "Summary of I/O Timing Characteristics – Default I/O Software Settings" "User I/O Characteristics" "Detailed I/O DC Characteristics" "Single-Ended I/O Characteristics" (SAR 31925) 2-2 2-11 2-24 2-27 2-20 2-31 2-39 The "Quiescent Supply Current " section was updated. Table 2-7 • Power Supply State Per Mode is new (SAR 24882, 24112, 32549). New values were added to the following tables (SAR 30619): Table 2-8 • Quiescent Supply Current (IDD) Characteristics, Flash*Freeze Mode* Table 2-10 • Quiescent Supply Current (IDD) Characteristics, Shutdown Mode* Table 2-11 • Quiescent Supply Current (IDD), Static Mode and Active Mode 1 (the name of this table changed from "No Flash*Freeze Mode" to "Static Mode and Active Mode" per SAR 32549) Table 2-12 • Quiescent Supply Current (IDD) Characteristics for A3P250 and A3P1000 The military maximum current for A3P1000 was revised in the following table (SAR 30620): Table 2-12 • Quiescent Supply Current (IDD) Characteristics for A3P250 and A3P1000 2-9

All timing and power tables were updated to reflect changes in the software resulting from characterization and bug fixes (SAR 32394). 2-11 to 2-14 Revision 1 (continued) In the following tables for A3P250 and A3P1000, the note regarding dynamic power was revised to, "Dynamic Power consumption is gi ven for software default drive strength and output slew. Output load is lower than the software default" (SAR 32449). Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1 Table 2-18 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 2-14, 2-14 Values for A3PE600L and A3P250 were added to Table 2-20 • Different Components Contributing to Dynamic Power Consumption in Military ProASIC3 and ProASIC3/EL Devices at 1.5 V VCC . Values in the table, and in Table 2-19 • Different Components Contributing to Dynamic Power Consumption in Military ProASIC3/EL Devices Operating at 1.2 V VCC , were updated were updated to reflect changes in the software resulting from characterization and bug fixes (SAR 30528). 2-15, 2-16 Table 2-21 • Different Components Contribut ing to the Static Power Consumption in Military ProASIC3/EL Devices and the "Total Static Power Consumption—PSTAT" calculation were updated to add PDC0 (SAR 32549). 2-16, 2-17 The "Timing Model" was updated (SAR 29793). 2-20 The title of Table 2-28 • Summary of AC Measuring Points was changed from "Summary of AC Memory Points" (SAR 32446). 2-27 The following note was added to Table 2-30, Table 2-31, and Table 2-31, Summary of I/O Timing Characteristics (SAR 32449): "Output delays provided in this table were ex tracted with an output load indicated in the Capacitive Load column. For a specific output load, refer to Designer software." 2-28 Resistances and short circuit currents were updated (SARs 29793, 31717): Table 2-35 • I/O Output Buffer Maximum Re sistances 1 Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Table 2-39 • I/O Short Currents IOSH/IOSL Ap plicable to Pro I/Os for A3PE600L and A3PE3000L Only (SAR 31717) Tables for Pro I/Os in the "Single-Ended I/O Characteristics" section (SAR 31717). 2-32 throu gh 2-35 The drive strength was changed from 25 mA to 20 mA for 3.3 V and 2.5 V GTL (SAR 31978). This affects the following tables: Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Table 2-30 • Summary of I/O Timing Char acteristics—Softwar e Default Settings (SAR 32394) Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings Table 2-35 • I/O Output Buffer Maximum Re sistances 1 Applicable to Pro I/Os for A3PE600L and A3PE3000L Only Table 2-39 • I/O Short Currents IOSH/IOSL Ap plicable to Pro I/Os for A3PE600L and A3PE3000L Only Table 2-119 • Minimum and Maximum DC Input and Output Levels Table 2-123 • Minimum and Maximum DC Input and Output Levels 2-24 2-28 2-29 2-32 2-35 2-75 2-77 The values in Table 2-38 • I/O Weak Pull-Up/Pull-Down Resistances were revised (SAR 29793, 28061). 2-34 Revision Changes Page

In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "Military ProASIC3/EL Device Status" table on page II, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a data sheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, bu t not for production. This label only applies to the DC and Switching Characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subj ect to the Export Administ ration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.actel.com/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information.

Military ProASIC3/EL Low Power Flash FPGAs Revision 3 5-5

51700106-3/9.12 © 2011 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi Corporation (NASDAQ: MSCC) offers the industry’s most comprehensive portfolio of semiconductor technology. Committed to solving the most critical system challenges, Microsemi’s products include high-performance, high-reliability analog and RF devices, mixed signal integrated circuits, FPGAs and customizable SoCs, and co mplete subsystems. Microsemi serves leading system manufacturers around the world in th e defense, security, aerospace, enterprise, commercial, and industrial markets. Learn more at www.microsemi.com. Microsemmi Corporate Headquarters

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