Memory

A3P1000-FG256

Microsemi Corporation

ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Manufacturer: Microsemi Corporation

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Technical content

15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI † In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†
FlashLock ® to Secure FPGA Contents Low Power
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / † and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate † and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family Clock Conditioning Circuit (CCC) and PLL†
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz) Embedded Memory†
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
True Dual-Port SRAM (except ×18) ARM Processor Support in ProASIC3 FPGAs
M1 ProASIC3 Devices—ARM ®Cortex™-M1 Soft Processor Available with or without Debug † A3P015 and A3P030 devices do not support this f eature. ‡ Supported only by A3P015 and A3P030 devices. ProASIC3 Devices A3P015 1 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Cortex-M1 Devices 2 M1A3P250 M1A3P400 M1A3P600 M1A3P1000 System Gates 15,000 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000 Typical Equivalent Macrocells 128 256 512 1,024 2,048 – – – VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576 RAM Kbits (1,024 bits) – – 18 36 36 54 108 144 4,608-Bit Blocks ––4 8 81 2 2 43 2 FlashROM Kbits 111 1 1 1 1 1 Secure (AES) ISP 3 – – Yes Yes Yes Yes Yes Yes Integrated PLL in CCCs ––1 1 1 1 1 1 VersaNet Globals 4 6 6 18 18 18 18 18 18 I/O Banks 222 2 4 4 4 4 Maximum User I/Os 49 81 96 133 157 194 235 300 Package Pins QFN CS VQFP TQFP PQFP FBGA QN68 QN48, QN68, QN132 VQ100 QN132 CS121 VQ100 TQ144 FG144 QN132 VQ100 TQ144 PQ208 FG144 QN132 VQ100 PQ208 FG144/256 5 PQ208 FG144/256/ 484 PQ208 FG144/256/ 484 PQ208 FG144/256/ 484 Notes: 1. A3P015 is not recommended for new designs. 2. Refer to the Cortex-M1 product brief for more information. 3. AES is not available for Cortex-M1 ProASIC3 devices. 4. Six chip (main) and three quadrant global networks are available for A3P060 and above. 5. The M1A3P250 device does not support this package. 6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet. Revision 13

ProASIC3 Flash Family FPGAs I/Os Per Package 1 ProASIC3 Devices A3P015 2 A3P030 A3P060 A3P125 A3P250 3 A3P400 3 A3P600 A3P1000 Cortex-M1 Devices M1A3P250 3,5 M1A3P400 3 M1A3P600 M1A3P1000 Package I/O Type Single-Ended I/O Single-Ended I/O Single-Ended I/O Single-Ended I/O Single-Ended I/O Differential I/O Pairs Single-Ended I/O4 Differential I/O Pairs Single-Ended I/O4 Differential I/O Pairs Single-Ended I/O Differential I/O Pairs QN132 5 – 8 18 08 4 8 7 1 9 – – – – – VQ100 – 77 71 71 68 13 – – – – – PQ208 – – – 133 151 34 151 34 154 35 154 35 F G 1 4 4 – – 9 6 9 7 9 7 2 4 9 72 59 72 59 72 5 FG256 5,6 – – – – 157 38 178 38 177 43 177 44 FG4846 – – – – – – 194 38 235 60 300 74 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide to ensure complying with design and board migration requirements. 2. A3P015 is not recommended for new designs. 3. For A3P250 and A3P400 devices, the maximum number of LVPE CL pairs in east and west banks cannot exceed 15. Refer to the ProASIC3 FPGA Fabric User’s Guide for position assignments of the 15 LVPECL pairs. 4. Each used differential I/O pair reduces t he number of single-ended I/Os available by two. 5. The M1A3P250 device does not support FG256 or QN132 packages. 6. FG256 and FG484 are footprint-compatible packages. Table 1 • ProASIC3 FPGAs Package Sizes Dimensions Length × Width (mm\\mm) 6 × 6 6 × 6 8 × 8 8 × 8 14 × 14 20 × 20 28 × 28 13 × 13 17 × 17 23 × 23 Nominal Area (mm2) 36 36 64 64 196 400 784 169 289 529

ProASIC3 Flash Family FPGAs Revision 13 III ProASIC3 Ordering Information ProASIC3 Device Status ProASIC3 Devices Status Cortex-M1 Devices Status A3P015 Not recommended for new designs. A3P030 Production A3P060 Production A3P125 Production A3P250 Production M1A3P250 Production A3P400 Production M1A3P400 Production A3P600 Production M1A3P600 Production A3P1000 Production M1A3P1000 Production Speed Grade Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard A3P1000 FG_ Part Number ProASIC3 Devices Package Type VQ = Very Thin Quad Flat Pack (0.5 mm pitch) QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) TQ = Thin Quad Flat Pack (0.5 mm pitch) 144 I Y Package Lead Count G Lead-Free Packaging Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature) I = Industrial ( –40°C to +85°C Ambient Temperature) Blank = Standard Packaging G= RoHS-Compliant (Green) Packaging (some packages also halogen-free) PP= Pre-Production ES= Engineering Sample (Room Temperature Only) 30,000 System GatesA3P030 = 15,000 System Gates (A3P015 is not recommended for new designs.)A3P015 = 60,000 System GatesA3P060 = 125,000 System GatesA3P125 = 250,000 System GatesA3P250 = 400,000 System GatesA3P400 = 600,000 System GatesA3P600 = 1,000,000 System GatesA3P1000 = ProASIC3 Devices with Cortex-M1 250,000 System GatesM1A3P250 = 400,000 System GatesM1A3P400 = 600,000 System GatesM1A3P600 = 1,000,000 System GatesM1A3P1000 = PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) CS = Chip Scale Package (0.5 mm pitch) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio

ProASIC3 Flash Family FPGAs Temperature Grade Offerings Speed Grade and Temperature Grade Matrix References made to ProASIC3 devices also apply to ARM-enable d ProASIC3 devices. The ARM-ena bled part numbers start with M1 (Cortex-M1). Contact your local Microsemi representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. A3P015 and A3P030 The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features. Devices Not Recommended For New Designs A3P015 is not recommended for new designs. Package A3P015 * A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Cortex-M1 Devices M1A3P250 M1A3P400 M1A3P600 M1A3P1000 QN132 – C, I C, I C, I C, I – – – V Q 1 0 0 – C , IC , IC , I C , I – – – PQ208 – – – C, I C, I C, I C, I C, I FG144 – – C, I C, I C, I C, I C, I C, I FG256 – – – – C, I C, I C, I C, I FG484 – – – – – C, I C, I C, I Note: *A3P015 is not recommended for new designs. C = Commercial temperature range: 0°C to 70°C ambient temperature I = Industrial temperature range: –40°C to 85°C ambient temperature Temperature Grade Std. –1 –2 C 1  I 2  Notes: 1. C = Commercial temperature range: 0°C to 70°C ambient temperature 2. I = Industrial temperature range: –40°C to 85°C ambient temperature

ProASIC3 Flash Family FPGAs Revision 13 V Table of Contents ProASIC3 Device Family Overview ProASIC3 DC and Switching Characteristics Pin Descriptions Package Pin Assignments Datasheet Information

1 – ProASIC3 Device Family Overview General Description ProASIC3, the third-generation fami ly of Microsemi flash FPGAs, of fers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 is reprogrammable and offers time-to -market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, reprogr ammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ProASIC3 devices support the ARM Cortex-M1 proc essor. The ARM-enabled devices have Microsemi ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM- based FPGAs, flash-based ProASIC3 devices allow all functionality to be Instant On; no external boot PROM is required. On-boa rd security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in the cons umer, networking/ communic ations, computing, and avionics markets. Security The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for intellect ual property and configuration data. In addition, all FlashROM data in ProASIC3 devic es can be encrypted prior to loadi ng, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES decrypti on engine and a flash-based AE S key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the ARM core must be protected at al l times, AES encryption is always on for the core logic, so bitstreams are always encrypted. There is no user access to encryption for the FlashROM programming data. Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are located beneath seven metal layers, and many devi ce design and layout techniques have been used to make invasive attacks extremely di fficult. The ProASIC3 family, wi th FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks.

ProASIC3 Device Family Overview Your valuable IP is protected with industry-stand ard security, making remote ISP possible. A ProASIC3 device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration informati on in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power- up (unlike SRAM-based FPGAs). Theref ore, flash-based ProASIC3 FPGAs do not require system configurati on components such as EEPROMs or mi crocontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Instant On Flash-based ProASIC3 devices support Level 0 of the Instant On classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock genera tion, and bus activity management. The Instant On feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGA s, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash- based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuratio n memory of ProASIC3 flash-based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore im mune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Low Power Flash-based ProASIC3 devices exhibit power characteri stics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASI C3 devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. ProASIC3 devices also have low dynamic power consumption to further maximize power savings.

ProASIC3 Flash Family FPGAs Revision 13 1-5 User Nonvolatile FlashROM ProASIC3 devices have 1 kbit of on-chip, user-a ccessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications:

Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management The FlashROM is written using th e standard ProASIC3 IEEE 1532 JT AG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG progr amming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits ; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address fr om the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The ProASIC3 development software solutions, Libero ® System-on-Chip (SoC) and Designer, have extensive support for the FlashROM. One such feat ure is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero SoC and Designer software tools. Comprehe nsive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a sing le bitstream. The embedded SRAM blocks can be initialized via the device JTAG por t (ROM emulation mode) using the UJTAG macro (except in A3P015 and A3P030 devices). In addition, every SRAM block has an embedded FI FO control unit. The contro l unit allows the SRAM block to be configured as a synchronous FIFO with out using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also feat ures programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the norma l Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generati on of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and A3P030 devices do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allo w simple clock delay operations as well as clock spine access.

ProASIC3 Device Family Overview The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features:

Wide input frequency range (f IN_CCC) = 1.5 MHz to 350 MHz
Output frequency range (f OUT_CCC) = 0.75 MHz to 350 MHz
Clock delay adjustment via programmable a nd fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only) Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock per iod peak-to-peak period jitter when single global network used (for PLL only)
Maximum acquisition time = 300 µs (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter— allowa ble input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz / f OUT_CCC) (for PLL only) Global Clocking ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets.

ProASIC3 Flash Family FPGAs Revision 13 1-7 I/Os with Advanced I/O Standards The ProASIC3 family of FPGAs feat ures a flexible I/O structure, su pporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported (Table 1-1). Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following:

Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a devi ce to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components wit h greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configurat ion. A FlashPoint – Pr ogramming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. Table 1-1 • I/O Standards Supported I/O Bank Type Device and Bank Location I/O Standards Supported LVTTL/ LVCMOS PCI/PCI-X LVPECL, LVDS, B-LVDS, M-LVDS Advanced East and west Banks of A3P250 and larger devices   Standard Plus North and south banks of A3P250 and larger devices All banks of A3P060 and A3P125  Not supported Standard All banks of A3P015 and A3P030  Not supported Not supported

ProASIC3 Device Family Overview 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-4 on page 1-8). 5. Set the I/O Output State. You can set Basic I/O se ttings if you want to use the default I/O settings for your pins, or use Custom I/O settings to cust omize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tristate: I/O is tristated 6. Click OK to return to the FlashPoi nt – Programming File Generator window. Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. Figure 1-4 • I/O States During Programming Window

2 – ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of th e device at these or any other conditions beyond those listed under the Recommended O perating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V VMV DC I/O input buffer supply voltage –0.3 to 3.75 V VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) V T STG

2 Storage temperature –65 to +150 °C

2 Junction temperature +125 °C

Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2.

ProASIC3 DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions 1,2 Symbol Parameters 1 Commercial Industrial Units TA Ambient temperature 0 to +70 -40 to +85 °C TJ Junction temperature 0 to 85 -40 to 100 °C VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V VPUMP Programming voltage Programming Mode 4 3.15 to 3.45 3.15 to 3.45 V Operation 5 0 to 3.6 0 to 3.6 V VCCPLL Analog power supply (PLL ) 1.425 to 1.575 1.425 to 1.575 V

3.3 V wide range DC supply voltage

7 2.7 to 3.6 2.7 to 3.6 V LVDS/B-LVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi recommends that the user follow best design practices using Microsemi’s timing and power simulation tools. 3. The ranges given here are for power supplies only. Th e recommended input voltage ranges specific to each I/O standard are given in Table 2-18 on page 2-18. 4. The programming temperat ure range supported is Tambient = 0°C to 85°C. 5. VPUMP can be left floating during operation (not programming mode). 6. VMV and VCCI should be at the same voltage within a given I/O bank. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 7. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation. Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1 Product Grade Programming Cycles Program Retention (biased/unbiased) Maximum Storage Temperature TSTG (°C) 2 Maximum Operating Junction Temperature TJ (°C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits.

ProASIC3 Flash Family FPGAs Revision 13 2-3 I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circui try is designed into every ProASIC ®3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points ( Figure 2-1 on page 2-4). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplie s or voltage regulators to ensure proper power- up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for information on clock and lock recovery. Table 2-4 • Overshoot and Undershoot Limits 1 VCCI and VMV Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 2.7 V or less 10% 1.4 V 5% 1.49 V 3 V 10% 1.1 V 5% 1.19 V 3.3 V 10% 0.79 V 5% 0.88 V 3.6 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one out of si x clock cycles. If the overshoot/unders hoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits.

ProASIC3 DC and Switching Characteristics Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation Thermal Characteristics Introduction The temperature variable in the Microsemi Designer software refers to the junction temperature, not the ambient temperature. This is an important distin ction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels Region 1: I/O buffers are OFF Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCC VCC = 1.425 V Region 1: I/O Buffers are OFF Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc. Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCCI Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. VCC = VCCI + VT

ProASIC3 Flash Family FPGAs Revision 13 2-5 Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. EQ 2 Maximum Power Allowed Max. junction temp. (C) Max. ambient temp. ( C)– Table 2-5 • Package Thermal Resistivities Package Type Device Pin Count jc ja UnitsStill Air 200 ft./min. 500 ft./min. Quad Flat No Lead A3P 030 132 0.4 21.4 16.8 15.3 C/W A3P060 132 0.3 21.2 16.6 15.0 C/W A3P125 132 0.2 21.1 16.5 14.9 C/W A3P250 132 0.1 21.0 16.4 14.8 C/W Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 C/W Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W Fine Pitch Ball Grid Array (FBGA) See note* 144 3.8 26.9 22.9 21.5 C/W See note* 256 3.8 26.6 22.8 21.5 C/W See note* 484 3.2 20.5 17.0 15.9 C/W A3P1000 144 6.3 31.6 26.2 24.2 C/W A3P1000 256 6.6 28.1 24.4 22.7 C/W A3P1000 484 8.0 23.3 19.0 16.7 C/W Note: *This information applies to all ProASIC3 devices e xcept the A3P1000. Detailed device/package thermal information will be available in future revisions of the datasheet.

ProASIC3 DC and Switching Characteristics Temperature and Voltage Derating Factors Calculating Power Dissipation Quiescent Supply Current Power per I/O Pin Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) Array Voltage VCC (V) Junction Temperature (°C) –40°C 0°C 25°C 70°C 85°C 100°C Table 2-7 • Quiescent Supply Current Characteristics A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Typical (25°C) 2 mA 2 mA 2 mA 2 mA 3 mA 3 mA 5 mA 8 mA Max. (Commercial) 10 mA 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 50 mA Max. (Industrial) 15 mA 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA 75 mA Note: IDD Includes VCC, VPUMP, VCCI, and VMV curr ents. Values do not include I/O static contribution, which is shown in Table 2-11 and Table 2-12 on page 2-8. Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Advanced I/O Banks VMV (V) Static Power P DC2 (mW) 1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.22

3.3 V LVCMOS Wide Range

3 3.3 – 16.22 2.5 V LVCMOS 2.5 – 5.12 1.8 V LVCMOS 1.8 – 2.13 1.5 V LVCMOS (JESD8-11) 1.5 – 1.45 3.3 V PCI 3.3 – 18.11 3.3 V PCI-X 3.3 – 18.11 Differential LVDS 2.5 2.26 1.20 LVPECL 3.3 5.72 1.87 Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCM OS 3.3 V wide range as specified in the JESD8-B specification.

ProASIC3 Flash Family FPGAs Revision 13 2-7 Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.23 3.3 V LVCMOS Wide Range3 3.3 – 16.23 2.5 V LVCMOS 2.5 – 5.14 1.8 V LVCMOS 1.8 – 2.13 1.5 V LVCMOS (JESD8-11) 1.5 – 1.48 3.3 V PCI 3.3 – 18.13 3.3 V PCI-X 3.3 – 18.13 Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCM OS 3.3 V wide range as specified in the JESD8-B specification. Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (µW/MHz)2 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.24 3 3.3 – 17.24 2.5 V LVCMOS 2.5 – 5.19 1.8 V LVCMOS 1.8 – 2.18 1.5 V LVCMOS (JESD8-11) 1.5 – 1.52 Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

ProASIC3 DC and Switching Characteristics Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Advanced I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 468.67 3.3 V LVCMOS Wide Range4 35 3.3 – 468.67 2.5 V LVCMOS 35 2.5 – 267.48 1.8 V LVCMOS 35 1.8 – 149.46

1.5 V LVCMOS

(JESD8-11) 35 1.5 – 103.12 3.3 V PCI 10 3.3 – 201.02 3.3 V PCI-X 10 3.3 – 201.02 Differential LVDS – 2.5 7.74 88.92 LVPECL – 3.3 19.54 166.52 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings1 Applicable to Standard Plus I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 452.67 3.3 V LVCMOS Wide Range4 35 3.3 – 452.67 2.5 V LVCMOS 35 2.5 – 258.32 1.8 V LVCMOS 35 1.8 – 133.59 1.5 V LVCMOS (JESD8-11) 35 1.5 – 92.84 3.3 V PCI 10 3.3 – 184.92 3.3 V PCI-X 10 3.3 – 184.92 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. P DC3 is the static power (where applicable) measured on VMV. 3. P AC10 is the total dynamic power measured on VCC and VMV. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

ProASIC3 Flash Family FPGAs Revision 13 2-9 Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings 1 Applicable to Standard I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW) 2 Dynamic Power PAC10 (µW/MHz) 3 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 431.08 3.3 V LVCMOS Wide Range4 35 3.3 – 431.08 2.5 V LVCMOS 35 2.5 – 247.36 1.8 V LVCMOS 35 1.8 – 128.46 1.5 V LVCMOS (JESD8-11) 35 1.5 – 89.46 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. P DC3 is the static power (where applicable) measured on VCCI. 3. P AC10 is the total dynamic power measured on VCC and VCCI. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

ProASIC3 DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices Parameter Definition Device Specific Dynamic Contributions (µW/MHz) A3P1000 A3P600 A3P400 A3P250 A3P125 A3P060 A3P030 A3P015 PAC3 Clock contribution of a VersaTile row 0.81 PAC4 Clock contribution of a VersaTile used as a sequential module 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard dependent) See Table 2-8 on page 2-6 through Table 2-10 on page 2-7. PAC10 Contribution of an I/O output pin (standard dependent) See Table 2-11 on page 2-8 through Table 2-13 on page 2-9. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.60 Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet calculator or SmartPower tool in Libero SoC software.

ProASIC3 Flash Family FPGAs Revision 13 2-11 Power Calculation Methodology This section describes a simplified method to estima te power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC software. The power calculation methodology described below uses the following variables:

The number of PLLs as well as the number a nd the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on page 2-13.
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on page 2-13.
Read rate and write rate to the memory—guidel ines are provided for typical applications in Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—P TOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—P STAT PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices Parameter Definition Device Specific Static Power (mW) A3P1000 A3P600 A3P400 A3P250 A3P125 A3P060 A3P030 A3P015 PDC1 Array static power in Active mode See Table 2-7 on page 2-6. PDC2 I/O input pin static power (standard-dependent) See Table 2-8 on page 2-6 through Table 2-10 on page 2-7. PDC3 I/O output pin static power (standard-dependent) See Table 2-11 on page 2-8 through Table 2-13 on page 2-9. PDC4 Static PLL contribution 2.55 mW PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-6. Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet calculator or SmartPower tool in Libero SoC software.

ProASIC3 DC and Switching Characteristics Total Dynamic Power Consumption—P DYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—P CLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in t he "Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide. NROW is the number of VersaTile rows used in the design—guidelines are provided in t he "Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—P S-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequent ial modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. Combinatorial Cells Contribution—P C-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. Routing Net Contribution—P NET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—P INPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13. FCLK is the global clock signal frequency. I/O Output Buffer Contribution—P OUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13. 1 is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-13. FCLK is the global clock signal frequency.

ProASIC3 Flash Family FPGAs Revision 13 2-13 RAM Contribution—P MEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on page 2-13. PLL Contribution—P PLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic elem ent relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples:

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency.
The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – Bit 7 (MSB) = 0.78125% Enable Rate Definition Output enable rate is the average percentage of ti me during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. 1. The PLL dynamic contribution depends on th e input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution. Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Guideline 1 Toggle rate of VersaTile outputs 10% 2 I/O buffer toggle rate 10% Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation Component Definition Guideline 1 I/O output buffer enable rate 100% 2 RAM enable rate for read operations 12.5% 3 RAM enable rate for write operations 12.5%

ProASIC3 DC and Switching Characteristics User I/O Characteristics Timing Model Figure 2-2 • Timing Model Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case VCC = 1.425 V DQ Y Y DQDQ DQY Combinational Cell Combinational Cell Combinational Cell I/O Module (Registered) I/O Module (Non-Registered) Register Cell Register Cell I/O Module (Registered) I/O Module (Non-Registered) LVPECL (Applicable to Advanced I/O Banks Only)L LVPECL (Applicable to Advanced I/O Banks only) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) LVTTL 3.3 V Output drive strength = 12 mA High slew rate Y Combinational Cell Y Combinational Cell Y Combinational Cell I/O Module (Non-Registered) LVTTLOutput drive strength = 8 mA High slew rate I/O Module (Non-Registered) LVCMOS 1.5 VOutput drive strength = 4 mA High slew rate LVTTLOutput drive strength = 12 mA High slew rate I/O Module (Non-Registered) Input LVTTL Clock Input LVTTL Clock Input LVTTL Clock tPD = 0.56 ns tPD = 0.49 ns tDP = 1.34 ns tPD = 0.87 ns tDP = 2.64 ns (Advanced I/O Banks) tPD = 0.47 ns tDP = 3.66 ns (Advanced I/O Banks) tPD = 0.47 ns tDP = 3.97 ns (Advanced I/O Banks) tPD = 0.47 ns tPY = 0.76 ns (Advanced I/O Banks) tCLKQ = 0.55 ns tOCLKQ = 0.59 ns tSUD = 0.43 ns tOSUD = 0.31 ns tDP = 2.64 ns (Advanced I/O Banks) tPY = 0.76 ns (Advanced I/O Banks) tPY = 1.20 ns tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 0.76 ns (Advanced I/O Banks) tICLKQ = 0.24 ns tISUD = 0.26 ns tPY = 1.05 ns

ProASIC3 Flash Family FPGAs Revision 13 2-15 Figure 2-3 • Input Buffer Timing Model and Delays (example) tPY (R) PAD Y Vtrip GND tPY (F) Vtrip 50%50% VIH VCC VIL tDIN (R) DIN GND tDIN (F) 50%50% VCC PAD Y tPY D CLK Q I/O Interface DIN tDIN To Array tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F))

ProASIC3 DC and Switching Characteristics Figure 2-4 • Output Buffer Model and Delays (example) tDP (R) PAD VOL tDP (F) VtripVtrip VOH VCC D 50% 50% VCC 0 V DOUT 50% 50% 0 V tDOUT (R) tDOUT (F) From Array PAD tDP Std Load D CLK Q I/O Interface DOUT D tDOUT tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3 Flash Family FPGAs Revision 13 2-17 Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example) D CLK Q D CLK Q 10% VCCI tZL Vtrip 50% tHZ 90% VCCI tZH Vtrip 50% 50% tLZ 50% EOUT PAD D E 50% tEOUT (R) 50% tEOUT (F) PAD DOUT EOUT D I/O Interface E tEOUT tZLS Vtrip 50% tZHS Vtrip 50%EOUT PAD D E 50% 50%tEOUT (R) tEOUT (F) 50% VCC VCC VCC VCCI VCC VCC VCC VOH VOL VOL tZL, tZH, tHZ, tLZ, tZLS, tZHS tEOUT = MAX(tEOUT(r), tEOUT(f))

ProASIC3 DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—S oftware Default Settings Applicable to Advanced I/O Banks I/O Standard Drive Strength Equiv. Software Default Drive Strength Option2 Slew Rate VIL VIH VOL VOH IOL 1 IOH1 Min. V Max. V Min. V Max. V Max. V Min. Vm A m A

3.3 V LVTTL /

3.3 V LVCMOS 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Notes: 1. Currents are measured at 85°C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

ProASIC3 Flash Family FPGAs Revision 13 2-19 Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—S oftware Default Settings Applicable to Standard Plus I/O Banks I/O Standard Drive Strength Equiv. Software Default Drive Strength Option2 Slew Rate VIL VIH VOL VOH IOL 1 IOH Min. V Max. V Min. V Max. V Max. V Min. Vm A m A 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 1. Currents are measured at 85°C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

ProASIC3 DC and Switching Characteristics Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—S oftware Default Settings Applicable to Standard I/O Banks I/O Standard Drive Strength Equiv. Software Default Drive Strength Option2 Slew Rate VIL VIH VOL VOH IOL 1 IOH1 Min. V Max. V Min. V Max. V Max. V Min. Vm A m A 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 1. Currents are measured at 85°C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Table 2-21 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards Commercial1 Industrial2 IIL3 IIH4 IIL3 IIH4 µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCMOS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

Notes: 1. Commercial range (0°C < T A < 70°C) 2. Industrial range (–40°C < T A < 85°C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3V < VIN <VIL. 4. IIH is the input leakage current per I/O pin over reco mmended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges.

ProASIC3 Flash Family FPGAs Revision 13 2-21 Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-22 • Summary of AC Measuring Points Standard Measuring Trip Point (V trip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 3.3 V LVCMOS Wide Range 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 3.3 V PCI 0.285 * VCCI (RR) 0.615 * VCCI (FF) 3.3 V PCI-X 0.285 * VCCI (RR) 0.615 * VCCI (FF) Table 2-23 • I/O AC Parameter Definitions Parameter Parameter Definition t DP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer—High to Z tZH Enable to Pad delay through the Output Buffer—Z to High tLZ Enable to Pad delay through the Output Buffer—Low to Z tZL Enable to Pad delay through the Output Buffer—Z to Low tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to High tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

ProASIC3 DC and Switching Characteristics Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Advanced I/O Banks I/O Standard Drive Strength Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units

3.3 V LVCMOS

3.3 V PCI Per

3.3 V PCI-X Per

LVDS 24 mA – High – – 0.45 1.37 0.03 1.20 – – – – – – – ns LVPECL 24 mA – High – – 0.45 1.34 0.03 1.05 – – – – – – – ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for connectivity. This resistor is not required during normal operation.

ProASIC3 Flash Family FPGAs Revision 13 2-23 Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Standard Plus I/O Banks I/O Standard Drive Strength Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) tZLS (ns) tZHS (ns) Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for connectivity. This resistor is not required during normal operation.

ProASIC3 DC and Switching Characteristics Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Standard I/O Banks I/O Standard Drive Strength Equiv. Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tEOUT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-25 Detailed I/O DC Characteristics Table 2-27 • Input Capacitance Symbol Definition Cond itions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Table 2-28 • I/O Output Buffer Maximum Resistances1 Applicable to Advanced I/O Banks Standard Drive Strength R PULL-DOWN ()2 RPULL-UP ()3 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33 4 100 µA Same as regular

2.5 V LVCMOS 2 mA 100 200

1.8 V LVCMOS 2 mA 200 225

1.5 V LVCMOS 2 mA 200 224

3.3 V PCI/PCI-X Per PCI/PCI-X

Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

ProASIC3 DC and Switching Characteristics Table 2-29 • I/O Output Buffer Maximum Resistances 1 Applicable to Standard Plus I/O Banks Standard Drive Strength R PULL-DOWN ()2 RPULL-UP ()3 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 25 75 4 100 µA Same as regular Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.

ProASIC3 Flash Family FPGAs Revision 13 2-27 Table 2-30 • I/O Output Buffer Maximum Resistances1 Applicable to Standard I/O Banks Standard Drive Strength RPULL-DOWN ()2 RPULL-UP ()3 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150

3.3 V LVCMOS Wide Range4 100 µA Same as regular

Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec 4. All LVCMOS 3.3 V software macros support LVCM OS 3.3 V wide range as specified in the JESD-8B specification. Table 2-31 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values VCCI R(WEAK PULL-UP) () R(WEAK PULL-DOWN) () Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

3.3 V (wide range I/Os) 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

Notes: 1. R (WEAK PULL-UP-MAX) = (VCCIMAX – VOHspec) / I(WEAK PULL-UP-MIN) 2. R (WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)

ProASIC3 DC and Switching Characteristics Table 2-32 • I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks Drive Strength IOSL (mA) 1 IOSH (mA)1 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 12 mA 109 103 16 mA 127 132 24 mA 181 268 2 100 µA Same as regular

2.5 V LVCMOS 2 mA 18 16

1.8 V LVCMOS 2 mA 11 9

1.5 V LVCMOS 2 mA 16 13

Notes: 1. T J = 100°C 2. Applicable to 3.3 V LVCMOS Wide Range. I OSL/IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

ProASIC3 Flash Family FPGAs Revision 13 2-29 Table 2-33 • I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks Drive Strength IOSL (mA)* IOSH (mA)* 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 12 mA 109 103 16 mA 109 103 2 100 µA Same as regular Notes: 1. T J = 100°C 2. Applicable to 3.3 V LVCMOS Wide Range. IOSL /IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

ProASIC3 DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junc tion temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-34 • I/O Short Currents IOSH/IOSL Applicable to Standard I/O Banks Drive Strength IOSL (mA)* IOSH (mA)* 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 2 100 µA Same as regular Notes: 1. T J = 100°C 2. Applicable to 3.3 V LVCMOS Wide Range. I OSL/IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Table 2-35 • Duration of Short Circuit Event Before Failure Temperature Time before Failure –40°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C) LVDS/B-LVDS/ M-LVDS/LVPECL No requirement 10 ns * 10 years (100°C) Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more su sceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

ProASIC3 Flash Family FPGAs Revision 13 2-31 Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-37 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Table 2-38 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < V CCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray.

ProASIC3 DC and Switching Characteristics Table 2-39 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. I IH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-6 • AC Loading Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 03 . 3 1 . 4 3 5 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 35 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ

ProASIC3 Flash Family FPGAs Revision 13 2-33 Timing Characteristics Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-35 Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-37 Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVCMOS Wide Range Equiv. Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 2 IIH3 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V µA µA Max. mA Max. mA4 µA5 µA5 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 85°C junction temperature. 5. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 6. Software default selection highlighted in gray. Table 2-48 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks Equiv. Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 2 IIH3 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA4 Max. mA4 µA5 µA5 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 85°C junction temperature. 5. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 6. Software default selection highlighted in gray.

ProASIC3 Flash Family FPGAs Revision 13 2-39 Table 2-49 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVCMOS Wide Range Equiv. Software Default Drive Strength Option1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 2 IIH3 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. mA Max. mA4 µA5 µA5 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 85°C junction temperature. 5. All LVMCOS 3.3 V software macros s upport LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 6. Software default selection highlighted in gray.

ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Software default selection highlighted in gray. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-41 Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Software default selection highlighted in gray. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-43 Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V softwa re configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Software default selection highlighted in gray. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-45 Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Equiv. Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. Table 2-56 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH 2

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2

ProASIC3 Flash Family FPGAs Revision 13 2-47 Table 2-58 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks Min. V Max., V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-7 • AC Loading Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 02 . 5 1 . 2 3 5 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 35 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ

ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-60 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-49 Table 2-61 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-62 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-63 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-51 Table 2-64 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-65 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standa rd (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-66 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Strength Min. V Max., V Min. V Max. V Max. V Min. Vm A m A Max. mA Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Table 2-67 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100° C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray.

ProASIC3 Flash Family FPGAs Revision 13 2-53 Table 2-68 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over reco mmended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100° C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-8 • AC Loading Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 01 . 8 0 . 9 3 5 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 35 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ

ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-70 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-55 Table 2-71 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-72 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-57 Table 2-73 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-74 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-75 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-76 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Strength Min. V Max. V Min. V Max., V Max. V Min. Vm A m A Max. mA Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray.

ProASIC3 Flash Family FPGAs Revision 13 2-59 Table 2-77 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Table 2-78 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-9 • AC Loading Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 0 1.5 0.75 35 Note: *Measuring point = V trip. See Table 2-22 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 35 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ

ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-80 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP t DIN t PY t EOUT t ZL t ZH t LZ t HZ t ZLS t ZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-61 Table 2-81 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-82 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-83 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-84 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-63 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable path characterization are described in Figure 2-10. AC loadings are defined per PCI/PC I-X specifications for the datapath; Microsemi loading for tristate is described in Table 2-87. Table 2-85 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-86 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min. V Max. V Min. V Max. V Max,. V Min. Vm A m A Max. mA1 Max. mA1 µA2 µA2 Per PCI specification Per PCI curves 10 10 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-10 • AC Loading Test Point Enable Path R to VCCI for tLZ / tZL / tZLS 10 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ R to GND for tHZ / tZH / tZHS R = 1 k Test Point Datapath R = 25 R to VCCI for tDP (F) R to GND for tDP (R) Table 2-87 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 0 3.3 0.285 * VCCI for t DP(R) 0.615 * VCCI for tDP(F) Note: *Measuring point = Vtrip. See Table 2-22 on page 2-21 for a complete table of trip points.

ProASIC3 DC and Switching Characteristics Timing Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pa ir is handled by Microsemi Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjuncti on with the embedded Input R egister (InReg), Output Register (OutReg), Enable Register (EnReg), an d Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644 ) is a high-speed, differential I/O standard. It requires that one data bit be carried through two si gnal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The building blocks of the LVDS transmitter-receiver are one transmitte r macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, ProASIC3 also supports Bu s LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes). Table 2-88 • 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-89 • 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation 140  100  Z0 = 50  Z0 = 50  165  165  P N P N INBUF_LVDS OUTBUF_LVDS FPGA FPGA Bourns Part Number: CAT16-LV4F12

ProASIC3 Flash Family FPGAs Revision 13 2-65 Timing Characteristics Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter Description Min. Typ. Max. Units VCCI Supply Voltage 2.375 2.5 2.625 V VOL Output Low Voltage 0.9 1.075 1.25 V VOH Output High Voltage 1.25 1.425 1.6 V IOL 1 Output Lower Current 0.65 0.91 1.16 mA IOH 1 Output High Current 0.65 0.91 1.16 mA VI Input Voltage 0 2.925 V IIH 2,3 Input High Leakage Current 10 µA IIL 2,4 Input Low Leakage Current 10 µA VODIFF Differential Output Voltage 250 350 450 mV VOCM Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 V VIDIFF Input Differential Voltage 100 350 mV Notes: 1. IOL/ IOH defined by VODIFF/(Resistor Network) 2. Currents are measured at 85°C junction temperature. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <VCCI. Input current is larger when operating outside recommended ranges. 4. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN <VIL. Table 2-91 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.075 1.325 Cross point Note: *Measuring point = V trip. See Table 2-22 on page 2-21 for a complete table of trip points. Table 2-92 • LVDS Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade t DOUT tDP tDIN tPY Units –1 0.56 1.56 0.04 1.36 ns –2 0.49 1.37 0.03 1.20 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multid rop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accomm odate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appr opriate terminations. Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-12. The input and output buffer delays are available in the LVDS section in Table 2-92. Example: For a bus consisting of 20 equidistant lo ads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R S =6 0  and RT =7 0 , given Z0 =5 0  (2") and Zstub =5 0  (~1.5"). LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differ ential I/O standard. It requires that one data bit be carried through two signal lines . Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation beca use the output standard specifications are different. Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers ... RT RT BIBUF_LVDS R + - T + - R + - T + - D + - EN EN EN EN EN Receiver Transceiver Receiver Transceiver Driver RS RS RS RS RS RS RS RSRS RS Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation

187 W 100 

Z0 = 50  Z0 = 50  100  100  P N P N INBUF_LVPECL OUTBUF_LVPECLFPGA FPGA Bourns Part Number: CAT16-PC4F12

ProASIC3 Flash Family FPGAs Revision 13 2-67 Timing Characteristics Table 2-93 • Minimum and Maximum DC Input and Output Levels VCCI Supply Voltage 3.0 3.3 3.6 V VIL, VIH Input Low, Input High Voltages 0 3.6 0 3.6 0 3.6 V VIDIFF Input Differential Voltage 300 300 300 mV Table 2-94 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.64 1.94 Cross point Note: *Measuring point = V trip. See Table 2-22 on page 2-21 for a complete table of trip points. Table 2-95 • LVPECL Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade t DOUT tDP tDIN tPY Units –1 0.56 1.53 0.04 1.19 ns –2 0.49 1.34 0.03 1.05 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF INBUF INBUF TRIBUF CLKBUF INBUFINBUFCLKBUF Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered Pad Out CLK Enable Preset Data_out Data EOUT DOUT Enable CLK DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE D_Enable A B C D E E E E F G H I J L K Y Core Array

ProASIC3 Flash Family FPGAs Revision 13 2-69 Table 2-96 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register H, DOUT tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A Note: *See Figure 2-14 on page 2-68 for more information.

ProASIC3 DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Enable CLK Pad Out CLK Enable CLR Data_out Data Y AA EOUT DOUT Core ArrayDQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR D_Enable BB CC DD EE FF GG LL HH JJ KK CLKBUF INBUF INBUF TRIBUF INBUF INBUF CLKBUF INBUF Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered

ProASIC3 Flash Family FPGAs Revision 13 2-71 Table 2-97 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA Note: *See Figure 2-15 on page 2-70 for more information.

ProASIC3 DC and Switching Characteristics Input Register Timing Characteristics Figure 2-16 • Input Register Timing Diagram 50% Preset Clear Out_1 CLK Data Enable tISUE 50% 50% tISUD tIHD 50% 50% tICLKQ 1 0 tIHE tIRECPRE tIREMPRE tIRECCLR tIREMCLRtIWCLR tIWPRE tIPRE2Q tICLR2Q tICKMPWH tICKMPWL 50% 50% 50% 50% 50% 50% 50% 50% Table 2-98 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units t ICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 ns tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.36 0.41 0.48 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.32 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-73 Output Register Timing Characteristics Figure 2-17 • Output Register Timing Diagram Preset Clear DOUT CLK Data_out Enable tOSUE 50% 50% tOSUD tOHD 50% 50% tOCLKQ 1 0 tOHE tORECPRE tOREMPRE tORECCLR tOREMCLRtOWCLR tOWPRE tOPRE2Q tOCLR2Q tOCKMPWH tOCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-99 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 ns tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.36 0.41 0.48 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.32 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Output Enable Register Figure 2-18 • Output Enable Register Timing Diagram 50% Preset Clear EOUT CLK D_Enable Enable tOESUE 50% 50% tOESUDtOEHD 50% 50% tOECLKQ 1 0 tOEHE tOERECPRE tOEREMPRE tOERECCLR tOEREMCLRtOEWCLR tOEWPRE tOEPRE2Q tOECLR2Q tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% 50%

ProASIC3 Flash Family FPGAs Revision 13 2-75 Timing Characteristics Table 2-100 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.67 0.79 ns tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.36 0.41 0.48 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.32 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics DDR Module Specifications Input DDR Module Figure 2-19 • Input DDR Timing Model Table 2-101 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B Input DDR Data CLK CLKBUF INBUF Out_QF (to core) FF2 FF1 INBUF CLR DDR_IN E A B C D Out_QR (to core)

ProASIC3 Flash Family FPGAs Revision 13 2-77 Timing Characteristics Figure 2-20 • Input DDR Timing Diagram tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRICLR2Q1 12 3 4 5 6 7 8 9 CLK Data CLR Out_QR Out_QF tDDRICLKQ1 2 4 6 3 5 7 tDDRIHDtDDRISUD tDDRICLKQ2 Table 2-102 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.27 0.31 0.37 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.39 0.44 0.52 ns tDDRISUD Data Setup for Input DDR (Fall) 0.25 0.28 0.33 ns Data Setup for Input DDR (Rise) 0.25 0.28 0.33 ns tDDRIHD Data Hold for Input DDR (Fall) 0.00 0.00 0.00 ns Data Hold for Input DDR (Rise) 0.00 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.46 0.53 0.62 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.57 0.65 0.76 ns tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.22 0.25 0.30 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 ns tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.41 0.48 ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.37 0.43 ns FDDRIMAX Maximum Frequency for Input DDR 350 309 263 MHz Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Output DDR Module Figure 2-21 • Output DDR Timing Model Table 2-103 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B Data_F (from core) CLK CLKBUF Out FF2 INBUF CLR DDR_OUT Output DDR FF1 X X X X X X X A B D EC C B OUTBUFData_R (from core)

ProASIC3 Flash Family FPGAs Revision 13 2-79 Timing Characteristics Figure 2-22 • Output DDR Timing Diagram 116 91 0 28 3 9 tDDROREMCLR tDDROHD1tDDROREMCLR tDDROHD2tDDROSUD2 tDDROCLKQ tDDRORECCLR CLK Data_R Data_F CLR Out tDDROCLR2Q 71 0 4 Table 2-104 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 ns tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 ns tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.36 0.41 0.48 ns tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.32 0.37 0.43 ns FDDOMAX Maximum Frequency for the Output DDR 350 309 263 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT- 3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO®/e, and ProASIC3/E Macro Library Guide. Figure 2-23 • Sample of Combinatorial Cells MAJ3 A C BY MUX2 B A S Y AY B B A XOR2 Y NOR2 B A Y B A YOR2 INV A YAND2 B A Y NAND3B A C XOR3 YB A C NAND2

ProASIC3 Flash Family FPGAs Revision 13 2-81 Figure 2-24 • Timing Model and Waveforms tPD A B tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell YNAND2 or Any Combinatorial Logic t PD tPD 50% VCC VCC VCC 50% GNDA, B, C 50% 50% 50% (RR) (RF) GND OUT OUT GND 50% (FF) (FR) tPD tPD

ProASIC3 DC and Switching Characteristics Timing Characteristics VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. Table 2-105 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter –2 –1 Std. Units INV Y = !A t PD 0.40 0.46 0.54 ns AND2 Y = A · B t PD 0.47 0.54 0.63 ns NAND2 Y = !(A · B) t PD 0.47 0.54 0.63 ns OR2 Y = A + B t PD 0.49 0.55 0.65 ns NOR2 Y = !(A + B) t PD 0.49 0.55 0.65 ns XOR2 Y = A Bt PD 0.74 0.84 0.99 ns MAJ3 Y = MAJ(A, B, C) t PD 0.70 0.79 0.93 ns XOR3 Y = A  B Ct PD 0.87 1.00 1.17 ns MUX2 Y = A !S + B S t PD 0.51 0.58 0.68 ns AND3 Y = A · B · C t PD 0.56 0.64 0.75 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Figure 2-25 • Sample of Sequential Cells DQ DFN1 Data CLK Out D Q DFN1C1 Data CLK Out CLR DQ DFI1E1P1 Data CLK Out En PRE D Q DFN1E1 Data CLK Out En

ProASIC3 Flash Family FPGAs Revision 13 2-83 Timing Characteristics Figure 2-26 • Timing Model and Waveforms PRE CLR Out CLK Data EN tSUE 50% 50% tSUD tHD 50% 50% tCLKQ tHE tRECPRE tREMPRE tRECCLR tREMCLRtWCLR tWPRE tPRE2Q tCLR2Q tCKMPWH tCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-106 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 ns tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 ns tHD Data Hold Time for the Core Register 0.00 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 ns tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.32 0.37 0.43 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.36 0.41 0.48 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Global Resource Characteristics A3P250 Clock Tree Topology Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flip-flops in the device. Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-89 . Table 2-108 to Table 2-114 on page 2-88 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing Central Global Rib VersaTile Rows Global Spine CCC

ProASIC3 Flash Family FPGAs Revision 13 2-85 Timing Characteristics Table 2-107 • A3P015 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.18 0.21 0.25 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-108 • A3P030 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.18 0.21 0.24 ns Notes: 1. Value reflects minimum load . The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-109 • A3P060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-110 • A3P125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-87 Table 2-111 • A3P250 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns Notes: 1. Value reflects minimum load . The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-112 • A3P400 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-113 • A3P600 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-114 • A3P1000 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width High for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.35 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-89 Clock Conditioning Circuits Timing Characteristics Table 2-115 • ProASIC3 CCC/PLL Specification Parameter Minimum Typical Maximum Units Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz Serial Clock (SCLK) for Dynamic PLL1 125 MHz Delay Increments in Programmable Delay Blocks2, 3 2004 ps Number of Programmable Values in Each Programmable Delay Block Input Period Jitter 1.5 ns CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter

1 Global

3 Global

0.75 MHz to 24 MHz 0.50% 0.70% 24 MHz to 100 MHz 1.00% 1.20% 100 MHz to 250 MHz 1.75% 2.00% 250 MHz to 350 MHz 2.50% 5.60% Acquisition Time (A3P250 and A3P1000 only) LockControl = 0 300 µs LockControl = 1 300 µs (all other dies) LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter (A3P250 and A3P1000 only) LockControl = 0 1.6 ns LockControl = 1 1.6 ns (all other dies) LockControl = 0 1.6 ns LockControl = 1 0.8 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 2, 3 0.6 5.56 ns Delay Range in Block: Programmable Delay 22, 3 0.225 5.56 ns Delay Range in Block: Fixed Delay2, 3 2.2 ns Notes: 1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings. 3. T J = 25°C, VCC = 1.5 V 4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help for more information. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 6. The A3P030 device does not contain a PLL.

ProASIC3 DC and Switching Characteristics Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-28 • Peak-to-Peak Jitter Definition Tperiod_max Tperiod_min Output Signal

ProASIC3 Flash Family FPGAs Revision 13 2-91 Embedded SRAM and FIFO Characteristics SRAM Figure 2-29 • RAM Models ADDRA11 DOUTA8 DOUTA7 DOUTA0 DOUTB8 DOUTB7 DOUTB0 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RAM4K9 RADDR8 RD17 RADDR7 RD16 RADDR0 RD0 WD17 WD16 WD0 WW1 WW0 RW1 RW0 PIPE REN RCLK RAM512X18 WADDR8 WADDR7 WADDR0 WEN WCLK RESETRESET

ProASIC3 DC and Switching Characteristics Timing Characteristics Figure 2-34 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18. CLK RESET DOUT|RD Dn tCYC tCKH tCKL tRSTBQ Dm Table 2-116 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tAS Address setup time 0.25 0.28 0.33 ns tAH Address hold time 0.00 0.00 0.00 ns tENS REN, WEN setup time 0.14 0.16 0.19 ns tENH REN, WEN hold time 0.10 0.11 0.13 ns tBKS BLK setup time 0.23 0.27 0.31 ns tBKH BLK hold time 0.02 0.02 0.02 ns tDS Input data (DIN) setup time 0.18 0.21 0.25 ns tDH Input data (DIN) hold time 0.00 0.00 0.00 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 2.36 2.68 3.15 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 1.79 2.03 2.39 ns tCKQ2 Clock High to new data valid on DOUT (pipelined) 0.89 1.02 1.20 ns tC2CWWL

1 Address collision clk-to-clk delay for reliable write after write on same

address—Applicable to Closing Edge 0.33 0.28 0.25 ns tC2CWWH address—Applicable to Rising Edge 0.30 0.26 0.23 ns tC2CRWH

1 Address collision clk-to-clk delay for reliable read access after write on same

address—Applicable to Opening Edge 0.45 0.38 0.34 ns tC2CWRH

1 Address collision clk-to-clk delay for reliable write access after read on same

address— Applicable to Opening Edge 0.49 0.42 0.37 ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on DOUT (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET removal 0.29 0.33 0.38 ns Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-95 tRECRSTB RESET recovery 1.50 1.71 2.01 ns tMPWRSTB RESET minimum pulse width 0.21 0.24 0.29 ns tCYC Clock cycle time 3.23 3.68 4.32 ns FMAX Maximum frequency 310 272 231 MHz Table 2-116 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V (continued) Parameter Description –2 –1 Std. Units Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-117 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tAS Address setup time 0.25 0.28 0.33 ns tAH Address hold time 0.00 0.00 0.00 ns tENS REN, WEN setup time 0.13 0.15 0.17 ns tENH REN, WEN hold time 0.10 0.11 0.13 ns tDS Input data (WD) setup time 0.18 0.21 0.25 ns tDH Input data (WD) hold time 0.00 0.00 0.00 ns tCKQ1 Clock High to new data valid on RD (output retained) 2.16 2.46 2.89 ns tCKQ2 Clock High to new data valid on RD (pipelined) 0.90 1.02 1.20 ns tC2CRWH address—Applicable to Opening Edge 0.50 0.43 0.38 ns tC2CWRH address—Applicable to Opening Edge 0.59 0.50 0.44 ns tRSTBQ RESET Low to data out Low on RD (flow-through) 0.92 1.05 1.23 ns RESET Low to data out Low on RD (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET removal 0.29 0.33 0.38 ns tRECRSTB RESET recovery 1.50 1.71 2.01 ns tMPWRSTB RESET minimum pulse width 0.21 0.24 0.29 ns tCYC Clock cycle time 3.23 3.68 4.32 ns FMAX Maximum frequency 310 272 231 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 Flash Family FPGAs Revision 13 2-97 FIFO Figure 2-35 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 WW0 RD0 ESTOP FSTOP FULL AFULL EMPTY AFVAL11 AEMPTY AFVAL10 AFVAL0 AEVAL11 AEVAL10 AEVAL0 REN RBLK RCLK WEN WBLK WCLK RPIPE WD17 WD16 WD0 RESET

ProASIC3 Flash Family FPGAs Revision 13 2-101 Timing Characteristics Table 2-118 • FIFO (for all dies except A3P250) Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN, WEN Setup Time 1.34 1.52 1.79 ns tENH REN, WEN Hold Time 0.00 0.00 0.00 ns tBKS BLK Setup Time 0.19 0.22 0.26 ns tBKH BLK Hold Time 0.00 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.17 2.47 2.90 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.94 1.07 1.26 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on RD (pipelined) 0 .92 1.05 1.23 ns tREMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency for FIFO 310 272 231 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

ProASIC3 DC and Switching Characteristics Table 2-119 • FIFO (for A3P250 only, aspect-ratio-dependent) Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN, WEN Setup Time 3.26 3.71 4.36 ns tENH REN, WEN Hold Time 0.00 0.00 0.00 ns tBKS BLK Setup Time 0.19 0.22 0.26 ns tBKH BLK Hold Time 0.00 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.17 2.47 2.90 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.94 1.07 1.26 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0 .92 1.05 1.23 ns RESET Low to Data Out Low on RD (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency for FIFO 310 272 231 MHz

ProASIC3 Flash Family FPGAs Revision 13 2-103 Table 2-120 • A3P250 FIFO 512×8 Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN, WEN Setup Time 3.75 4.27 5.02 ns tENH REN, WEN Hold Time 0.00 0.00 0.00 ns tBKS BLK Setup Time 0.19 0.22 0.26 ns tBKH BLK Hold Time 0.00 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.17 2.47 2.90 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.94 1.07 1.26 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on RD (pipelined) 0 .92 1.05 1.23 ns tREMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency for FIFO 310 272 231 MHz

ProASIC3 DC and Switching Characteristics Table 2-121 • A3P250 FIFO 1k×4 Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN, WEN Setup Time 4.05 4.61 5.42 ns tENH REN, WEN Hold Time 0.00 0.00 0.00 ns tBKS BLK Setup Time 0.19 0.22 0.26 ns tBKH BLK Hold Time 0.00 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.36 2.68 3.15 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.89 1.02 1.20 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on RD (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency for FIFO 310 272 231 MHz

ProASIC3 Flash Family FPGAs Revision 13 2-105 Table 2-122 • A3P250 FIFO 2k×2 Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN, WEN Setup Time 4.39 5.00 5.88 ns tENH REN, WEN Hold Time 0.00 0.00 0.00 ns tBKS BLK Setup Time 0.19 0.22 0.26 ns tBKH BLK Hold Time 0.00 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.36 2.68 3.15 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.89 1.02 1.20 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on RD (pipelined) 0 .92 1.05 1.23 ns t REMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency for FIFO 310 272 231 MHz

ProASIC3 DC and Switching Characteristics Table 2-123 • A3P250 FIFO 4k×1 Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN, WEN Setup Time 4.86 5.53 6.50 ns tENH REN, WEN Hold Time 0.00 0.00 0.00 ns tBKS BLK Setup Time 0.19 0.22 0.26 ns tBKH BLK Hold Time 0.00 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.36 2.68 3.15 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.89 1.02 1.20 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on DO (pass-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 ns t REMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency 310 272 231 MHz

ProASIC3 Flash Family FPGAs Revision 13 2-107 Embedded FlashROM Characteristics Timing Characteristics Figure 2-43 • Timing Diagram A0 A1 tSU tHOLD tSU tHOLD tSU tHOLD tCKQ2 tCKQ2 tCKQ2 CLK Address Data D0 D0 D1 Table 2-124 • Embedded FlashROM Access Time Parameter Description –2 –1 Std. Units tSU Address Setup Time 0.53 0.61 0.71 ns tHOLD Address Hold Time 0.00 0.00 0.00 ns tCK2Q Clock to Out 21.42 24.40 28.68 ns FMAX Maximum Clock Frequency 15 15 15 MHz

ProASIC3 DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-14 for more details. Timing Characteristics Table 2-125 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDISU Test Data Input Setup Time 0.50 0.57 0.67 ns tDIHD Test Data Input Hold Time 1.00 1.13 1.33 ns tTMSSU Test Mode Select Setup Time 0.50 0.57 0.67 ns tTMDHD Test Mode Select Hold Time 1.00 1.13 1.33 ns tTCK2Q Clock to Q (data out) 6.00 6.80 8.00 ns tRSTB2Q Reset to Q (data out) 20.00 22.67 26.67 ns FTCKMAX TCK Maximum Frequency 25.00 22.00 19.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.20 0.23 0.27 ns tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

3 – Pin Descriptions Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise orig inated from the output buffer ground domain. This minimizes the noise transfer within the package and im proves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a gi ven I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V. When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Deco upling section of the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for a complete board solution for the PLL analog power supply and ground. There is one VCCPLF pin on ProASIC3 devices. VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. There is one VCOMPLF pin on ProASIC3 devices. VJTAG JTAG Supply Voltage Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isol ating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and si mplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is

insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. Duri ng normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in Table 2-2 on page 2-2. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tr istated and weakly pulled up to V CCI. With V CCI, VMV, and V CC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows:

Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed GL Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connecti vity in the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For exampl e, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant global s. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the I/O Structure section of the handbook fo r the device you are using for an explanation of the naming of global pins. FF Flash*Freeze Mode Activation Pin Flash*Freeze is available on IGLOO, ProASIC3L, an d RT ProASIC3 devices. It is not supported on ProASIC3/E devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active-low, has the same characteristi cs as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. For IGLOOe, ProASIC3EL, and RT ProASIC3 only, the FF pin can be configured as a Schmitt trigger input. When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single- ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin

ProASIC3 Flash Family FPGAs Revision 13 3-3 should be treated as a sensitive asynchronous signa l. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pul l-up. This default config uration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. JTAG Pins Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VC C must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in s upply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull- up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Refer to Table 1 for more information. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP , and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull- down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 1 and must satisfy the parallel resistance value requirement. The values in Table 1 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circui t could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Table 1 • Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200  to 1 k VJTAG at 2.5 V 200  to 1 k VJTAG at 1.8 V 500  to 1 k VJTAG at 1.5 V 500  to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down.

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Related Documents User’s Guides ProASIC FPGA Fabric User’s Guide http://www.microsemi.com/soc/documents/PA3_UG.pdf Packaging The following documents provide packaging information and device selection for low power flash devices. Product Catalog http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf This document contains the package mechanical dr awings for all packages currently or previously supplied by Actel. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials are at http://www.microsemi.com/products/solutions/package/docs.aspx.

4 – Package Pin Assignments QN48 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Pin 1

Pin Number A3P030 Function

1 IO82RSB1

2 GEC0/IO73RSB1

3 GEA0/IO72RSB1

4 GEB0/IO71RSB1

6 VCCIB1

7 IO68RSB1

8 IO67RSB1

9 IO66RSB1

10 IO65RSB1

11 IO64RSB1

12 IO62RSB1

13 IO61RSB1

14 IO60RSB1

15 IO57RSB1

16 IO55RSB1

17 IO53RSB1

18 VCC

19 VCCIB1

20 IO46RSB1

21 IO42RSB1

22 TCK

23 TDI

24 TMS

25 VPUMP

26 TDO

27 TRST

28 VJTAG

29 IO38RSB0

30 GDB0/IO34RSB0

31 GDA0/IO33RSB0

32 GDC0/IO32RSB0

33 VCCIB0

34 GND

35 VCC

36 IO25RSB0

37 IO24RSB0

38 IO22RSB0

39 IO20RSB0

40 IO18RSB0

41 IO16RSB0

42 IO14RSB0

43 IO10RSB0

44 IO08RSB0

45 IO06RSB0

46 IO04RSB0

47 IO02RSB0

48 IO00RSB0

Pin Number A3P030 Function

ProASIC3 Flash Family FPGAs Revision 13 4-3 QN68 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Pin A1 Mark

Pin Number A3P015 Function

2 IO80RSB1

3 IO78RSB1

4 IO76RSB1

5 GEC0/IO73RSB1

6 GEA0/IO72RSB1

7 GEB0/IO71RSB1

10 VCCIB1

11 IO68RSB1

12 IO67RSB1

13 IO66RSB1

14 IO65RSB1

15 IO64RSB1

16 IO63RSB1

17 IO62RSB1

18 IO60RSB1

19 IO58RSB1

20 IO56RSB1

21 IO54RSB1

22 IO52RSB1

23 IO51RSB1

24 VCC

25 GND

26 VCCIB1

27 IO50RSB1

28 IO48RSB1

29 IO46RSB1

30 IO44RSB1

31 IO42RSB1

32 TCK

33 TDI

34 TMS

35 VPUMP

36 TDO

37 TRST

38 VJTAG

39 IO40RSB0

40 IO37RSB0

41 GDB0/IO34RSB0

42 GDA0/IO33RSB0

43 GDC0/IO32RSB0

44 VCCIB0

45 GND

46 VCC

47 IO31RSB0

48 IO29RSB0

49 IO28RSB0

50 IO27RSB0

51 IO25RSB0

52 IO24RSB0

53 IO22RSB0

54 IO21RSB0

55 IO19RSB0

56 IO17RSB0

57 IO15RSB0

58 IO14RSB0

59 VCCIB0

60 GND

61 VCC

62 IO12RSB0

63 IO10RSB0

64 IO08RSB0

65 IO06RSB0

66 IO04RSB0

67 IO02RSB0

68 IO00RSB0

Pin Number A3P015 Function

ProASIC3 Flash Family FPGAs Revision 13 4-5 QN68 Pin Number A3P030 Function Pin Number A3P030 Function

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). A37 A12 A36 A25 A48 A24 A13 B34 B11 B44 B22 B12 C31 C10 B33 B23 C30 C21 C40 C20 C11 Optional Corner Pad (4x) Pin A1Mark

ProASIC3 Flash Family FPGAs Revision 13 4-7 QN132 Pin Number A3P030 Function A1 IO01RSB1 A2 IO81RSB1 A3 NC A4 IO80RSB1 A5 GEC0/IO77RSB1 A6 NC A7 GEB0/IO75RSB1 A8 IO73RSB1 A9 NC A10 VCC A11 IO71RSB1 A12 IO68RSB1 A13 IO63RSB1 A14 IO60RSB1 A15 NC A16 IO59RSB1 A17 IO57RSB1 A18 VCC A19 IO54RSB1 A20 IO52RSB1 A21 IO49RSB1 A22 IO48RSB1 A23 IO47RSB1 A24 TDI A25 TRST A26 IO44RSB0 A27 NC A28 IO43RSB0 A29 IO42RSB0 A30 IO40RSB0 A31 IO39RSB0 A32 GDC0/IO36RSB0 A33 NC A34 VCC A35 IO34RSB0 A36 IO31RSB0 A37 IO26RSB0 A38 IO23RSB0 A39 NC A40 IO22RSB0 A41 IO20RSB0 A42 IO18RSB0 A43 VCC A44 IO15RSB0 A45 IO12RSB0 A46 IO10RSB0 A47 IO09RSB0 A48 IO06RSB0 B1 IO02RSB1 B2 IO82RSB1 B3 GND B4 IO79RSB1 B5 NC B6 GND B7 IO74RSB1 B8 NC B9 GND B10 IO70RSB1 B11 IO67RSB1 B12 IO64RSB1 B13 IO61RSB1 B14 GND B15 IO58RSB1 B16 IO56RSB1 B17 GND B18 IO53RSB1 B19 IO50RSB1 B20 GND B21 IO46RSB1 B22 TMS B23 TDO B24 IO45RSB0 QN132 Pin Number A3P030 Function B25 GND B26 NC B27 IO41RSB0 B28 GND B29 GDA0/IO37RSB0 B30 NC B31 GND B32 IO33RSB0 B33 IO30RSB0 B34 IO27RSB0 B35 IO24RSB0 B36 GND B37 IO21RSB0 B38 IO19RSB0 B39 GND B40 IO16RSB0 B41 IO13RSB0 B42 GND B43 IO08RSB0 B44 IO05RSB0 C1 IO03RSB1 C2 IO00RSB1 C3 NC C4 IO78RSB1 C5 GEA0/IO76RSB1 C6 NC C7 NC C8 VCCIB1 C9 IO69RSB1 C10 IO66RSB1 C11 IO65RSB1 C12 IO62RSB1 C13 NC C14 NC C15 IO55RSB1 C16 VCCIB1 QN132 Pin Number A3P030 Function

Pin Number A3P030 Function

ProASIC3 Flash Family FPGAs Revision 13 4-9 QN132 Pin Number A3P060 Function A1 GAB2/IO00RSB1 A2 IO93RSB1 A3 VCCIB1 A4 GFC1/IO89RSB1 A5 GFB0/IO86RSB1 A6 VCCPLF A7 GFA1/IO84RSB1 A8 GFC2/IO81RSB1 A9 IO78RSB1 A10 VCC A11 GEB1/IO75RSB1 A12 GEA0/IO72RSB1 A13 GEC2/IO69RSB1 A14 IO65RSB1 A15 VCC A16 IO64RSB1 A17 IO63RSB1 A18 IO62RSB1 A19 IO61RSB1 A20 IO58RSB1 A21 GDB2/IO55RSB1 A22 NC A23 GDA2/IO54RSB1 A24 TDI A25 TRST A26 GDC1/IO48RSB0 A27 VCC A28 IO47RSB0 A29 GCC2/IO46RSB0 A30 GCA2/IO44RSB0 A31 GCA0/IO43RSB0 A32 GCB1/IO40RSB0 A33 IO36RSB0 A34 VCC A35 IO31RSB0 A36 GBA2/IO28RSB0 A37 GBB1/IO25RSB0 A38 GBC0/IO22RSB0 A39 VCCIB0 A40 IO21RSB0 A41 IO18RSB0 A42 IO15RSB0 A43 IO14RSB0 A44 IO11RSB0 A45 GAB1/IO08RSB0 A46 NC A47 GAB0/IO07RSB0 A48 IO04RSB0 B1 IO01RSB1 B2 GAC2/IO94RSB1 B3 GND B4 GFC0/IO88RSB1 B5 VCOMPLF B6 GND B7 GFB2/IO82RSB1 B8 IO79RSB1 B9 GND B10 GEB0/IO74RSB1 B11 VMV1 B12 GEB2/IO70RSB1 B13 IO67RSB1 B14 GND B15 NC B16 NC B17 GND B18 IO59RSB1 B19 GDC2/IO56RSB1 B20 GND B21 GNDQ B22 TMS B23 TDO B24 GDC0/IO49RSB0 QN132 Pin Number A3P060 Function B25 GND B26 NC B27 GCB2/IO45RSB0 B28 GND B29 GCB0/IO41RSB0 B30 GCC1/IO38RSB0 B31 GND B32 GBB2/IO30RSB0 B33 VMV0 B34 GBA0/IO26RSB0 B35 GBC1/IO23RSB0 B36 GND B37 IO20RSB0 B38 IO17RSB0 B39 GND B40 IO12RSB0 B41 GAC0/IO09RSB0 B42 GND B43 GAA1/IO06RSB0 B44 GNDQ C1 GAA2/IO02RSB1 C2 IO95RSB1 C3 VCC C4 GFB1/IO87RSB1 C5 GFA0/IO85RSB1 C6 GFA2/IO83RSB1 C7 IO80RSB1 C8 VCCIB1 C9 GEA1/IO73RSB1 C10 GNDQ C11 GEA2/IO71RSB1 C12 IO68RSB1 C13 VCCIB1 C14 NC C15 NC C16 IO60RSB1 QN132 Pin Number A3P060 Function

Pin Number A3P060 Function

ProASIC3 Flash Family FPGAs Revision 13 4-11 QN132 Pin Number A3P125 Function A1 GAB2/IO69RSB1 A2 IO130RSB1 A3 VCCIB1 A4 GFC1/IO126RSB1 A5 GFB0/IO123RSB1 A6 VCCPLF A7 GFA1/IO121RSB1 A8 GFC2/IO118RSB1 A9 IO115RSB1 A10 VCC A11 GEB1/IO110RSB1 A12 GEA0/IO107RSB1 A13 GEC2/IO104RSB1 A14 IO100RSB1 A15 VCC A16 IO99RSB1 A17 IO96RSB1 A18 IO94RSB1 A19 IO91RSB1 A20 IO85RSB1 A21 IO79RSB1 A22 VCC A23 GDB2/IO71RSB1 A24 TDI A25 TRST A26 GDC1/IO61RSB0 A27 VCC A28 IO60RSB0 A29 GCC2/IO59RSB0 A30 GCA2/IO57RSB0 A31 GCA0/IO56RSB0 A32 GCB1/IO53RSB0 A33 IO49RSB0 A34 VCC A35 IO44RSB0 A36 GBA2/IO41RSB0 A37 GBB1/IO38RSB0 A38 GBC0/IO35RSB0 A39 VCCIB0 A40 IO28RSB0 A41 IO22RSB0 A42 IO18RSB0 A43 IO14RSB0 A44 IO11RSB0 A45 IO07RSB0 A46 VCC A47 GAC1/IO05RSB0 A48 GAB0/IO02RSB0 B1 IO68RSB1 B2 GAC2/IO131RSB1 B3 GND B4 GFC0/IO125RSB1 B5 VCOMPLF B6 GND B7 GFB2/IO119RSB1 B8 IO116RSB1 B9 GND B10 GEB0/IO109RSB1 B11 VMV1 B12 GEB2/IO105RSB1 B13 IO101RSB1 B14 GND B15 IO98RSB1 B16 IO95RSB1 B17 GND B18 IO87RSB1 B19 IO81RSB1 B20 GND B21 GNDQ B22 TMS B23 TDO B24 GDC0/IO62RSB0 QN132 Pin Number A3P125 Function B25 GND B26 NC B27 GCB2/IO58RSB0 B28 GND B29 GCB0/IO54RSB0 B30 GCC1/IO51RSB0 B31 GND B32 GBB2/IO43RSB0 B33 VMV0 B34 GBA0/IO39RSB0 B35 GBC1/IO36RSB0 B36 GND B37 IO26RSB0 B38 IO21RSB0 B39 GND B40 IO13RSB0 B41 IO08RSB0 B42 GND B43 GAC0/IO04RSB0 B44 GNDQ C1 GAA2/IO67RSB1 C2 IO132RSB1 C3 VCC C4 GFB1/IO124RSB1 C5 GFA0/IO122RSB1 C6 GFA2/IO120RSB1 C7 IO117RSB1 C8 VCCIB1 C9 GEA1/IO108RSB1 C10 GNDQ C11 GEA2/IO106RSB1 C12 IO103RSB1 C13 VCCIB1 C14 IO97RSB1 C15 IO93RSB1 C16 IO89RSB1 QN132 Pin Number A3P125 Function

Pin Number A3P125 Function

ProASIC3 Flash Family FPGAs Revision 13 4-13 QN132 Pin Number A3P250 Function A1 GAB2/IO117UPB3 A2 IO117VPB3 A3 VCCIB3 A4 GFC1/IO110PDB3 A5 GFB0/IO109NPB3 A6 VCCPLF A7 GFA1/IO108PPB3 A8 GFC2/IO105PPB3 A9 IO103NDB3 A10 VCC A11 GEA1/IO98PPB3 A12 GEA0/IO98NPB3 A13 GEC2/IO95RSB2 A14 IO91RSB2 A15 VCC A16 IO90RSB2 A17 IO87RSB2 A18 IO85RSB2 A19 IO82RSB2 A20 IO76RSB2 A21 IO70RSB2 A22 VCC A23 GDB2/IO62RSB2 A24 TDI A25 TRST A26 GDC1/IO58UDB1 A27 VCC A28 IO54NDB1 A29 IO52NDB1 A30 GCA2/IO51PPB1 A31 GCA0/IO50NPB1 A32 GCB1/IO49PDB1 A33 IO47NSB1 A34 VCC A35 IO41NPB1 A36 GBA2/IO41PPB1 A37 GBB1/IO38RSB0 A38 GBC0/IO35RSB0 A39 VCCIB0 A40 IO28RSB0 A41 IO22RSB0 A42 IO18RSB0 A43 IO14RSB0 A44 IO11RSB0 A45 IO07RSB0 A46 VCC A47 GAC1/IO05RSB0 A48 GAB0/IO02RSB0 B1 IO118VDB3 B2 GAC2/IO116UDB3 B3 GND B4 GFC0/IO110NDB3 B5 VCOMPLF B6 GND B7 GFB2/IO106PSB3 B8 IO103PDB3 B9 GND B10 GEB0/IO99NDB3 B11 VMV3 B12 GEB2/IO96RSB2 B13 IO92RSB2 B14 GND B15 IO89RSB2 B16 IO86RSB2 B17 GND B18 IO78RSB2 B19 IO72RSB2 B20 GND B21 GNDQ B22 TMS B23 TDO B24 GDC0/IO58VDB1 QN132 Pin Number A3P250 Function B25 GND B26 IO54PDB1 B27 GCB2/IO52PDB1 B28 GND B29 GCB0/IO49NDB1 B30 GCC1/IO48PDB1 B31 GND B32 GBB2/IO42PDB1 B33 VMV1 B34 GBA0/IO39RSB0 B35 GBC1/IO36RSB0 B36 GND B37 IO26RSB0 B38 IO21RSB0 B39 GND B40 IO13RSB0 B41 IO08RSB0 B42 GND B43 GAC0/IO04RSB0 B44 GNDQ C1 GAA2/IO118UDB3 C2 IO116VDB3 C3 VCC C4 GFB1/IO109PPB3 C5 GFA0/IO108NPB3 C6 GFA2/IO107PSB3 C7 IO105NPB3 C8 VCCIB3 C9 GEB1/IO99PDB3 C10 GNDQ C11 GEA2/IO97RSB2 C12 IO94RSB2 C13 VCCIB2 C14 IO88RSB2 C15 IO84RSB2 C16 IO80RSB2 QN132 Pin Number A3P250 Function

Pin Number A3P250 Function

ProASIC3 Flash Family FPGAs Revision 13 4-15 CS121 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). 11 10 1 23456789 A B C D E F G H J K L

Pin Number A3P060 Function A1 GNDQ A2 IO01RSB0 A3 GAA1/IO03RSB0 A4 GAC1/IO07RSB0 A5 IO15RSB0 A6 IO13RSB0 A7 IO17RSB0 A8 GBB1/IO22RSB0 A9 GBA1/IO24RSB0 A10 GNDQ A11 VMV0 B1 GAA2/IO95RSB1 B2 IO00RSB0 B3 GAA0/IO02RSB0 B4 GAC0/IO06RSB0 B5 IO08RSB0 B6 IO12RSB0 B7 IO16RSB0 B8 GBC1/IO20RSB0 B9 GBB0/IO21RSB0 B10 GBB2/IO27RSB0 B11 GBA2/IO25RSB0 C1 IO89RSB1 C2 GAC2/IO91RSB1 C3 GAB1/IO05RSB0 C4 GAB0/IO04RSB0 C5 IO09RSB0 C6 IO14RSB0 C7 GBA0/IO23RSB0 C8 GBC0/IO19RSB0 C9 IO26RSB0 C10 IO28RSB0 C11 GBC2/IO29RSB0 D1 IO88RSB1 D2 IO90RSB1 D3 GAB2/IO93RSB1 D4 IO10RSB0 D5 IO11RSB0 D6 IO18RSB0 D7 IO32RSB0 D8 IO31RSB0 D9 GCA2/IO41RSB0 D10 IO30RSB0 D11 IO33RSB0 E1 IO87RSB1 E2 GFC0/IO85RSB1 E3 IO92RSB1 E4 IO94RSB1 E5 VCC E6 VCCIB0 E7 GND E8 GCC0/IO36RSB0 E9 IO34RSB0 E10 GCB1/IO37RSB0 E11 GCC1/IO35RSB0 F1 VCOMPLF F2 GFB0/IO83RSB1 F3 GFA0/IO82RSB1 F4 GFC1/IO86RSB1 F5 VCCIB1 F6 VCC F7 VCCIB0 F8 GCB2/IO42RSB0 F9 GCC2/IO43RSB0 F10 GCB0/IO38RSB0 F11 GCA1/IO39RSB0 G1 VCCPLF G2 GFB2/IO79RSB1 G3 GFA1/IO81RSB1 G4 GFB1/IO84RSB1 G5 GND G6 VCCIB1 CS121 Pin Number A3P060 Function G7 VCC G8 GDC0/IO46RSB0 G9 GDA1/IO49RSB0 G10 GDB0/IO48RSB0 G11 GCA0/IO40RSB0 H1 IO75RSB1 H2 IO76RSB1 H3 GFC2/IO78RSB1 H4 GFA2/IO80RSB1 H5 IO77RSB1 H6 GEC2/IO66RSB1 H7 IO54RSB1 H8 GDC2/IO53RSB1 H9 VJTAG H10 TRST H11 IO44RSB0 J1 GEC1/IO74RSB1 J2 GEC0/IO73RSB1 J3 GEB1/IO72RSB1 J4 GEA0/IO69RSB1 J5 GEB2/IO67RSB1 J6 IO62RSB1 J7 GDA2/IO51RSB1 J8 GDB2/IO52RSB1 J9 TDI J10 TDO J11 GDC1/IO45RSB0 K1 GEB0/IO71RSB1 K2 GEA1/IO70RSB1 K3 GEA2/IO68RSB1 K4 IO64RSB1 K5 IO60RSB1 K6 IO59RSB1 K7 IO56RSB1 K8 TCK K9 TMS CS121 Pin Number A3P060 Function

ProASIC3 Flash Family FPGAs Revision 13 4-17 K10 VPUMP K11 GDB1/IO47RSB0 L1 VMV1 L2 GNDQ L3 IO65RSB1 L4 IO63RSB1 L5 IO61RSB1 L6 IO58RSB1 L7 IO57RSB1 L8 IO55RSB1 L9 GNDQ L10 GDA0/IO50RSB0 L11 VMV1 CS121 Pin Number A3P060 Function

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the top view of the package. 100

ProASIC3 Flash Family FPGAs Revision 13 4-19 VQ100 Pin Number A3P030 Function 1G N D

2 IO82RSB1

3 IO81RSB1

4 IO80RSB1

5 IO79RSB1

6 IO78RSB1

7 IO77RSB1

8 IO76RSB1

10 IO75RSB1

11 IO74RSB1

12 GEC0/IO73RSB1

13 GEA0/IO72RSB1

14 GEB0/IO71RSB1

15 IO70RSB1

16 IO69RSB1

17 VCC

18 VCCIB1

19 IO68RSB1

20 IO67RSB1

21 IO66RSB1

22 IO65RSB1

23 IO64RSB1

24 IO63RSB1

25 IO62RSB1

26 IO61RSB1

27 IO60RSB1

28 IO59RSB1

29 IO58RSB1

30 IO57RSB1

31 IO56RSB1

32 IO55RSB1

33 IO54RSB1

34 IO53RSB1

35 IO52RSB1

36 IO51RSB1

37 VCC

38 GND

39 VCCIB1

40 IO49RSB1

41 IO47RSB1

42 IO46RSB1

43 IO45RSB1

44 IO44RSB1

45 IO43RSB1

46 IO42RSB1

47 TCK

48 TDI

49 TMS

51 GND

52 VPUMP

54 TDO

55 TRST

56 VJTAG

57 IO41RSB0

58 IO40RSB0

59 IO39RSB0

60 IO38RSB0

61 IO37RSB0

62 IO36RSB0

63 GDB0/IO34RSB0

64 GDA0/IO33RSB0

65 GDC0/IO32RSB0

66 VCCIB0

67 GND

68 VCC

69 IO31RSB0

70 IO30RSB0

71 IO29RSB0

72 IO28RSB0

Pin Number A3P030 Function

73 IO27RSB0

74 IO26RSB0

75 IO25RSB0

76 IO24RSB0

77 IO23RSB0

78 IO22RSB0

79 IO21RSB0

80 IO20RSB0

81 IO19RSB0

82 IO18RSB0

83 IO17RSB0

84 IO16RSB0

85 IO15RSB0

86 IO14RSB0

87 VCCIB0

88 GND

89 VCC

90 IO12RSB0

91 IO10RSB0

92 IO08RSB0

93 IO07RSB0

94 IO06RSB0

95 IO05RSB0

96 IO04RSB0

97 IO03RSB0

98 IO02RSB0

99 IO01RSB0

100 IO00RSB0

Pin Number A3P030 Function

Pin Number A3P060 Function 1G N D

2 GAA2/IO51RSB1

3 IO52RSB1

4 GAB2/IO53RSB1

5 IO95RSB1

6 GAC2/IO94RSB1

7 IO93RSB1

8 IO92RSB1

10 GFB1/IO87RSB1

11 GFB0/IO86RSB1

12 VCOMPLF

13 GFA0/IO85RSB1

14 VCCPLF

15 GFA1/IO84RSB1

16 GFA2/IO83RSB1

19 GEC1/IO77RSB1

20 GEB1/IO75RSB1

21 GEB0/IO74RSB1

22 GEA1/IO73RSB1

23 GEA0/IO72RSB1

24 VMV1

25 GNDQ

26 GEA2/IO71RSB1

27 GEB2/IO70RSB1

28 GEC2/IO69RSB1

29 IO68RSB1

30 IO67RSB1

31 IO66RSB1

32 IO65RSB1

33 IO64RSB1

34 IO63RSB1

35 IO62RSB1

36 IO61RSB1

40 IO60RSB1

41 IO59RSB1

42 IO58RSB1

43 IO57RSB1

44 GDC2/IO56RSB1

45 GDB2/IO55RSB1

46 GDA2/IO54RSB1

50 VMV1

57 GDA1/IO49RSB0

58 GDC0/IO46RSB0

59 GDC1/IO45RSB0

60 GCC2/IO43RSB0

61 GCB2/IO42RSB0

62 GCA0/IO40RSB0

63 GCA1/IO39RSB0

64 GCC0/IO36RSB0

65 GCC1/IO35RSB0

70 GBC2/IO29RSB0

71 GBB2/IO27RSB0

72 IO26RSB0

Pin Number A3P060 Function

73 GBA2/IO25RSB0

74 VMV0

75 GNDQ

76 GBA1/IO24RSB0

77 GBA0/IO23RSB0

78 GBB1/IO22RSB0

79 GBB0/IO21RSB0

80 GBC1/IO20RSB0

81 GBC0/IO19RSB0

84 IO15RSB0

85 IO13RSB0

86 IO11RSB0

90 IO10RSB0

91 IO09RSB0

93 GAC1/IO07RSB0

94 GAC0/IO06RSB0

95 GAB1/IO05RSB0

96 GAB0/IO04RSB0

97 GAA1/IO03RSB0

98 GAA0/IO02RSB0

Pin Number A3P060 Function

ProASIC3 Flash Family FPGAs Revision 13 4-21 VQ100 Pin Number A3P125 Function 1G N D

2 GAA2/IO67RSB1

3 IO68RSB1

4 GAB2/IO69RSB1

5 IO132RSB1

6 GAC2/IO131RSB1

7 IO130RSB1

8 IO129RSB1

10 GFB1/IO124RSB1

11 GFB0/IO123RSB1

13 GFA0/IO122RSB1

15 GFA1/IO121RSB1

16 GFA2/IO120RSB1

19 GEC0/IO111RSB1

20 GEB1/IO110RSB1

21 GEB0/IO109RSB1

22 GEA1/IO108RSB1

23 GEA0/IO107RSB1

26 GEA2/IO106RSB1

27 GEB2/IO105RSB1

28 GEC2/IO104RSB1

29 IO102RSB1

30 IO100RSB1

31 IO99RSB1

32 IO97RSB1

33 IO96RSB1

34 IO95RSB1

35 IO94RSB1

36 IO93RSB1

40 IO87RSB1

41 IO84RSB1

42 IO81RSB1

43 IO75RSB1

44 GDC2/IO72RSB1

45 GDB2/IO71RSB1

46 GDA2/IO70RSB1

57 GDA1/IO65RSB0

58 GDC0/IO62RSB0

59 GDC1/IO61RSB0

60 GCC2/IO59RSB0

61 GCB2/IO58RSB0

62 GCA0/IO56RSB0

63 GCA1/IO55RSB0

64 GCC0/IO52RSB0

65 GCC1/IO51RSB0

69 IO47RSB0

70 GBC2/IO45RSB0

71 GBB2/IO43RSB0

72 IO42RSB0

Pin Number A3P125 Function

73 GBA2/IO41RSB0

76 GBA1/IO40RSB0

77 GBA0/IO39RSB0

78 GBB1/IO38RSB0

79 GBB0/IO37RSB0

80 GBC1/IO36RSB0

81 GBC0/IO35RSB0

82 IO32RSB0

83 IO28RSB0

84 IO25RSB0

85 IO22RSB0

86 IO19RSB0

90 IO15RSB0

91 IO13RSB0

92 IO11RSB0

93 IO09RSB0

94 IO07RSB0

95 GAC1/IO05RSB0

96 GAC0/IO04RSB0

97 GAB1/IO03RSB0

98 GAB0/IO02RSB0

99 GAA1/IO01RSB0

100 GAA0/IO00RSB0

Pin Number A3P125 Function

Pin Number A3P250 Function 1G N D

2 GAA2/IO118UDB3

3 IO118VDB3

4 GAB2/IO117UDB3

5 IO117VDB3

6 GAC2/IO116UDB3

7 IO116VDB3

8 IO112PSB3

10 GFB1/IO109PDB3

11 GFB0/IO109NDB3

13 GFA0/IO108NPB3

15 GFA1/IO108PPB3

16 GFA2/IO107PSB3

18 VCCIB3

19 GFC2/IO105PSB3

20 GEC1/IO100PDB3

21 GEC0/IO100NDB3

22 GEA1/IO98PDB3

23 GEA0/IO98NDB3

24 VMV3

26 GEA2/IO97RSB2

27 GEB2/IO96RSB2

28 GEC2/IO95RSB2

29 IO93RSB2

30 IO92RSB2

31 IO91RSB2

32 IO90RSB2

33 IO88RSB2

34 IO86RSB2

35 IO85RSB2

36 IO84RSB2

39 VCCIB2

40 IO77RSB2

41 IO74RSB2

42 IO71RSB2

43 GDC2/IO63RSB2

44 GDB2/IO62RSB2

45 GDA2/IO61RSB2

46 GNDQ

50 VMV2

57 GDA1/IO60USB1

58 GDC0/IO58VDB1

59 GDC1/IO58UDB1

60 IO52NDB1

61 GCB2/IO52PDB1

62 GCA1/IO50PDB1

63 GCA0/IO50NDB1

64 GCC0/IO48NDB1

65 GCC1/IO48PDB1

66 VCCIB1

69 IO43NDB1

70 GBC2/IO43PDB1

71 GBB2/IO42PSB1

72 IO41NDB1

Pin Number A3P250 Function

73 GBA2/IO41PDB1

74 VMV1

82 IO29RSB0

83 IO27RSB0

85 IO23RSB0

86 IO21RSB0

93 GAC1/IO05RSB0

94 GAC0/IO04RSB0

95 GAB1/IO03RSB0

96 GAB0/IO02RSB0

97 GAA1/IO01RSB0

98 GAA0/IO00RSB0

99 GNDQ

100 VMV0

Pin Number A3P250 Function

ProASIC3 Flash Family FPGAs Revision 13 4-23 TQ144 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the top view of the package. 144 144-Pin TQFP

Pin Number A3P060 Function

1 GAA2/IO51RSB1

2 IO52RSB1

3 GAB2/IO53RSB1

4 IO95RSB1

5 GAC2/IO94RSB1

6 IO93RSB1

7 IO92RSB1

8 IO91RSB1

10 GND

11 VCCIB1

12 IO90RSB1

13 GFC1/IO89RSB1

14 GFC0/IO88RSB1

15 GFB1/IO87RSB1

16 GFB0/IO86RSB1

17 VCOMPLF

18 GFA0/IO85RSB1

19 VCCPLF

20 GFA1/IO84RSB1

21 GFA2/IO83RSB1

22 GFB2/IO82RSB1

23 GFC2/IO81RSB1

24 IO80RSB1

25 IO79RSB1

26 IO78RSB1

27 GND

28 VCCIB1

29 GEC1/IO77RSB1

30 GEC0/IO76RSB1

31 GEB1/IO75RSB1

32 GEB0/IO74RSB1

33 GEA1/IO73RSB1

34 GEA0/IO72RSB1

35 VMV1

36 GNDQ

38 GEA2/IO71RSB1

39 GEB2/IO70RSB1

40 GEC2/IO69RSB1

41 IO68RSB1

42 IO67RSB1

43 IO66RSB1

44 IO65RSB1

45 VCC

46 GND

47 VCCIB1

49 IO64RSB1

51 IO63RSB1

53 IO62RSB1

55 IO61RSB1

58 IO60RSB1

59 IO59RSB1

60 IO58RSB1

61 IO57RSB1

63 GND

65 GDC2/IO56RSB1

66 GDB2/IO55RSB1

67 GDA2/IO54RSB1

68 GNDQ

69 TCK

70 TDI

71 TMS

72 VMV1

Pin Number A3P060 Function

73 VPUMP

75 TDO

76 TRST

77 VJTAG

78 GDA0/IO50RSB0

79 GDB0/IO48RSB0

80 GDB1/IO47RSB0

81 VCCIB0

82 GND

83 IO44RSB0

84 GCC2/IO43RSB0

85 GCB2/IO42RSB0

86 GCA2/IO41RSB0

87 GCA0/IO40RSB0

88 GCA1/IO39RSB0

89 GCB0/IO38RSB0

90 GCB1/IO37RSB0

91 GCC0/IO36RSB0

92 GCC1/IO35RSB0

93 IO34RSB0

94 IO33RSB0

98 VCCIB0

99 GND

100 VCC

101 IO30RSB0

102 GBC2/IO29RSB0

103 IO28RSB0

104 GBB2/IO27RSB0

105 IO26RSB0

106 GBA2/IO25RSB0

107 VMV0

108 GNDQ

Pin Number A3P060 Function

ProASIC3 Flash Family FPGAs Revision 13 4-25 109 NC 110 NC

111 GBA1/IO24RSB0

112 GBA0/IO23RSB0

113 GBB1/IO22RSB0

114 GBB0/IO21RSB0

115 GBC1/IO20RSB0

116 GBC0/IO19RSB0

117 VCCIB0

118 GND

119 VCC

120 IO18RSB0

121 IO17RSB0

122 IO16RSB0

123 IO15RSB0

124 IO14RSB0

125 IO13RSB0

126 IO12RSB0

127 IO11RSB0

129 IO10RSB0

130 IO09RSB0

131 IO08RSB0

132 GAC1/IO07RSB0

133 GAC0/IO06RSB0

135 GND

137 GAB1/IO05RSB0

138 GAB0/IO04RSB0

139 GAA1/IO03RSB0

140 GAA0/IO02RSB0

141 IO01RSB0

142 IO00RSB0

143 GNDQ

144 VMV0

Pin Number A3P060 Function

Pin Number A3P125 Function

1 GAA2/IO67RSB1

2 IO68RSB1

3 GAB2/IO69RSB1

4 IO132RSB1

5 GAC2/IO131RSB1

6 IO130RSB1

7 IO129RSB1

8 IO128RSB1

12 IO127RSB1

13 GFC1/IO126RSB1

14 GFC0/IO125RSB1

15 GFB1/IO124RSB1

16 GFB0/IO123RSB1

18 GFA0/IO122RSB1

20 GFA1/IO121RSB1

21 GFA2/IO120RSB1

22 GFB2/IO119RSB1

23 GFC2/IO118RSB1

24 IO117RSB1

25 IO116RSB1

26 IO115RSB1

29 GEC1/IO112RSB1

30 GEC0/IO111RSB1

31 GEB1/IO110RSB1

32 GEB0/IO109RSB1

33 GEA1/IO108RSB1

34 GEA0/IO107RSB1

38 GEA2/IO106RSB1

39 GEB2/IO105RSB1

40 GEC2/IO104RSB1

41 IO103RSB1

42 IO102RSB1

43 IO101RSB1

44 IO100RSB1

48 IO99RSB1

49 IO97RSB1

50 IO95RSB1

51 IO93RSB1

52 IO92RSB1

53 IO90RSB1

54 IO88RSB1

55 IO86RSB1

56 IO84RSB1

57 IO83RSB1

58 IO82RSB1

59 IO81RSB1

60 IO80RSB1

61 IO79RSB1

62 VCC

64 VCCIB1

65 GDC2/IO72RSB1

66 GDB2/IO71RSB1

67 GDA2/IO70RSB1

Pin Number A3P125 Function

78 GDA0/IO66RSB0

79 GDB0/IO64RSB0

80 GDB1/IO63RSB0

83 IO60RSB0

84 GCC2/IO59RSB0

85 GCB2/IO58RSB0

86 GCA2/IO57RSB0

87 GCA0/IO56RSB0

88 GCA1/IO55RSB0

89 GCB0/IO54RSB0

90 GCB1/IO53RSB0

91 GCC0/IO52RSB0

92 GCC1/IO51RSB0

93 IO50RSB0

94 IO49RSB0

101 IO47RSB0

102 GBC2/IO45RSB0

103 IO44RSB0

104 GBB2/IO43RSB0

105 IO42RSB0

106 GBA2/IO41RSB0

Pin Number A3P125 Function

ProASIC3 Flash Family FPGAs Revision 13 4-27

109 GBA1/IO40RSB0

110 GBA0/IO39RSB0

111 GBB1/IO38RSB0

112 GBB0/IO37RSB0

113 GBC1/IO36RSB0

114 GBC0/IO35RSB0

115 IO34RSB0

116 IO33RSB0

120 IO29RSB0

121 IO28RSB0

122 IO27RSB0

123 IO25RSB0

124 IO23RSB0

125 IO21RSB0

126 IO19RSB0

127 IO17RSB0

128 IO16RSB0

129 IO14RSB0

130 IO12RSB0

131 IO10RSB0

132 IO08RSB0

133 IO06RSB0

134 VCCIB0

136 VCC

137 GAC1/IO05RSB0

138 GAC0/IO04RSB0

139 GAB1/IO03RSB0

140 GAB0/IO02RSB0

141 GAA1/IO01RSB0

142 GAA0/IO00RSB0

Pin Number A3P125 Function

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the top view of the package. 208-Pin PQFP 1 208

ProASIC3 Flash Family FPGAs Revision 13 4-29 PQ208 Pin Number A3P125 Function 1G N D

9 IO130RSB1

10 IO129RSB1

12 IO128RSB1

16 VCC

17 GND

19 IO127RSB1

21 GFC1/IO126RSB1

22 GFC0/IO125RSB1

23 GFB1/IO124RSB1

24 GFB0/IO123RSB1

25 VCOMPLF

26 GFA0/IO122RSB1

27 VCCPLF

28 GFA1/IO121RSB1

29 GND

30 GFA2/IO120RSB1

32 GFB2/IO119RSB1

34 GFC2/IO118RSB1

35 IO117RSB1

37 IO116RSB1

38 IO115RSB1

40 VCCIB1

41 GND

42 IO114RSB1

43 IO113RSB1

44 GEC1/IO112RSB1

45 GEC0/IO111RSB1

46 GEB1/IO110RSB1

47 GEB0/IO109RSB1

48 GEA1/IO108RSB1

49 GEA0/IO107RSB1

51 GNDQ

52 GND

55 GEA2/IO106RSB1

56 GEB2/IO105RSB1

57 GEC2/IO104RSB1

58 IO103RSB1

59 IO102RSB1

60 IO101RSB1

61 IO100RSB1

62 VCCIB1

63 IO99RSB1

64 IO98RSB1

65 GND

66 IO97RSB1

67 IO96RSB1

68 IO95RSB1

69 IO94RSB1

70 IO93RSB1

71 VCC

72 VCCIB1

Pin Number A3P125 Function

73 IO92RSB1

74 IO91RSB1

75 IO90RSB1

76 IO89RSB1

77 IO88RSB1

78 IO87RSB1

79 IO86RSB1

80 IO85RSB1

81 GND

82 IO84RSB1

83 IO83RSB1

84 IO82RSB1

85 IO81RSB1

86 IO80RSB1

87 IO79RSB1

88 VCC

89 VCCIB1

90 IO78RSB1

91 IO77RSB1

92 IO76RSB1

93 IO75RSB1

94 IO74RSB1

95 IO73RSB1

96 GDC2/IO72RSB1

97 GND

98 GDB2/IO71RSB1

99 GDA2/IO70RSB1

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV1

105 GND

106 VPUMP

108 TDO

Pin Number A3P125 Function

109 TRST

110 VJTAG

111 GDA0/IO66RSB0

112 GDA1/IO65RSB0

113 GDB0/IO64RSB0

114 GDB1/IO63RSB0

115 GDC0/IO62RSB0

116 GDC1/IO61RSB0

122 GND

123 VCCIB0

126 VCC

127 IO60RSB0

128 GCC2/IO59RSB0

129 GCB2/IO58RSB0

130 GND

131 GCA2/IO57RSB0

132 GCA0/IO56RSB0

133 GCA1/IO55RSB0

134 GCB0/IO54RSB0

135 GCB1/IO53RSB0

136 GCC0/IO52RSB0

137 GCC1/IO51RSB0

138 IO50RSB0

139 IO49RSB0

140 VCCIB0

141 GND

142 VCC

143 IO48RSB0

144 IO47RSB0

Pin Number A3P125 Function

145 IO46RSB0

149 GBC2/IO45RSB0

150 IO44RSB0

151 GBB2/IO43RSB0

152 IO42RSB0

153 GBA2/IO41RSB0

154 VMV0

155 GNDQ

156 GND

158 GBA1/IO40RSB0

159 GBA0/IO39RSB0

160 GBB1/IO38RSB0

161 GBB0/IO37RSB0

162 GND

163 GBC1/IO36RSB0

164 GBC0/IO35RSB0

165 IO34RSB0

166 IO33RSB0

167 IO32RSB0

168 IO31RSB0

169 IO30RSB0

170 VCCIB0

171 VCC

172 IO29RSB0

173 IO28RSB0

174 IO27RSB0

175 IO26RSB0

176 IO25RSB0

177 IO24RSB0

178 GND

179 IO23RSB0

180 IO22RSB0

Pin Number A3P125 Function

181 IO21RSB0

182 IO20RSB0

183 IO19RSB0

184 IO18RSB0

185 IO17RSB0

186 VCCIB0

187 VCC

188 IO16RSB0

189 IO15RSB0

190 IO14RSB0

191 IO13RSB0

192 IO12RSB0

193 IO11RSB0

194 IO10RSB0

195 GND

196 IO09RSB0

197 IO08RSB0

198 IO07RSB0

199 IO06RSB0

200 VCCIB0

201 GAC1/IO05RSB0

202 GAC0/IO04RSB0

203 GAB1/IO03RSB0

204 GAB0/IO02RSB0

205 GAA1/IO01RSB0

206 GAA0/IO00RSB0

207 GNDQ

208 VMV0

Pin Number A3P125 Function

ProASIC3 Flash Family FPGAs Revision 13 4-31 PQ208 Pin Number A3P250 Function 1G N D

8 IO115UDB3

9 IO115VDB3

10 IO114UDB3

11 IO114VDB3

12 IO113PDB3

13 IO113NDB3

14 IO112PDB3

15 IO112NDB3

19 IO111PDB3

20 IO111NDB3

21 GFC1/IO110PDB3

22 GFC0/IO110NDB3

23 GFB1/IO109PDB3

24 GFB0/IO109NDB3

26 GFA0/IO108NPB3

28 GFA1/IO108PPB3

30 GFA2/IO107PDB3

31 IO107NDB3

32 GFB2/IO106PDB3

33 IO106NDB3

34 GFC2/IO105PDB3

35 IO105NDB3

37 IO104PDB3

38 IO104NDB3

39 IO103PSB3

40 VCCIB3

42 IO101PDB3

43 IO101NDB3

44 GEC1/IO100PDB3

45 GEC0/IO100NDB3

46 GEB1/IO99PDB3

47 GEB0/IO99NDB3

48 GEA1/IO98PDB3

49 GEA0/IO98NDB3

50 VMV3

55 GEA2/IO97RSB2

56 GEB2/IO96RSB2

57 GEC2/IO95RSB2

58 IO94RSB2

59 IO93RSB2

60 IO92RSB2

61 IO91RSB2

62 VCCIB2

63 IO90RSB2

64 IO89RSB2

66 IO88RSB2

67 IO87RSB2

68 IO86RSB2

69 IO85RSB2

70 IO84RSB2

72 VCCIB2

Pin Number A3P250 Function

73 IO83RSB2

74 IO82RSB2

75 IO81RSB2

76 IO80RSB2

77 IO79RSB2

78 IO78RSB2

79 IO77RSB2

80 IO76RSB2

82 IO75RSB2

83 IO74RSB2

84 IO73RSB2

85 IO72RSB2

86 IO71RSB2

87 IO70RSB2

89 VCCIB2

90 IO69RSB2

91 IO68RSB2

92 IO67RSB2

93 IO66RSB2

94 IO65RSB2

95 IO64RSB2

96 GDC2/IO63RSB2

98 GDB2/IO62RSB2

99 GDA2/IO61RSB2

104 VMV2

Pin Number A3P250 Function

111 GDA0/IO60VDB1

112 GDA1/IO60UDB1

113 GDB0/IO59VDB1

114 GDB1/IO59UDB1

115 GDC0/IO58VDB1

116 GDC1/IO58UDB1

117 IO57VDB1

118 IO57UDB1

119 IO56NDB1

120 IO56PDB1

121 IO55RSB1

123 VCCIB1

127 IO53NDB1

128 GCC2/IO53PDB1

129 GCB2/IO52PSB1

131 GCA2/IO51PSB1

132 GCA1/IO50PDB1

133 GCA0/IO50NDB1

134 GCB0/IO49NDB1

135 GCB1/IO49PDB1

136 GCC0/IO48NDB1

137 GCC1/IO48PDB1

138 IO47NDB1

139 IO47PDB1

140 VCCIB1

143 IO46RSB1

144 IO45NDB1

Pin Number A3P250 Function

145 IO45PDB1

146 IO44NDB1

147 IO44PDB1

148 IO43NDB1

149 GBC2/IO43PDB1

150 IO42NDB1

151 GBB2/IO42PDB1

152 IO41NDB1

153 GBA2/IO41PDB1

154 VMV1

Pin Number A3P250 Function Pin Number A3P250 Function

ProASIC3 Flash Family FPGAs Revision 13 4-33 PQ208 Pin Number A3P400 Function 1G N D

2 GAA2/IO155UDB3

3 IO155VDB3

4 GAB2/IO154UDB3

5 IO154VDB3

6 GAC2/IO153UDB3

7 IO153VDB3

8 IO152UDB3

9 IO152VDB3

10 IO151UDB3

11 IO151VDB3

12 IO150PDB3

13 IO150NDB3

14 IO149PDB3

15 IO149NDB3

19 IO148PDB3

20 IO148NDB3

21 GFC1/IO147PDB3

22 GFC0/IO147NDB3

23 GFB1/IO146PDB3

24 GFB0/IO146NDB3

26 GFA0/IO145NPB3

28 GFA1/IO145PPB3

30 GFA2/IO144PDB3

31 IO144NDB3

32 GFB2/IO143PDB3

33 IO143NDB3

34 GFC2/IO142PDB3

35 IO142NDB3

37 IO141PSB3

38 IO140PDB3

39 IO140NDB3

42 IO138PDB3

43 IO138NDB3

44 GEC1/IO137PDB3

45 GEC0/IO137NDB3

46 GEB1/IO136PDB3

47 GEB0/IO136NDB3

48 GEA1/IO135PDB3

49 GEA0/IO135NDB3

53 VMV2

55 GEA2/IO134RSB2

56 GEB2/IO133RSB2

57 GEC2/IO132RSB2

58 IO131RSB2

59 IO130RSB2

60 IO129RSB2

61 IO128RSB2

63 IO125RSB2

64 IO123RSB2

66 IO121RSB2

67 IO119RSB2

68 IO117RSB2

69 IO115RSB2

70 IO113RSB2

Pin Number A3P400 Function

73 IO112RSB2

74 IO111RSB2

75 IO110RSB2

76 IO109RSB2

77 IO108RSB2

78 IO107RSB2

79 IO106RSB2

80 IO104RSB2

82 IO102RSB2

83 IO101RSB2

84 IO100RSB2

85 IO99RSB2

86 IO98RSB2

87 IO97RSB2

90 IO94RSB2

91 IO92RSB2

92 IO90RSB2

93 IO88RSB2

94 IO86RSB2

95 IO84RSB2

96 GDC2/IO82RSB2

98 GDB2/IO81RSB2

99 GDA2/IO80RSB2

Pin Number A3P400 Function

111 GDA0/IO79VDB1

112 GDA1/IO79UDB1

113 GDB0/IO78VDB1

114 GDB1/IO78UDB1

115 GDC0/IO77VDB1

116 GDC1/IO77UDB1

117 IO76VDB1

118 IO76UDB1

119 IO75NDB1

120 IO75PDB1

121 IO74RSB1

127 IO72NDB1

128 GCC2/IO72PDB1

129 GCB2/IO71PSB1

131 GCA2/IO70PSB1

132 GCA1/IO69PDB1

133 GCA0/IO69NDB1

134 GCB0/IO68NDB1

135 GCB1/IO68PDB1

136 GCC0/IO67NDB1

137 GCC1/IO67PDB1

138 IO66NDB1

139 IO66PDB1

143 IO65RSB1

144 IO64NDB1

Pin Number A3P400 Function

145 IO64PDB1

146 IO63NDB1

147 IO63PDB1

148 IO62NDB1

149 GBC2/IO62PDB1

150 IO61NDB1

151 GBB2/IO61PDB1

152 IO60NDB1

153 GBA2/IO60PDB1

157 VMV0

158 GBA1/IO59RSB0

159 GBA0/IO58RSB0

160 GBB1/IO57RSB0

161 GBB0/IO56RSB0

163 GBC1/IO55RSB0

164 GBC0/IO54RSB0

165 IO52RSB0

166 IO49RSB0

167 IO46RSB0

168 IO43RSB0

169 IO40RSB0

172 IO36RSB0

173 IO35RSB0

174 IO34RSB0

175 IO33RSB0

176 IO32RSB0

177 IO31RSB0

179 IO29RSB0

180 IO28RSB0

Pin Number A3P400 Function

181 IO27RSB0

182 IO26RSB0

183 IO25RSB0

184 IO24RSB0

185 IO23RSB0

188 IO21RSB0

189 IO20RSB0

190 IO19RSB0

191 IO18RSB0

192 IO17RSB0

193 IO16RSB0

194 IO15RSB0

196 IO13RSB0

197 IO11RSB0

198 IO09RSB0

199 IO07RSB0

Pin Number A3P400 Function

ProASIC3 Flash Family FPGAs Revision 13 4-35 PQ208 Pin Number A3P600 Function 1G N D

2 GAA2/IO174PDB3

3 IO174NDB3

4 GAB2/IO173PDB3

5 IO173NDB3

6 GAC2/IO172PDB3

7 IO172NDB3

8 IO171PDB3

9 IO171NDB3

10 IO170PDB3

11 IO170NDB3

12 IO169PDB3

13 IO169NDB3

14 IO168PDB3

15 IO168NDB3

19 IO166PDB3

20 IO166NDB3

21 GFC1/IO164PDB3

22 GFC0/IO164NDB3

23 GFB1/IO163PDB3

24 GFB0/IO163NDB3

26 GFA0/IO162NPB3

28 GFA1/IO162PPB3

30 GFA2/IO161PDB3

31 IO161NDB3

32 GFB2/IO160PDB3

33 IO160NDB3

34 GFC2/IO159PDB3

35 IO159NDB3

36 VCC

37 IO152PDB3

38 IO152NDB3

39 IO150PSB3

42 IO147PDB3

43 IO147NDB3

44 GEC1/IO146PDB3

45 GEC0/IO146NDB3

46 GEB1/IO145PDB3

47 GEB0/IO145NDB3

48 GEA1/IO144PDB3

49 GEA0/IO144NDB3

54 GEA2/IO143RSB2

55 GEB2/IO142RSB2

56 GEC2/IO141RSB2

57 IO140RSB2

58 IO139RSB2

59 IO138RSB2

60 IO137RSB2

61 IO136RSB2

63 IO135RSB2

64 IO133RSB2

66 IO131RSB2

67 IO129RSB2

68 IO127RSB2

69 IO125RSB2

70 IO123RSB2

Pin Number A3P600 Function

73 IO120RSB2

74 IO119RSB2

75 IO118RSB2

76 IO117RSB2

77 IO116RSB2

78 IO115RSB2

79 IO114RSB2

80 IO112RSB2

82 IO111RSB2

83 IO110RSB2

84 IO109RSB2

85 IO108RSB2

86 IO107RSB2

87 IO106RSB2

90 IO104RSB2

91 IO102RSB2

92 IO100RSB2

93 IO98RSB2

94 IO96RSB2

95 IO92RSB2

96 GDC2/IO91RSB2

98 GDB2/IO90RSB2

99 GDA2/IO89RSB2

107 GNDQ

Pin Number A3P600 Function

111 GDA0/IO88NDB1

112 GDA1/IO88PDB1

113 GDB0/IO87NDB1

114 GDB1/IO87PDB1

115 GDC0/IO86NDB1

116 GDC1/IO86PDB1

117 IO84NDB1

118 IO84PDB1

119 IO82NDB1

120 IO82PDB1

121 IO81PSB1

124 IO77NDB1

125 IO77PDB1

127 IO74NDB1

128 GCC2/IO74PDB1

129 GCB2/IO73PSB1

131 GCA2/IO72PSB1

132 GCA1/IO71PDB1

133 GCA0/IO71NDB1

134 GCB0/IO70NDB1

135 GCB1/IO70PDB1

136 GCC0/IO69NDB1

137 GCC1/IO69PDB1

138 IO67NDB1

139 IO67PDB1

143 IO65PSB1

Pin Number A3P600 Function

166 IO50RSB0

167 IO48RSB0

168 IO46RSB0

169 IO44RSB0

Pin Number A3P600 Function

188 IO20RSB0

189 IO19RSB0

190 IO18RSB0

191 IO17RSB0

192 IO16RSB0

193 IO14RSB0

194 IO12RSB0

196 IO10RSB0

197 IO09RSB0

198 IO08RSB0

Pin Number A3P600 Function

ProASIC3 Flash Family FPGAs Revision 13 4-37 PQ208 Pin Number A3P1000 Function 1G N D

2 GAA2/IO225PDB3

3 IO225NDB3

4 GAB2/IO224PDB3

5 IO224NDB3

6 GAC2/IO223PDB3

7 IO223NDB3

8 IO222PDB3

9 IO222NDB3

10 IO220PDB3

11 IO220NDB3

12 IO218PDB3

13 IO218NDB3

14 IO216PDB3

15 IO216NDB3

19 IO212PDB3

20 IO212NDB3

21 GFC1/IO209PDB3

22 GFC0/IO209NDB3

23 GFB1/IO208PDB3

24 GFB0/IO208NDB3

26 GFA0/IO207NPB3

28 GFA1/IO207PPB3

30 GFA2/IO206PDB3

31 IO206NDB3

32 GFB2/IO205PDB3

33 IO205NDB3

34 GFC2/IO204PDB3

35 IO204NDB3

37 IO199PDB3

38 IO199NDB3

39 IO197PSB3

42 IO191PDB3

43 IO191NDB3

44 GEC1/IO190PDB3

45 GEC0/IO190NDB3

46 GEB1/IO189PDB3

47 GEB0/IO189NDB3

48 GEA1/IO188PDB3

49 GEA0/IO188NDB3

54 GEA2/IO187RSB2

55 GEB2/IO186RSB2

56 GEC2/IO185RSB2

57 IO184RSB2

58 IO183RSB2

59 IO182RSB2

60 IO181RSB2

61 IO180RSB2

63 IO178RSB2

64 IO176RSB2

66 IO174RSB2

67 IO172RSB2

68 IO170RSB2

69 IO168RSB2

70 IO166RSB2

Pin Number A3P1000 Function

73 IO162RSB2

74 IO160RSB2

75 IO158RSB2

76 IO156RSB2

77 IO154RSB2

78 IO152RSB2

79 IO150RSB2

80 IO148RSB2

82 IO143RSB2

83 IO141RSB2

84 IO139RSB2

85 IO137RSB2

86 IO135RSB2

87 IO133RSB2

90 IO128RSB2

91 IO126RSB2

92 IO124RSB2

93 IO122RSB2

94 IO120RSB2

95 IO118RSB2

96 GDC2/IO116RSB2

98 GDB2/IO115RSB2

99 GDA2/IO114RSB2

Pin Number A3P1000 Function

111 GDA0/IO113NDB1

112 GDA1/IO113PDB1

113 GDB0/IO112NDB1

114 GDB1/IO112PDB1

115 GDC0/IO111NDB1

116 GDC1/IO111PDB1

117 IO109NDB1

118 IO109PDB1

119 IO106NDB1

120 IO106PDB1

121 IO104PSB1

124 IO99NDB1

125 IO99PDB1

127 IO96NDB1

128 GCC2/IO96PDB1

129 GCB2/IO95PSB1

131 GCA2/IO94PSB1

132 GCA1/IO93PDB1

133 GCA0/IO93NDB1

134 GCB0/IO92NDB1

135 GCB1/IO92PDB1

136 GCC0/IO91NDB1

137 GCC1/IO91PDB1

138 IO88NDB1

139 IO88PDB1

143 IO86PSB1

144 IO84NDB1

Pin Number A3P1000 Function

145 IO84PDB1

146 IO82NDB1

147 IO82PDB1

148 IO80NDB1

149 GBC2/IO80PDB1

150 IO79NDB1

151 GBB2/IO79PDB1

152 IO78NDB1

153 GBA2/IO78PDB1

158 GBA1/IO77RSB0

159 GBA0/IO76RSB0

160 GBB1/IO75RSB0

161 GBB0/IO74RSB0

163 GBC1/IO73RSB0

164 GBC0/IO72RSB0

165 IO70RSB0

166 IO67RSB0

167 IO63RSB0

168 IO60RSB0

169 IO57RSB0

172 IO54RSB0

173 IO51RSB0

174 IO48RSB0

175 IO45RSB0

176 IO42RSB0

177 IO40RSB0

179 IO38RSB0

180 IO35RSB0

Pin Number A3P1000 Function

181 IO33RSB0

182 IO31RSB0

183 IO29RSB0

184 IO27RSB0

185 IO25RSB0

188 IO22RSB0

191 IO16RSB0

192 IO15RSB0

194 IO13RSB0

196 IO12RSB0

198 IO10RSB0

199 IO09RSB0

Pin Number A3P1000 Function

ProASIC3 Flash Family FPGAs Revision 13 4-39 FG144 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. 123456789101112 A B C D E F G H J K L M A1 Ball Pad Corner

Pin Number A3P060 Function A1 GNDQ A2 VMV0 A3 GAB0/IO04RSB0 A4 GAB1/IO05RSB0 A5 IO08RSB0 A6 GND A7 IO11RSB0 A8 VCC A9 IO16RSB0 A10 GBA0/IO23RSB0 A11 GBA1/IO24RSB0 A12 GNDQ B1 GAB2/IO53RSB1 B2 GND B3 GAA0/IO02RSB0 B4 GAA1/IO03RSB0 B5 IO00RSB0 B6 IO10RSB0 B7 IO12RSB0 B8 IO14RSB0 B9 GBB0/IO21RSB0 B10 GBB1/IO22RSB0 B11 GND B12 VMV0 C1 IO95RSB1 C2 GFA2/IO83RSB1 C3 GAC2/IO94RSB1 C4 VCC C5 IO01RSB0 C6 IO09RSB0 C7 IO13RSB0 C8 IO15RSB0 C9 IO17RSB0 C10 GBA2/IO25RSB0 C11 IO26RSB0 C12 GBC2/IO29RSB0 D1 IO91RSB1 D2 IO92RSB1 D3 IO93RSB1 D4 GAA2/IO51RSB1 D5 GAC0/IO06RSB0 D6 GAC1/IO07RSB0 D7 GBC0/IO19RSB0 D8 GBC1/IO20RSB0 D9 GBB2/IO27RSB0 D10 IO18RSB0 D11 IO28RSB0 D12 GCB1/IO37RSB0 E1 VCC E2 GFC0/IO88RSB1 E3 GFC1/IO89RSB1 E4 VCCIB1 E5 IO52RSB1 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO35RSB0 E9 VCCIB0 E10 VCC E11 GCA0/IO40RSB0 E12 IO30RSB0 F1 GFB0/IO86RSB1 F2 VCOMPLF F3 GFB1/IO87RSB1 F4 IO90RSB1 F5 GND F6 GND F7 GND F8 GCC0/IO36RSB0 F9 GCB0/IO38RSB0 F10 GND F11 GCA1/IO39RSB0 F12 GCA2/IO41RSB0 FG144 Pin Number A3P060 Function G1 GFA1/IO84RSB1 G2 GND G3 VCCPLF G4 GFA0/IO85RSB1 G5 GND G6 GND G7 GND G8 GDC1/IO45RSB0 G9 IO32RSB0 G10 GCC2/IO43RSB0 G11 IO31RSB0 G12 GCB2/IO42RSB0 H1 VCC H2 GFB2/IO82RSB1 H3 GFC2/IO81RSB1 H4 GEC1/IO77RSB1 H5 VCC H6 IO34RSB0 H7 IO44RSB0 H8 GDB2/IO55RSB1 H9 GDC0/IO46RSB0 H10 VCCIB0 H11 IO33RSB0 H12 VCC J1 GEB1/IO75RSB1 J2 IO78RSB1 J3 VCCIB1 J4 GEC0/IO76RSB1 J5 IO79RSB1 J6 IO80RSB1 J7 VCC J8 TCK J9 GDA2/IO54RSB1 J10 TDO J11 GDA1/IO49RSB0 J12 GDB1/IO47RSB0 FG144 Pin Number A3P060 Function

ProASIC3 Flash Family FPGAs Revision 13 4-41 K1 GEB0/IO74RSB1 K2 GEA1/IO73RSB1 K3 GEA0/IO72RSB1 K4 GEA2/IO71RSB1 K5 IO65RSB1 K6 IO64RSB1 K7 GND K8 IO57RSB1 K9 GDC2/IO56RSB1 K10 GND K11 GDA0/IO50RSB0 K12 GDB0/IO48RSB0 L1 GND L2 VMV1 L3 GEB2/IO70RSB1 L4 IO67RSB1 L5 VCCIB1 L6 IO62RSB1 L7 IO59RSB1 L8 IO58RSB1 L9 TMS L10 VJTAG L11 VMV1 L12 TRST M1 GNDQ M2 GEC2/IO69RSB1 M3 IO68RSB1 M4 IO66RSB1 M5 IO63RSB1 M6 IO61RSB1 M7 IO60RSB1 M8 NC M9 TDI M10 VCCIB1 M11 VPUMP M12 GNDQ FG144 Pin Number A3P060 Function

Pin Number A3P125 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO11RSB0 A6 GND A7 IO18RSB0 A8 VCC A9 IO25RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO69RSB1 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO08RSB0 B6 IO14RSB0 B7 IO19RSB0 B8 IO22RSB0 B9 GBB0/IO37RSB0 B10 GBB1/IO38RSB0 B11 GND B12 VMV0 C1 IO132RSB1 C2 GFA2/IO120RSB1 C3 GAC2/IO131RSB1 C4 VCC C5 IO10RSB0 C6 IO12RSB0 C7 IO21RSB0 C8 IO24RSB0 C9 IO27RSB0 C10 GBA2/IO41RSB0 C11 IO42RSB0 C12 GBC2/IO45RSB0 D1 IO128RSB1 D2 IO129RSB1 D3 IO130RSB1 D4 GAA2/IO67RSB1 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO35RSB0 D8 GBC1/IO36RSB0 D9 GBB2/IO43RSB0 D10 IO28RSB0 D11 IO44RSB0 D12 GCB1/IO53RSB0 E1 VCC E2 GFC0/IO125RSB1 E3 GFC1/IO126RSB1 E4 VCCIB1 E5 IO68RSB1 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO51RSB0 E9 VCCIB0 E10 VCC E11 GCA0/IO56RSB0 E12 IO46RSB0 F1 GFB0/IO123RSB1 F2 VCOMPLF F3 GFB1/IO124RSB1 F4 IO127RSB1 F5 GND F6 GND F7 GND F8 GCC0/IO52RSB0 F9 GCB0/IO54RSB0 F10 GND F11 GCA1/IO55RSB0 F12 GCA2/IO57RSB0 FG144 Pin Number A3P125 Function G1 GFA1/IO121RSB1 G2 GND G3 VCCPLF G4 GFA0/IO122RSB1 G5 GND G6 GND G7 GND G8 GDC1/IO61RSB0 G9 IO48RSB0 G10 GCC2/IO59RSB0 G11 IO47RSB0 G12 GCB2/IO58RSB0 H1 VCC H2 GFB2/IO119RSB1 H3 GFC2/IO118RSB1 H4 GEC1/IO112RSB1 H5 VCC H6 IO50RSB0 H7 IO60RSB0 H8 GDB2/IO71RSB1 H9 GDC0/IO62RSB0 H10 VCCIB0 H11 IO49RSB0 H12 VCC J1 GEB1/IO110RSB1 J2 IO115RSB1 J3 VCCIB1 J4 GEC0/IO111RSB1 J5 IO116RSB1 J6 IO117RSB1 J7 VCC J8 TCK J9 GDA2/IO70RSB1 J10 TDO J11 GDA1/IO65RSB0 J12 GDB1/IO63RSB0 FG144 Pin Number A3P125 Function

ProASIC3 Flash Family FPGAs Revision 13 4-43 K1 GEB0/IO109RSB1 K2 GEA1/IO108RSB1 K3 GEA0/IO107RSB1 K4 GEA2/IO106RSB1 K5 IO100RSB1 K6 IO98RSB1 K7 GND K8 IO73RSB1 K9 GDC2/IO72RSB1 K10 GND K11 GDA0/IO66RSB0 K12 GDB0/IO64RSB0 L1 GND L2 VMV1 L3 GEB2/IO105RSB1 L4 IO102RSB1 L5 VCCIB1 L6 IO95RSB1 L7 IO85RSB1 L8 IO74RSB1 L9 TMS L10 VJTAG L11 VMV1 L12 TRST M1 GNDQ M2 GEC2/IO104RSB1 M3 IO103RSB1 M4 IO101RSB1 M5 IO97RSB1 M6 IO94RSB1 M7 IO86RSB1 M8 IO75RSB1 M9 TDI M10 VCCIB1 M11 VPUMP M12 GNDQ FG144 Pin Number A3P125 Function

Pin Number A3P250 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO29RSB0 A8 VCC A9 IO33RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO117UDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO14RSB0 B6 IO19RSB0 B7 IO22RSB0 B8 IO30RSB0 B9 GBB0/IO37RSB0 B10 GBB1/IO38RSB0 B11 GND B12 VMV1 C1 IO117VDB3 C2 GFA2/IO107PPB3 C3 GAC2/IO116UDB3 C4 VCC C5 IO12RSB0 C6 IO17RSB0 C7 IO24RSB0 C8 IO31RSB0 C9 IO34RSB0 C10 GBA2/IO41PDB1 C11 IO41NDB1 C12 GBC2/IO43PPB1 D1 IO112NDB3 D2 IO112PDB3 D3 IO116VDB3 D4 GAA2/IO118UPB3 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO35RSB0 D8 GBC1/IO36RSB0 D9 GBB2/IO42PDB1 D10 IO42NDB1 D11 IO43NPB1 D12 GCB1/IO49PPB1 E1 VCC E2 GFC0/IO110NDB3 E3 GFC1/IO110PDB3 E4 VCCIB3 E5 IO118VPB3 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO48PDB1 E9 VCCIB1 E10 VCC E11 GCA0/IO50NDB1 E12 IO51NDB1 F1 GFB0/IO109NPB3 F2 VCOMPLF F3 GFB1/IO109PPB3 F4 IO107NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO48NDB1 F9 GCB0/IO49NPB1 F10 GND F11 GCA1/IO50PDB1 F12 GCA2/IO51PDB1 FG144 Pin Number A3P250 Function G1 GFA1/IO108PPB3 G2 GND G3 VCCPLF G4 GFA0/IO108NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO58UPB1 G9 IO53NDB1 G10 GCC2/IO53PDB1 G11 IO52NDB1 G12 GCB2/IO52PDB1 H1 VCC H2 GFB2/IO106PDB3 H3 GFC2/IO105PSB3 H4 GEC1/IO100PDB3 H5 VCC H6 IO79RSB2 H7 IO65RSB2 H8 GDB2/IO62RSB2 H9 GDC0/IO58VPB1 H10 VCCIB1 H11 IO54PSB1 H12 VCC J1 GEB1/IO99PDB3 J2 IO106NDB3 J3 VCCIB3 J4 GEC0/IO100NDB3 J5 IO88RSB2 J6 IO81RSB2 J7 VCC J8 TCK J9 GDA2/IO61RSB2 J10 TDO J11 GDA1/IO60UDB1 J12 GDB1/IO59UDB1 FG144 Pin Number A3P250 Function

ProASIC3 Flash Family FPGAs Revision 13 4-45 K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 GEB2/IO96RSB2 L4 IO91RSB2 L5 VCCIB2 L6 IO82RSB2 L7 IO80RSB2 L8 IO72RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO95RSB2 M3 IO92RSB2 M4 IO89RSB2 M5 IO87RSB2 M6 IO85RSB2 M7 IO78RSB2 M8 IO76RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ FG144 Pin Number A3P250 Function

Pin Number A3P400 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO30RSB0 A8 VCC A9 IO34RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO154UDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO14RSB0 B6 IO19RSB0 B7 IO23RSB0 B8 IO31RSB0 B9 GBB0/IO56RSB0 B10 GBB1/IO57RSB0 B11 GND B12 VMV1 C1 IO154VDB3 C2 GFA2/IO144PPB3 C3 GAC2/IO153UDB3 C4 VCC C5 IO12RSB0 C6 IO17RSB0 C7 IO25RSB0 C8 IO32RSB0 C9 IO53RSB0 C10 GBA2/IO60PDB1 C11 IO60NDB1 C12 GBC2/IO62PPB1 D1 IO149NDB3 D2 IO149PDB3 D3 IO153VDB3 D4 GAA2/IO155UPB3 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO54RSB0 D8 GBC1/IO55RSB0 D9 GBB2/IO61PDB1 D10 IO61NDB1 D11 IO62NPB1 D12 GCB1/IO68PPB1 E1 VCC E2 GFC0/IO147NDB3 E3 GFC1/IO147PDB3 E4 VCCIB3 E5 IO155VPB3 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO67PDB1 E9 VCCIB1 E10 VCC E11 GCA0/IO69NDB1 E12 IO70NDB1 F1 GFB0/IO146NPB3 F2 VCOMPLF F3 GFB1/IO146PPB3 F4 IO144NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO67NDB1 F9 GCB0/IO68NPB1 F10 GND F11 GCA1/IO69PDB1 F12 GCA2/IO70PDB1 FG144 Pin Number A3P400 Function G1 GFA1/IO145PPB3 G2 GND G3 VCCPLF G4 GFA0/IO145NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO77UPB1 G9 IO72NDB1 G10 GCC2/IO72PDB1 G11 IO71NDB1 G12 GCB2/IO71PDB1 H1 VCC H2 GFB2/IO143PDB3 H3 GFC2/IO142PSB3 H4 GEC1/IO137PDB3 H5 VCC H6 IO75PDB1 H7 IO75NDB1 H8 GDB2/IO81RSB2 H9 GDC0/IO77VPB1 H10 VCCIB1 H11 IO73PSB1 H12 VCC J1 GEB1/IO136PDB3 J2 IO143NDB3 J3 VCCIB3 J4 GEC0/IO137NDB3 J5 IO125RSB2 J6 IO116RSB2 J7 VCC J8 TCK J9 GDA2/IO80RSB2 J10 TDO J11 GDA1/IO79UDB1 J12 GDB1/IO78UDB1 FG144 Pin Number A3P400 Function

ProASIC3 Flash Family FPGAs Revision 13 4-47 K1 GEB0/IO136NDB3 K2 GEA1/IO135PDB3 K3 GEA0/IO135NDB3 K4 GEA2/IO134RSB2 K5 IO127RSB2 K6 IO121RSB2 K7 GND K8 IO104RSB2 K9 GDC2/IO82RSB2 K10 GND K11 GDA0/IO79VDB1 K12 GDB0/IO78VDB1 L1 GND L2 VMV3 L3 GEB2/IO133RSB2 L4 IO128RSB2 L5 VCCIB2 L6 IO119RSB2 L7 IO114RSB2 L8 IO110RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO132RSB2 M3 IO129RSB2 M4 IO126RSB2 M5 IO124RSB2 M6 IO122RSB2 M7 IO117RSB2 M8 IO115RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ FG144 Pin Number A3P400 Function

Pin Number A3P600 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO34RSB0 A8 VCC A9 IO50RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO173PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO13RSB0 B6 IO19RSB0 B7 IO31RSB0 B8 IO39RSB0 B9 GBB0/IO56RSB0 B10 GBB1/IO57RSB0 B11 GND B12 VMV1 C1 IO173NDB3 C2 GFA2/IO161PPB3 C3 GAC2/IO172PDB3 C4 VCC C5 IO16RSB0 C6 IO25RSB0 C7 IO28RSB0 C8 IO42RSB0 C9 IO45RSB0 C10 GBA2/IO60PDB1 C11 IO60NDB1 C12 GBC2/IO62PPB1 D1 IO169PDB3 D2 IO169NDB3 D3 IO172NDB3 D4 GAA2/IO174PPB3 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO54RSB0 D8 GBC1/IO55RSB0 D9 GBB2/IO61PDB1 D10 IO61NDB1 D11 IO62NPB1 D12 GCB1/IO70PPB1 E1 VCC E2 GFC0/IO164NDB3 E3 GFC1/IO164PDB3 E4 VCCIB3 E5 IO174NPB3 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO69PDB1 E9 VCCIB1 E10 VCC E11 GCA0/IO71NDB1 E12 IO72NDB1 F1 GFB0/IO163NPB3 F2 VCOMPLF F3 GFB1/IO163PPB3 F4 IO161NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO69NDB1 F9 GCB0/IO70NPB1 F10 GND F11 GCA1/IO71PDB1 F12 GCA2/IO72PDB1 FG144 Pin Number A3P600 Function G1 GFA1/IO162PPB3 G2 GND G3 VCCPLF G4 GFA0/IO162NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO86PPB1 G9 IO74NDB1 G10 GCC2/IO74PDB1 G11 IO73NDB1 G12 GCB2/IO73PDB1 H1 VCC H2 GFB2/IO160PDB3 H3 GFC2/IO159PSB3 H4 GEC1/IO146PDB3 H5 VCC H6 IO80PDB1 H7 IO80NDB1 H8 GDB2/IO90RSB2 H9 GDC0/IO86NPB1 H10 VCCIB1 H11 IO84PSB1 H12 VCC J1 GEB1/IO145PDB3 J2 IO160NDB3 J3 VCCIB3 J4 GEC0/IO146NDB3 J5 IO129RSB2 J6 IO131RSB2 J7 VCC J8 TCK J9 GDA2/IO89RSB2 J10 TDO J11 GDA1/IO88PDB1 J12 GDB1/IO87PDB1 FG144 Pin Number A3P600 Function

ProASIC3 Flash Family FPGAs Revision 13 4-49 K1 GEB0/IO145NDB3 K2 GEA1/IO144PDB3 K3 GEA0/IO144NDB3 K4 GEA2/IO143RSB2 K5 IO119RSB2 K6 IO111RSB2 K7 GND K8 IO94RSB2 K9 GDC2/IO91RSB2 K10 GND K11 GDA0/IO88NDB1 K12 GDB0/IO87NDB1 L1 GND L2 VMV3 L3 GEB2/IO142RSB2 L4 IO136RSB2 L5 VCCIB2 L6 IO115RSB2 L7 IO103RSB2 L8 IO97RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO141RSB2 M3 IO138RSB2 M4 IO123RSB2 M5 IO126RSB2 M6 IO134RSB2 M7 IO108RSB2 M8 IO99RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ FG144 Pin Number A3P600 Function

Pin Number A3P1000 Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 A8 VCC A9 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO13RSB0 B6 IO26RSB0 B7 IO35RSB0 B8 IO60RSB0 B9 GBB0/IO74RSB0 B10 GBB1/IO75RSB0 B11 GND B12 VMV1 C1 IO224NDB3 C2 GFA2/IO206PPB3 C3 GAC2/IO223PDB3 C4 VCC C5 IO16RSB0 C6 IO29RSB0 C7 IO32RSB0 C8 IO63RSB0 C9 IO66RSB0 C10 GBA2/IO78PDB1 C11 IO78NDB1 C12 GBC2/IO80PPB1 D1 IO213PDB3 D2 IO213NDB3 D3 IO223NDB3 D4 GAA2/IO225PPB3 D5 GAC0/IO04RSB0 D6 GAC1/IO05RSB0 D7 GBC0/IO72RSB0 D8 GBC1/IO73RSB0 D9 GBB2/IO79PDB1 D10 IO79NDB1 D11 IO80NPB1 D12 GCB1/IO92PPB1 E1 VCC E2 GFC0/IO209NDB3 E3 GFC1/IO209PDB3 E4 VCCIB3 E5 IO225NPB3 E6 VCCIB0 E7 VCCIB0 E8 GCC1/IO91PDB1 E9 VCCIB1 E10 VCC E11 GCA0/IO93NDB1 E12 IO94NDB1 F1 GFB0/IO208NPB3 F2 VCOMPLF F3 GFB1/IO208PPB3 F4 IO206NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO91NDB1 F9 GCB0/IO92NPB1 F10 GND F11 GCA1/IO93PDB1 F12 GCA2/IO94PDB1 FG144 Pin Number A3P1000 Function G1 GFA1/IO207PPB3 G2 GND G3 VCCPLF G4 GFA0/IO207NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO111PPB1 G9 IO96NDB1 G10 GCC2/IO96PDB1 G11 IO95NDB1 G12 GCB2/IO95PDB1 H1 VCC H2 GFB2/IO205PDB3 H3 GFC2/IO204PSB3 H4 GEC1/IO190PDB3 H5 VCC H6 IO105PDB1 H7 IO105NDB1 H8 GDB2/IO115RSB2 H9 GDC0/IO111NPB1 H10 VCCIB1 H11 IO101PSB1 H12 VCC J1 GEB1/IO189PDB3 J2 IO205NDB3 J3 VCCIB3 J4 GEC0/IO190NDB3 J5 IO160RSB2 J6 IO157RSB2 J7 VCC J8 TCK J9 GDA2/IO114RSB2 J10 TDO J11 GDA1/IO113PDB1 J12 GDB1/IO112PDB1 FG144 Pin Number A3P1000 Function

ProASIC3 Flash Family FPGAs Revision 13 4-51 K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 GEB2/IO186RSB2 L4 IO172RSB2 L5 VCCIB2 L6 IO153RSB2 L7 IO144RSB2 L8 IO140RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO185RSB2 M3 IO173RSB2 M4 IO168RSB2 M5 IO161RSB2 M6 IO156RSB2 M7 IO145RSB2 M8 IO141RSB2 M9 TDI M10 VCCIB2 M11 VPUMP M12 GNDQ FG144 Pin Number A3P1000 Function

ProASIC3 Flash Family FPGAs Revision 13 4-53 FG256 Pin Number A3P250 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO07RSB0 A6 IO10RSB0 A7 IO11RSB0 A8 IO15RSB0 A9 IO20RSB0 A10 IO25RSB0 A11 IO29RSB0 A12 IO33RSB0 A13 GBB1/IO38RSB0 A14 GBA0/IO39RSB0 A15 GBA1/IO40RSB0 A16 GND B1 GAB2/IO117UDB3 B2 GAA2/IO118UDB3 B3 NC B4 GAB1/IO03RSB0 B5 IO06RSB0 B6 IO09RSB0 B7 IO12RSB0 B8 IO16RSB0 B9 IO21RSB0 B10 IO26RSB0 B11 IO30RSB0 B12 GBC1/IO36RSB0 B13 GBB0/IO37RSB0 B14 NC B15 GBA2/IO41PDB1 B16 IO41NDB1 C1 IO117VDB3 C2 IO118VDB3 C3 NC C4 NC C5 GAC0/IO04RSB0 C6 GAC1/IO05RSB0 C7 IO13RSB0 C8 IO17RSB0 C9 IO22RSB0 C10 IO27RSB0 C11 IO31RSB0 C12 GBC0/IO35RSB0 C13 IO34RSB0 C14 NC C15 IO42NPB1 C16 IO44PDB1 D1 IO114VDB3 D2 IO114UDB3 D3 GAC2/IO116UDB3 D4 NC D5 GNDQ D6 IO08RSB0 D7 IO14RSB0 D8 IO18RSB0 D9 IO23RSB0 D10 IO28RSB0 D11 IO32RSB0 D12 GNDQ D13 NC D14 GBB2/IO42PPB1 D15 NC D16 IO44NDB1 E1 IO113PDB3 E2 NC E3 IO116VDB3 E4 IO115UDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO19RSB0 FG256 Pin Number A3P250 Function E9 IO24RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO43PDB1 E14 IO46RSB1 E15 NC E16 IO45PDB1 F1 IO113NDB3 F2 IO112PPB3 F3 NC F4 IO115VDB3 F5 VCCIB3 F6 GND F7 VCC F8 VCC F9 VCC F10 VCC F11 GND F12 VCCIB1 F13 IO43NDB1 F14 NC F15 IO47PPB1 F16 IO45NDB1 G1 IO111NDB3 G2 IO111PDB3 G3 IO112NPB3 G4 GFC1/IO110PPB3 G5 VCCIB3 G6 VCC G7 GND G8 GND G9 GND G10 GND G11 VCC G12 VCCIB1 FG256 Pin Number A3P250 Function

Pin Number A3P250 Function K1 GFC2/IO105PDB3 K2 IO107NPB3 K3 IO104PPB3 K4 NC K5 VCCIB3 K6 VCC K7 GND K8 GND K9 GND K10 GND K11 VCC K12 VCCIB1 K13 IO52NPB1 K14 IO55RSB1 K15 IO53NPB1 K16 IO51NDB1 L1 IO105NDB3 L2 IO104NPB3 L3 NC L4 IO102RSB3 L5 VCCIB3 L6 GND L7 VCC L8 VCC L9 VCC L10 VCC L11 GND L12 VCCIB1 L13 GDB0/IO59VPB1 L14 IO57VDB1 L15 IO57UDB1 L16 IO56PDB1 M1 IO103PDB3 M2 NC M3 IO101NPB3 M4 GEC0/IO100NPB3 FG256 Pin Number A3P250 Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 NC M9 IO74RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 NC M14 GDB1/IO59UPB1 M15 GDC1/IO58UDB1 M16 IO56NDB1 N1 IO103NDB3 N2 IO101PPB3 N3 GEC1/IO100PPB3 N4 NC N5 GNDQ N6 GEA2/IO97RSB2 N7 IO86RSB2 N8 IO82RSB2 N9 IO75RSB2 N10 IO69RSB2 N11 IO64RSB2 N12 GNDQ N13 NC N14 VJTAG N15 GDC0/IO58VDB1 N16 GDA1/IO60UDB1 P1 GEB1/IO99PDB3 P2 GEB0/IO99NDB3 P3 NC P4 NC P5 IO92RSB2 P6 IO89RSB2 P7 IO85RSB2 P8 IO81RSB2 FG256 Pin Number A3P250 Function

ProASIC3 Flash Family FPGAs Revision 13 4-55 P9 IO76RSB2 P10 IO71RSB2 P11 IO66RSB2 P12 NC P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO60VDB1 R1 GEA1/IO98PDB3 R2 GEA0/IO98NDB3 R3 NC R4 GEC2/IO95RSB2 R5 IO91RSB2 R6 IO88RSB2 R7 IO84RSB2 R8 IO80RSB2 R9 IO77RSB2 R10 IO72RSB2 R11 IO68RSB2 R12 IO65RSB2 R13 GDB2/IO62RSB2 R14 TDI R15 NC R16 TDO T1 GND T2 IO94RSB2 T3 GEB2/IO96RSB2 T4 IO93RSB2 T5 IO90RSB2 T6 IO87RSB2 T7 IO83RSB2 T8 IO79RSB2 T9 IO78RSB2 T10 IO73RSB2 T11 IO70RSB2 T12 GDC2/IO63RSB2 FG256 Pin Number A3P250 Function T13 IO67RSB2 T14 GDA2/IO61RSB2 T15 TMS T16 GND FG256 Pin Number A3P250 Function

Pin Number A3P400 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO17RSB0 A7 IO22RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 GND B1 GAB2/IO154UDB3 B2 GAA2/IO155UDB3 B3 IO12RSB0 B4 GAB1/IO03RSB0 B5 IO13RSB0 B6 IO14RSB0 B7 IO21RSB0 B8 IO27RSB0 B9 IO32RSB0 B10 IO38RSB0 B11 IO42RSB0 B12 GBC1/IO55RSB0 B13 GBB0/IO56RSB0 B14 IO44RSB0 B15 GBA2/IO60PDB1 B16 IO60NDB1 C1 IO154VDB3 C2 IO155VDB3 C3 IO11RSB0 C4 IO07RSB0 C5 GAC0/IO04RSB0 C6 GAC1/IO05RSB0 C7 IO20RSB0 C8 IO24RSB0 C9 IO33RSB0 C10 IO39RSB0 C11 IO45RSB0 C12 GBC0/IO54RSB0 C13 IO48RSB0 C14 VMV0 C15 IO61NPB1 C16 IO63PDB1 D1 IO151VDB3 D2 IO151UDB3 D3 GAC2/IO153UDB3 D4 IO06RSB0 D5 GNDQ D6 IO10RSB0 D7 IO19RSB0 D8 IO26RSB0 D9 IO30RSB0 D10 IO40RSB0 D11 IO46RSB0 D12 GNDQ D13 IO47RSB0 D14 GBB2/IO61PPB1 D15 IO53RSB0 D16 IO63NDB1 E1 IO150PDB3 E2 IO08RSB0 E3 IO153VDB3 E4 IO152VDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO25RSB0 FG256 Pin Number A3P400 Function E9 IO31RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO62PDB1 E14 IO65RSB1 E15 IO52RSB0 E16 IO66PDB1 F1 IO150NDB3 F2 IO149NPB3 F3 IO09RSB0 F4 IO152UDB3 F5 VCCIB3 F6 GND F7 VCC F8 VCC F9 VCC F10 VCC F11 GND F12 VCCIB1 F13 IO62NDB1 F14 IO49RSB0 F15 IO64PPB1 F16 IO66NDB1 G1 IO148NDB3 G2 IO148PDB3 G3 IO149PPB3 G4 GFC1/IO147PPB3 G5 VCCIB3 G6 VCC G7 GND G8 GND G9 GND G10 GND G11 VCC G12 VCCIB1 FG256 Pin Number A3P400 Function

ProASIC3 Flash Family FPGAs Revision 13 4-57 G13 GCC1/IO67PPB1 G14 IO64NPB1 G15 IO73PDB1 G16 IO73NDB1 H1 GFB0/IO146NPB3 H2 GFA0/IO145NDB3 H3 GFB1/IO146PPB3 H4 VCOMPLF H5 GFC0/IO147NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO67NPB1 H13 GCB1/IO68PPB1 H14 GCA0/IO69NPB1 H15 NC H16 GCB0/IO68NPB1 J1 GFA2/IO144PPB3 J2 GFA1/IO145PDB3 J3 VCCPLF J4 IO143NDB3 J5 GFB2/IO143PDB3 J6 VCC J7 GND J8 GND J9 GND J10 GND J11 VCC J12 GCB2/IO71PPB1 J13 GCA1/IO69PPB1 J14 GCC2/IO72PPB1 J15 NC J16 GCA2/IO70PDB1 FG256 Pin Number A3P400 Function K1 GFC2/IO142PDB3 K2 IO144NPB3 K3 IO141PPB3 K4 IO120RSB2 K5 VCCIB3 K6 VCC K7 GND K8 GND K9 GND K10 GND K11 VCC K12 VCCIB1 K13 IO71NPB1 K14 IO74RSB1 K15 IO72NPB1 K16 IO70NDB1 L1 IO142NDB3 L2 IO141NPB3 L3 IO125RSB2 L4 IO139RSB3 L5 VCCIB3 L6 GND L7 VCC L8 VCC L9 VCC L10 VCC L11 GND L12 VCCIB1 L13 GDB0/IO78VPB1 L14 IO76VDB1 L15 IO76UDB1 L16 IO75PDB1 M1 IO140PDB3 M2 IO130RSB2 M3 IO138NPB3 M4 GEC0/IO137NPB3 FG256 Pin Number A3P400 Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 IO108RSB2 M9 IO101RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 IO83RSB2 M14 GDB1/IO78UPB1 M15 GDC1/IO77UDB1 M16 IO75NDB1 N1 IO140NDB3 N2 IO138PPB3 N3 GEC1/IO137PPB3 N4 IO131RSB2 N5 GNDQ N6 GEA2/IO134RSB2 N7 IO117RSB2 N8 IO111RSB2 N9 IO99RSB2 N10 IO94RSB2 N11 IO87RSB2 N12 GNDQ N13 IO93RSB2 N14 VJTAG N15 GDC0/IO77VDB1 N16 GDA1/IO79UDB1 P1 GEB1/IO136PDB3 P2 GEB0/IO136NDB3 P3 VMV2 P4 IO129RSB2 P5 IO128RSB2 P6 IO122RSB2 P7 IO115RSB2 P8 IO110RSB2 FG256 Pin Number A3P400 Function

Pin Number A3P400 Function T13 IO86RSB2 T14 GDA2/IO80RSB2 T15 TMS T16 GND FG256 Pin Number A3P400 Function

ProASIC3 Flash Family FPGAs Revision 13 4-59 FG256 Pin Number A3P600 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO11RSB0 A6 IO16RSB0 A7 IO18RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 GND B1 GAB2/IO173PDB3 B2 GAA2/IO174PDB3 B3 GNDQ B4 GAB1/IO03RSB0 B5 IO13RSB0 B6 IO14RSB0 B7 IO21RSB0 B8 IO27RSB0 B9 IO32RSB0 B10 IO38RSB0 B11 IO42RSB0 B12 GBC1/IO55RSB0 B13 GBB0/IO56RSB0 B14 IO52RSB0 B15 GBA2/IO60PDB1 B16 IO60NDB1 C1 IO173NDB3 C2 IO174NDB3 C3 VMV3 C4 IO07RSB0 C5 GAC0/IO04RSB0 C6 GAC1/IO05RSB0 C7 IO20RSB0 C8 IO24RSB0 C9 IO33RSB0 C10 IO39RSB0 C11 IO44RSB0 C12 GBC0/IO54RSB0 C13 IO51RSB0 C14 VMV0 C15 IO61NPB1 C16 IO63PDB1 D1 IO171NDB3 D2 IO171PDB3 D3 GAC2/IO172PDB3 D4 IO06RSB0 D5 GNDQ D6 IO10RSB0 D7 IO19RSB0 D8 IO26RSB0 D9 IO30RSB0 D10 IO40RSB0 D11 IO45RSB0 D12 GNDQ D13 IO50RSB0 D14 GBB2/IO61PPB1 D15 IO53RSB0 D16 IO63NDB1 E1 IO166PDB3 E2 IO167NPB3 E3 IO172NDB3 E4 IO169NDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO25RSB0 FG256 Pin Number A3P600 Function E9 IO31RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO62PDB1 E14 IO67PPB1 E15 IO64PPB1 E16 IO66PDB1 F1 IO166NDB3 F2 IO168NPB3 F3 IO167PPB3 F4 IO169PDB3 F5 VCCIB3 F6 GND F7 VCC F8 VCC F9 VCC F10 VCC F11 GND F12 VCCIB1 F13 IO62NDB1 F14 IO64NPB1 F15 IO65PPB1 F16 IO66NDB1 G1 IO165NDB3 G2 IO165PDB3 G3 IO168PPB3 G4 GFC1/IO164PPB3 G5 VCCIB3 G6 VCC G7 GND G8 GND G9 GND G10 GND G11 VCC G12 VCCIB1 FG256 Pin Number A3P600 Function

Pin Number A3P600 Function K1 GFC2/IO159PDB3 K2 IO161NPB3 K3 IO156PPB3 K4 IO129RSB2 K5 VCCIB3 K6 VCC K7 GND K8 GND K9 GND K10 GND K11 VCC K12 VCCIB1 K13 IO73NPB1 K14 IO80NPB1 K15 IO74NPB1 K16 IO72NDB1 L1 IO159NDB3 L2 IO156NPB3 L3 IO151PPB3 L4 IO158PSB3 L5 VCCIB3 L6 GND L7 VCC L8 VCC L9 VCC L10 VCC L11 GND L12 VCCIB1 L13 GDB0/IO87NPB1 L14 IO85NDB1 L15 IO85PDB1 L16 IO84PDB1 M1 IO150PDB3 M2 IO151NPB3 M3 IO147NPB3 M4 GEC0/IO146NPB3 FG256 Pin Number A3P600 Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 IO117RSB2 M9 IO110RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 IO94RSB2 M14 GDB1/IO87PPB1 M15 GDC1/IO86PDB1 M16 IO84NDB1 N1 IO150NDB3 N2 IO147PPB3 N3 GEC1/IO146PPB3 N4 IO140RSB2 N5 GNDQ N6 GEA2/IO143RSB2 N7 IO126RSB2 N8 IO120RSB2 N9 IO108RSB2 N10 IO103RSB2 N11 IO99RSB2 N12 GNDQ N13 IO92RSB2 N14 VJTAG N15 GDC0/IO86NDB1 N16 GDA1/IO88PDB1 P1 GEB1/IO145PDB3 P2 GEB0/IO145NDB3 P3 VMV2 P4 IO138RSB2 P5 IO136RSB2 P6 IO131RSB2 P7 IO124RSB2 P8 IO119RSB2 FG256 Pin Number A3P600 Function

ProASIC3 Flash Family FPGAs Revision 13 4-61 P9 IO107RSB2 P10 IO104RSB2 P11 IO97RSB2 P12 VMV1 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO88NDB1 R1 GEA1/IO144PDB3 R2 GEA0/IO144NDB3 R3 IO139RSB2 R4 GEC2/IO141RSB2 R5 IO132RSB2 R6 IO127RSB2 R7 IO121RSB2 R8 IO114RSB2 R9 IO109RSB2 R10 IO105RSB2 R11 IO98RSB2 R12 IO96RSB2 R13 GDB2/IO90RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO137RSB2 T3 GEB2/IO142RSB2 T4 IO134RSB2 T5 IO125RSB2 T6 IO123RSB2 T7 IO118RSB2 T8 IO115RSB2 T9 IO111RSB2 T10 IO106RSB2 T11 IO102RSB2 T12 GDC2/IO91RSB2 FG256 Pin Number A3P600 Function T13 IO93RSB2 T14 GDA2/IO89RSB2 T15 TMS T16 GND FG256 Pin Number A3P600 Function

Pin Number A3P1000 Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO22RSB0 A7 IO28RSB0 A8 IO35RSB0 A9 IO45RSB0 A10 IO50RSB0 A11 IO55RSB0 A12 IO61RSB0 A13 GBB1/IO75RSB0 A14 GBA0/IO76RSB0 A15 GBA1/IO77RSB0 A16 GND B1 GAB2/IO224PDB3 B2 GAA2/IO225PDB3 B3 GNDQ B4 GAB1/IO03RSB0 B5 IO17RSB0 B6 IO21RSB0 B7 IO27RSB0 B8 IO34RSB0 B9 IO44RSB0 B10 IO51RSB0 B11 IO57RSB0 B12 GBC1/IO73RSB0 B13 GBB0/IO74RSB0 B14 IO71RSB0 B15 GBA2/IO78PDB1 B16 IO81PDB1 C1 IO224NDB3 C2 IO225NDB3 C3 VMV3 C4 IO11RSB0 C5 GAC0/IO04RSB0 C6 GAC1/IO05RSB0 C7 IO25RSB0 C8 IO36RSB0 C9 IO42RSB0 C10 IO49RSB0 C11 IO56RSB0 C12 GBC0/IO72RSB0 C13 IO62RSB0 C14 VMV0 C15 IO78NDB1 C16 IO81NDB1 D1 IO222NDB3 D2 IO222PDB3 D3 GAC2/IO223PDB3 D4 IO223NDB3 D5 GNDQ D6 IO23RSB0 D7 IO29RSB0 D8 IO33RSB0 D9 IO46RSB0 D10 IO52RSB0 D11 IO60RSB0 D12 GNDQ D13 IO80NDB1 D14 GBB2/IO79PDB1 D15 IO79NDB1 D16 IO82NSB1 E1 IO217PDB3 E2 IO218PDB3 E3 IO221NDB3 E4 IO221PDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO38RSB0 E9 IO47RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 FG256 Pin Number A3P1000 Function E13 GBC2/IO80PDB1 E14 IO83PPB1 E15 IO86PPB1 E16 IO87PDB1 F1 IO217NDB3 F2 IO218NDB3 F3 IO216PDB3 F4 IO216NDB3 F5 VCCIB3 F6 GND F7 VCC F8 VCC F9 VCC F10 VCC F11 GND F12 VCCIB1 F13 IO83NPB1 F14 IO86NPB1 F15 IO90PPB1 F16 IO87NDB1 G1 IO210PSB3 G2 IO213NDB3 G3 IO213PDB3 G4 GFC1/IO209PPB3 G5 VCCIB3 G6 VCC G7 GND G8 GND G9 GND G10 GND G11 VCC G12 VCCIB1 G13 GCC1/IO91PPB1 G14 IO90NPB1 G15 IO88PDB1 G16 IO88NDB1 H1 GFB0/IO208NPB3 H2 GFA0/IO207NDB3 FG256 Pin Number A3P1000 Function

ProASIC3 Flash Family FPGAs Revision 13 4-63 H3 GFB1/IO208PPB3 H4 VCOMPLF H5 GFC0/IO209NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO91NPB1 H13 GCB1/IO92PPB1 H14 GCA0/IO93NPB1 H15 IO96NPB1 H16 GCB0/IO92NPB1 J1 GFA2/IO206PSB3 J2 GFA1/IO207PDB3 J3 VCCPLF J4 IO205NDB3 J5 GFB2/IO205PDB3 J6 VCC J7 GND J8 GND J9 GND J10 GND J11 VCC J12 GCB2/IO95PPB1 J13 GCA1/IO93PPB1 J14 GCC2/IO96PPB1 J15 IO100PPB1 J16 GCA2/IO94PSB1 K1 GFC2/IO204PDB3 K2 IO204NDB3 K3 IO203NDB3 K4 IO203PDB3 K5 VCCIB3 K6 VCC K7 GND K8 GND FG256 Pin Number A3P1000 Function K9 GND K10 GND K11 VCC K12 VCCIB1 K13 IO95NPB1 K14 IO100NPB1 K15 IO102NDB1 K16 IO102PDB1 L1 IO202NDB3 L2 IO202PDB3 L3 IO196PPB3 L4 IO193PPB3 L5 VCCIB3 L6 GND L7 VCC L8 VCC L9 VCC L10 VCC L11 GND L12 VCCIB1 L13 GDB0/IO112NPB1 L14 IO106NDB1 L15 IO106PDB1 L16 IO107PDB1 M1 IO197NSB3 M2 IO196NPB3 M3 IO193NPB3 M4 GEC0/IO190NPB3 M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 IO147RSB2 M9 IO136RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 IO110NDB1 M14 GDB1/IO112PPB1 FG256 Pin Number A3P1000 Function M15 GDC1/IO111PDB1 M16 IO107NDB1 N1 IO194PSB3 N2 IO192PPB3 N3 GEC1/IO190PPB3 N4 IO192NPB3 N5 GNDQ N6 GEA2/IO187RSB2 N7 IO161RSB2 N8 IO155RSB2 N9 IO141RSB2 N10 IO129RSB2 N11 IO124RSB2 N12 GNDQ N13 IO110PDB1 N14 VJTAG N15 GDC0/IO111NDB1 N16 GDA1/IO113PDB1 P1 GEB1/IO189PDB3 P2 GEB0/IO189NDB3 P3 VMV2 P4 IO179RSB2 P5 IO171RSB2 P6 IO165RSB2 P7 IO159RSB2 P8 IO151RSB2 P9 IO137RSB2 P10 IO134RSB2 P11 IO128RSB2 P12 VMV1 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO113NDB1 R1 GEA1/IO188PDB3 R2 GEA0/IO188NDB3 R3 IO184RSB2 R4 GEC2/IO185RSB2 FG256 Pin Number A3P1000 Function

Pin Number A3P1000 Function

ProASIC3 Flash Family FPGAs Revision 13 4-65 FG484 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. A B C D E F G H J K L M N P R T U V W Y AA AB 12345678910111213141516171819202122 A1 Ball Pad Corner

Pin Number A3P400 Function A1 GND A2 GND A3 VCCIB0 A4 NC A5 NC A6 IO15RSB0 A7 IO18RSB0 A8 NC A9 NC A10 IO23RSB0 A11 IO29RSB0 A12 IO35RSB0 A13 IO36RSB0 A14 NC A15 NC A16 IO50RSB0 A17 IO51RSB0 A18 NC A19 NC A20 VCCIB0 A21 GND A22 GND B1 GND B2 VCCIB3 B3 NC B4 NC B5 NC B6 NC B7 NC B8 NC B9 NC B10 NC B11 NC B12 NC B13 NC B14 NC B15 NC B16 NC B17 NC B18 NC B19 NC B20 NC B21 VCCIB1 B22 GND C1 VCCIB3 C2 NC C3 NC C4 NC C5 GND C6 NC C7 NC C8 VCC C9 VCC C10 NC C11 NC C12 NC C13 NC C14 VCC C15 VCC C16 NC C17 NC C18 GND C19 NC C20 NC C21 NC C22 VCCIB1 D1 NC D2 NC D3 NC D4 GND D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 FG484 Pin Number A3P400 Function D7 GAB0/IO02RSB0 D8 IO16RSB0 D9 IO17RSB0 D10 IO22RSB0 D11 IO28RSB0 D12 IO34RSB0 D13 IO37RSB0 D14 IO41RSB0 D15 IO43RSB0 D16 GBB1/IO57RSB0 D17 GBA0/IO58RSB0 D18 GBA1/IO59RSB0 D19 GND D20 NC D21 NC D22 NC E1 NC E2 NC E3 GND E4 GAB2/IO154UDB3 E5 GAA2/IO155UDB3 E6 IO12RSB0 E7 GAB1/IO03RSB0 E8 IO13RSB0 E9 IO14RSB0 E10 IO21RSB0 E11 IO27RSB0 E12 IO32RSB0 E13 IO38RSB0 E14 IO42RSB0 E15 GBC1/IO55RSB0 E16 GBB0/IO56RSB0 E17 IO44RSB0 E18 GBA2/IO60PDB1 E19 IO60NDB1 E20 GND FG484 Pin Number A3P400 Function

ProASIC3 Flash Family FPGAs Revision 13 4-67 E21 NC E22 NC F1 NC F2 NC F3 NC F4 IO154VDB3 F5 IO155VDB3 F6 IO11RSB0 F7 IO07RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO20RSB0 F11 IO24RSB0 F12 IO33RSB0 F13 IO39RSB0 F14 IO45RSB0 F15 GBC0/IO54RSB0 F16 IO48RSB0 F17 VMV0 F18 IO61NPB1 F19 IO63PDB1 F20 NC F21 NC F22 NC G1 NC G2 NC G3 NC G4 IO151VDB3 G5 IO151UDB3 G6 GAC2/IO153UDB3 G7 IO06RSB0 G8 GNDQ G9 IO10RSB0 G10 IO19RSB0 G11 IO26RSB0 G12 IO30RSB0 FG484 Pin Number A3P400 Function G13 IO40RSB0 G14 IO46RSB0 G15 GNDQ G16 IO47RSB0 G17 GBB2/IO61PPB1 G18 IO53RSB0 G19 IO63NDB1 G20 NC G21 NC G22 NC H1 NC H2 NC H3 VCC H4 IO150PDB3 H5 IO08RSB0 H6 IO153VDB3 H7 IO152VDB3 H8 VMV0 H9 VCCIB0 H10 VCCIB0 H11 IO25RSB0 H12 IO31RSB0 H13 VCCIB0 H14 VCCIB0 H15 VMV1 H16 GBC2/IO62PDB1 H17 IO65RSB1 H18 IO52RSB0 H19 IO66PDB1 H20 VCC H21 NC H22 NC J1 NC J2 NC J3 NC J4 IO150NDB3 FG484 Pin Number A3P400 Function J5 IO149NPB3 J6 IO09RSB0 J7 IO152UDB3 J8 VCCIB3 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC J14 GND J15 VCCIB1 J16 IO62NDB1 J17 IO49RSB0 J18 IO64PPB1 J19 IO66NDB1 J20 NC J21 NC J22 NC K1 NC K2 NC K3 NC K4 IO148NDB3 K5 IO148PDB3 K6 IO149PPB3 K7 GFC1/IO147PPB3 K8 VCCIB3 K9 VCC K10 GND K11 GND K12 GND K13 GND K14 VCC K15 VCCIB1 K16 GCC1/IO67PPB1 K17 IO64NPB1 K18 IO73PDB1 FG484 Pin Number A3P400 Function

Pin Number A3P400 Function M11 GND M12 GND M13 GND M14 VCC M15 GCB2/IO71PPB1 M16 GCA1/IO69PPB1 M17 GCC2/IO72PPB1 M18 NC M19 GCA2/IO70PDB1 M20 NC M21 NC M22 NC N1 NC N2 NC N3 NC N4 GFC2/IO142PDB3 N5 IO144NPB3 N6 IO141PPB3 N7 IO120RSB2 N8 VCCIB3 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB1 N16 IO71NPB1 N17 IO74RSB1 N18 IO72NPB1 N19 IO70NDB1 N20 NC N21 NC N22 NC P1 NC P2 NC FG484 Pin Number A3P400 Function P3 NC P4 IO142NDB3 P5 IO141NPB3 P6 IO125RSB2 P7 IO139RSB3 P8 VCCIB3 P9 GND P10 VCC P11 VCC P12 VCC P13 VCC P14 GND P15 VCCIB1 P16 GDB0/IO78VPB1 P17 IO76VDB1 P18 IO76UDB1 P19 IO75PDB1 P20 NC P21 NC P22 NC R1 NC R2 NC R3 VCC R4 IO140PDB3 R5 IO130RSB2 R6 IO138NPB3 R7 GEC0/IO137NPB3 R8 VMV3 R9 VCCIB2 R10 VCCIB2 R11 IO108RSB2 R12 IO101RSB2 R13 VCCIB2 R14 VCCIB2 R15 VMV2 R16 IO83RSB2 FG484 Pin Number A3P400 Function

ProASIC3 Flash Family FPGAs Revision 13 4-69 R17 GDB1/IO78UPB1 R18 GDC1/IO77UDB1 R19 IO75NDB1 R20 VCC R21 NC R22 NC T1 NC T2 NC T3 NC T4 IO140NDB3 T5 IO138PPB3 T6 GEC1/IO137PPB3 T7 IO131RSB2 T8 GNDQ T9 GEA2/IO134RSB2 T10 IO117RSB2 T11 IO111RSB2 T12 IO99RSB2 T13 IO94RSB2 T14 IO87RSB2 T15 GNDQ T16 IO93RSB2 T17 VJTAG T18 GDC0/IO77VDB1 T19 GDA1/IO79UDB1 T20 NC T21 NC T22 NC U1 NC U2 NC U3 NC U4 GEB1/IO136PDB3 U5 GEB0/IO136NDB3 U6 VMV2 U7 IO129RSB2 U8 IO128RSB2 FG484 Pin Number A3P400 Function U9 IO122RSB2 U10 IO115RSB2 U11 IO110RSB2 U12 IO98RSB2 U13 IO95RSB2 U14 IO88RSB2 U15 IO84RSB2 U16 TCK U17 VPUMP U18 TRST U19 GDA0/IO79VDB1 U20 NC U21 NC U22 NC V1 NC V2 NC V3 GND V4 GEA1/IO135PDB3 V5 GEA0/IO135NDB3 V6 IO127RSB2 V7 GEC2/IO132RSB2 V8 IO123RSB2 V9 IO118RSB2 V10 IO112RSB2 V11 IO106RSB2 V12 IO100RSB2 V13 IO96RSB2 V14 IO89RSB2 V15 IO85RSB2 V16 GDB2/IO81RSB2 V17 TDI V18 NC V19 TDO V20 GND V21 NC V22 NC FG484 Pin Number A3P400 Function W1 NC W2 NC W3 NC W4 GND W5 IO126RSB2 W6 GEB2/IO133RSB2 W7 IO124RSB2 W8 IO116RSB2 W9 IO113RSB2 W10 IO107RSB2 W11 IO105RSB2 W12 IO102RSB2 W13 IO97RSB2 W14 IO92RSB2 W15 GDC2/IO82RSB2 W16 IO86RSB2 W17 GDA2/IO80RSB2 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB3 Y2 NC Y3 NC Y4 NC Y5 GND Y6 NC Y7 NC Y8 VCC Y9 VCC Y10 NC Y11 NC Y12 NC Y13 NC Y14 VCC FG484 Pin Number A3P400 Function

Pin Number A3P400 Function AB7 IO119RSB2 AB8 IO114RSB2 AB9 IO109RSB2 AB10 NC AB11 NC AB12 IO104RSB2 AB13 IO103RSB2 AB14 NC AB15 NC AB16 IO91RSB2 AB17 IO90RSB2 AB18 NC AB19 NC AB20 VCCIB2 AB21 GND AB22 GND FG484 Pin Number A3P400 Function

ProASIC3 Flash Family FPGAs Revision 13 4-71 FG484 Pin Number A3P600 Function A1 GND A2 GND A3 VCCIB0 A4 NC A5 NC A6 IO09RSB0 A7 IO15RSB0 A8 NC A9 NC A10 IO22RSB0 A11 IO23RSB0 A12 IO29RSB0 A13 IO35RSB0 A14 NC A15 NC A16 IO46RSB0 A17 IO48RSB0 A18 NC A19 NC A20 VCCIB0 A21 GND A22 GND B1 GND B2 VCCIB3 B3 NC B4 NC B5 NC B6 IO08RSB0 B7 IO12RSB0 B8 NC B9 NC B10 IO17RSB0 B11 NC B12 NC B13 IO36RSB0 B14 NC B15 NC B16 IO47RSB0 B17 IO49RSB0 B18 NC B19 NC B20 NC B21 VCCIB1 B22 GND C1 VCCIB3 C2 NC C3 NC C4 NC C5 GND C6 NC C7 NC C8 VCC C9 VCC C10 NC C11 NC C12 NC C13 NC C14 VCC C15 VCC C16 NC C17 NC C18 GND C19 NC C20 NC C21 NC C22 VCCIB1 D1 NC D2 NC D3 NC D4 GND D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 FG484 Pin Number A3P600 Function D7 GAB0/IO02RSB0 D8 IO11RSB0 D9 IO16RSB0 D10 IO18RSB0 D11 IO28RSB0 D12 IO34RSB0 D13 IO37RSB0 D14 IO41RSB0 D15 IO43RSB0 D16 GBB1/IO57RSB0 D17 GBA0/IO58RSB0 D18 GBA1/IO59RSB0 D19 GND D20 NC D21 NC D22 NC E1 NC E2 NC E3 GND E4 GAB2/IO173PDB3 E5 GAA2/IO174PDB3 E6 GNDQ E7 GAB1/IO03RSB0 E8 IO13RSB0 E9 IO14RSB0 E10 IO21RSB0 E11 IO27RSB0 E12 IO32RSB0 E13 IO38RSB0 E14 IO42RSB0 E15 GBC1/IO55RSB0 E16 GBB0/IO56RSB0 E17 IO52RSB0 E18 GBA2/IO60PDB1 E19 IO60NDB1 E20 GND FG484 Pin Number A3P600 Function

Pin Number A3P600 Function G13 IO40RSB0 G14 IO45RSB0 G15 GNDQ G16 IO50RSB0 G17 GBB2/IO61PPB1 G18 IO53RSB0 G19 IO63NDB1 G20 NC G21 NC G22 NC H1 NC H2 NC H3 VCC H4 IO166PDB3 H5 IO167NPB3 H6 IO172NDB3 H7 IO169NDB3 H8 VMV0 H9 VCCIB0 H10 VCCIB0 H11 IO25RSB0 H12 IO31RSB0 H13 VCCIB0 H14 VCCIB0 H15 VMV1 H16 GBC2/IO62PDB1 H17 IO67PPB1 H18 IO64PPB1 H19 IO66PDB1 H20 VCC H21 NC H22 NC J1 NC J2 NC J3 NC J4 IO166NDB3 FG484 Pin Number A3P600 Function J5 IO168NPB3 J6 IO167PPB3 J7 IO169PDB3 J8 VCCIB3 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC J14 GND J15 VCCIB1 J16 IO62NDB1 J17 IO64NPB1 J18 IO65PPB1 J19 IO66NDB1 J20 NC J21 IO68PDB1 J22 IO68NDB1 K1 IO157PDB3 K2 IO157NDB3 K3 NC K4 IO165NDB3 K5 IO165PDB3 K6 IO168PPB3 K7 GFC1/IO164PPB3 K8 VCCIB3 K9 VCC K10 GND K11 GND K12 GND K13 GND K14 VCC K15 VCCIB1 K16 GCC1/IO69PPB1 K17 IO65NPB1 K18 IO75PDB1 FG484 Pin Number A3P600 Function

ProASIC3 Flash Family FPGAs Revision 13 4-73 K19 IO75NDB1 K20 NC K21 IO76NDB1 K22 IO76PDB1 L1 NC L2 IO155PDB3 L3 NC L4 GFB0/IO163NPB3 L5 GFA0/IO162NDB3 L6 GFB1/IO163PPB3 L7 VCOMPLF L8 GFC0/IO164NPB3 L9 VCC L10 GND L11 GND L12 GND L13 GND L14 VCC L15 GCC0/IO69NPB1 L16 GCB1/IO70PPB1 L17 GCA0/IO71NPB1 L18 IO67NPB1 L19 GCB0/IO70NPB1 L20 IO77PDB1 L21 IO77NDB1 L22 IO78NPB1 M1 NC M2 IO155NDB3 M3 IO158NPB3 M4 GFA2/IO161PPB3 M5 GFA1/IO162PDB3 M6 VCCPLF M7 IO160NDB3 M8 GFB2/IO160PDB3 M9 VCC M10 GND FG484 Pin Number A3P600 Function M11 GND M12 GND M13 GND M14 VCC M15 GCB2/IO73PPB1 M16 GCA1/IO71PPB1 M17 GCC2/IO74PPB1 M18 IO80PPB1 M19 GCA2/IO72PDB1 M20 IO79PPB1 M21 IO78PPB1 M22 NC N1 IO154NDB3 N2 IO154PDB3 N3 NC N4 GFC2/IO159PDB3 N5 IO161NPB3 N6 IO156PPB3 N7 IO129RSB2 N8 VCCIB3 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB1 N16 IO73NPB1 N17 IO80NPB1 N18 IO74NPB1 N19 IO72NDB1 N20 NC N21 IO79NPB1 N22 NC P1 NC P2 IO153PDB3 FG484 Pin Number A3P600 Function P3 IO153NDB3 P4 IO159NDB3 P5 IO156NPB3 P6 IO151PPB3 P7 IO158PPB3 P8 VCCIB3 P9 GND P10 VCC P11 VCC P12 VCC P13 VCC P14 GND P15 VCCIB1 P16 GDB0/IO87NPB1 P17 IO85NDB1 P18 IO85PDB1 P19 IO84PDB1 P20 NC P21 IO81PDB1 P22 NC R1 NC R2 NC R3 VCC R4 IO150PDB3 R5 IO151NPB3 R6 IO147NPB3 R7 GEC0/IO146NPB3 R8 VMV3 R9 VCCIB2 R10 VCCIB2 R11 IO117RSB2 R12 IO110RSB2 R13 VCCIB2 R14 VCCIB2 R15 VMV2 R16 IO94RSB2 FG484 Pin Number A3P600 Function

Pin Number A3P600 Function U9 IO131RSB2 U10 IO124RSB2 U11 IO119RSB2 U12 IO107RSB2 U13 IO104RSB2 U14 IO97RSB2 U15 VMV1 U16 TCK U17 VPUMP U18 TRST U19 GDA0/IO88NDB1 U20 NC U21 IO83NDB1 U22 NC V1 NC V2 NC V3 GND V4 GEA1/IO144PDB3 V5 GEA0/IO144NDB3 V6 IO139RSB2 V7 GEC2/IO141RSB2 V8 IO132RSB2 V9 IO127RSB2 V10 IO121RSB2 V11 IO114RSB2 V12 IO109RSB2 V13 IO105RSB2 V14 IO98RSB2 V15 IO96RSB2 V16 GDB2/IO90RSB2 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 NC FG484 Pin Number A3P600 Function W1 NC W2 IO148PDB3 W3 NC W4 GND W5 IO137RSB2 W6 GEB2/IO142RSB2 W7 IO134RSB2 W8 IO125RSB2 W9 IO123RSB2 W10 IO118RSB2 W11 IO115RSB2 W12 IO111RSB2 W13 IO106RSB2 W14 IO102RSB2 W15 GDC2/IO91RSB2 W16 IO93RSB2 W17 GDA2/IO89RSB2 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB3 Y2 IO148NDB3 Y3 NC Y4 NC Y5 GND Y6 NC Y7 NC Y8 VCC Y9 VCC Y10 NC Y11 NC Y12 NC Y13 NC Y14 VCC FG484 Pin Number A3P600 Function

ProASIC3 Flash Family FPGAs Revision 13 4-75 Y15 VCC Y16 NC Y17 NC Y18 GND Y19 NC Y20 NC Y21 NC Y22 VCCIB1 AA1 GND AA2 VCCIB3 AA3 NC AA4 NC AA5 NC AA6 IO135RSB2 AA7 IO133RSB2 AA8 NC AA9 NC AA10 NC AA11 NC AA12 NC AA13 NC AA14 NC AA15 NC AA16 IO101RSB2 AA17 NC AA18 NC AA19 NC AA20 NC AA21 VCCIB1 AA22 GND AB1 GND AB2 GND AB3 VCCIB2 AB4 NC AB5 NC AB6 IO130RSB2 FG484 Pin Number A3P600 Function AB7 IO128RSB2 AB8 IO122RSB2 AB9 IO116RSB2 AB10 NC AB11 NC AB12 IO113RSB2 AB13 IO112RSB2 AB14 NC AB15 NC AB16 IO100RSB2 AB17 IO95RSB2 AB18 NC AB19 NC AB20 VCCIB2 AB21 GND AB22 GND FG484 Pin Number A3P600 Function

Pin Number A3P1000 Function A1 GND A2 GND A3 VCCIB0 A4 IO07RSB0 A5 IO09RSB0 A6 IO13RSB0 A7 IO18RSB0 A8 IO20RSB0 A9 IO26RSB0 A10 IO32RSB0 A11 IO40RSB0 A12 IO41RSB0 A13 IO53RSB0 A14 IO59RSB0 A15 IO64RSB0 A16 IO65RSB0 A17 IO67RSB0 A18 IO69RSB0 A19 NC A20 VCCIB0 A21 GND A22 GND B1 GND B2 VCCIB3 B3 NC B4 IO06RSB0 B5 IO08RSB0 B6 IO12RSB0 B7 IO15RSB0 B8 IO19RSB0 B9 IO24RSB0 B10 IO31RSB0 B11 IO39RSB0 B12 IO48RSB0 B13 IO54RSB0 B14 IO58RSB0 B15 IO63RSB0 B16 IO66RSB0 B17 IO68RSB0 B18 IO70RSB0 B19 NC B20 NC B21 VCCIB1 B22 GND C1 VCCIB3 C2 IO220PDB3 C3 NC C4 NC C5 GND C6 IO10RSB0 C7 IO14RSB0 C8 VCC C9 VCC C10 IO30RSB0 C11 IO37RSB0 C12 IO43RSB0 C13 NC C14 VCC C15 VCC C16 NC C17 NC C18 GND C19 NC C20 NC C21 NC C22 VCCIB1 D1 IO219PDB3 D2 IO220NDB3 D3 NC D4 GND D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 FG484 Pin Number A3P1000 Function D7 GAB0/IO02RSB0 D8 IO16RSB0 D9 IO22RSB0 D10 IO28RSB0 D11 IO35RSB0 D12 IO45RSB0 D13 IO50RSB0 D14 IO55RSB0 D15 IO61RSB0 D16 GBB1/IO75RSB0 D17 GBA0/IO76RSB0 D18 GBA1/IO77RSB0 D19 GND D20 NC D21 NC D22 NC E1 IO219NDB3 E2 NC E3 GND E4 GAB2/IO224PDB3 E5 GAA2/IO225PDB3 E6 GNDQ E7 GAB1/IO03RSB0 E8 IO17RSB0 E9 IO21RSB0 E10 IO27RSB0 E11 IO34RSB0 E12 IO44RSB0 E13 IO51RSB0 E14 IO57RSB0 E15 GBC1/IO73RSB0 E16 GBB0/IO74RSB0 E17 IO71RSB0 E18 GBA2/IO78PDB1 E19 IO81PDB1 E20 GND FG484 Pin Number A3P1000 Function

ProASIC3 Flash Family FPGAs Revision 13 4-77 E21 NC E22 IO84PDB1 F1 NC F2 IO215PDB3 F3 IO215NDB3 F4 IO224NDB3 F5 IO225NDB3 F6 VMV3 F7 IO11RSB0 F8 GAC0/IO04RSB0 F9 GAC1/IO05RSB0 F10 IO25RSB0 F11 IO36RSB0 F12 IO42RSB0 F13 IO49RSB0 F14 IO56RSB0 F15 GBC0/IO72RSB0 F16 IO62RSB0 F17 VMV0 F18 IO78NDB1 F19 IO81NDB1 F20 IO82PPB1 F21 NC F22 IO84NDB1 G1 IO214NDB3 G2 IO214PDB3 G3 NC G4 IO222NDB3 G5 IO222PDB3 G6 GAC2/IO223PDB3 G7 IO223NDB3 G8 GNDQ G9 IO23RSB0 G10 IO29RSB0 G11 IO33RSB0 G12 IO46RSB0 FG484 Pin Number A3P1000 Function G13 IO52RSB0 G14 IO60RSB0 G15 GNDQ G16 IO80NDB1 G17 GBB2/IO79PDB1 G18 IO79NDB1 G19 IO82NPB1 G20 IO85PDB1 G21 IO85NDB1 G22 NC H1 NC H2 NC H3 VCC H4 IO217PDB3 H5 IO218PDB3 H6 IO221NDB3 H7 IO221PDB3 H8 VMV0 H9 VCCIB0 H10 VCCIB0 H11 IO38RSB0 H12 IO47RSB0 H13 VCCIB0 H14 VCCIB0 H15 VMV1 H16 GBC2/IO80PDB1 H17 IO83PPB1 H18 IO86PPB1 H19 IO87PDB1 H20 VCC H21 NC H22 NC J1 IO212NDB3 J2 IO212PDB3 J3 NC J4 IO217NDB3 FG484 Pin Number A3P1000 Function J5 IO218NDB3 J6 IO216PDB3 J7 IO216NDB3 J8 VCCIB3 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC J14 GND J15 VCCIB1 J16 IO83NPB1 J17 IO86NPB1 J18 IO90PPB1 J19 IO87NDB1 J20 NC J21 IO89PDB1 J22 IO89NDB1 K1 IO211PDB3 K2 IO211NDB3 K3 NC K4 IO210PPB3 K5 IO213NDB3 K6 IO213PDB3 K7 GFC1/IO209PPB3 K8 VCCIB3 K9 VCC K10 GND K11 GND K12 GND K13 GND K14 VCC K15 VCCIB1 K16 GCC1/IO91PPB1 K17 IO90NPB1 K18 IO88PDB1 FG484 Pin Number A3P1000 Function

Pin Number A3P1000 Function M11 GND M12 GND M13 GND M14 VCC M15 GCB2/IO95PPB1 M16 GCA1/IO93PPB1 M17 GCC2/IO96PPB1 M18 IO100PPB1 M19 GCA2/IO94PPB1 M20 IO101PPB1 M21 IO99PPB1 M22 NC N1 IO201NDB3 N2 IO201PDB3 N3 NC N4 GFC2/IO204PDB3 N5 IO204NDB3 N6 IO203NDB3 N7 IO203PDB3 N8 VCCIB3 N9 VCC N10 GND N11 GND N12 GND N13 GND N14 VCC N15 VCCIB1 N16 IO95NPB1 N17 IO100NPB1 N18 IO102NDB1 N19 IO102PDB1 N20 NC N21 IO101NPB1 N22 IO103PDB1 P1 NC P2 IO199PDB3 FG484 Pin Number A3P1000 Function P3 IO199NDB3 P4 IO202NDB3 P5 IO202PDB3 P6 IO196PPB3 P7 IO193PPB3 P8 VCCIB3 P9 GND P10 VCC P11 VCC P12 VCC P13 VCC P14 GND P15 VCCIB1 P16 GDB0/IO112NPB1 P17 IO106NDB1 P18 IO106PDB1 P19 IO107PDB1 P20 NC P21 IO104PDB1 P22 IO103NDB1 R1 NC R2 IO197PPB3 R3 VCC R4 IO197NPB3 R5 IO196NPB3 R6 IO193NPB3 R7 GEC0/IO190NPB3 R8 VMV3 R9 VCCIB2 R10 VCCIB2 R11 IO147RSB2 R12 IO136RSB2 R13 VCCIB2 R14 VCCIB2 R15 VMV2 R16 IO110NDB1 FG484 Pin Number A3P1000 Function

ProASIC3 Flash Family FPGAs Revision 13 4-79 R17 GDB1/IO112PPB1 R18 GDC1/IO111PDB1 R19 IO107NDB1 R20 VCC R21 IO104NDB1 R22 IO105PDB1 T1 IO198PDB3 T2 IO198NDB3 T3 NC T4 IO194PPB3 T5 IO192PPB3 T6 GEC1/IO190PPB3 T7 IO192NPB3 T8 GNDQ T9 GEA2/IO187RSB2 T10 IO161RSB2 T11 IO155RSB2 T12 IO141RSB2 T13 IO129RSB2 T14 IO124RSB2 T15 GNDQ T16 IO110PDB1 T17 VJTAG T18 GDC0/IO111NDB1 T19 GDA1/IO113PDB1 T20 NC T21 IO108PDB1 T22 IO105NDB1 U1 IO195PDB3 U2 IO195NDB3 U3 IO194NPB3 U4 GEB1/IO189PDB3 U5 GEB0/IO189NDB3 U6 VMV2 U7 IO179RSB2 U8 IO171RSB2 FG484 Pin Number A3P1000 Function U9 IO165RSB2 U10 IO159RSB2 U11 IO151RSB2 U12 IO137RSB2 U13 IO134RSB2 U14 IO128RSB2 U15 VMV1 U16 TCK U17 VPUMP U18 TRST U19 GDA0/IO113NDB1 U20 NC U21 IO108NDB1 U22 IO109PDB1 V1 NC V2 NC V3 GND V4 GEA1/IO188PDB3 V5 GEA0/IO188NDB3 V6 IO184RSB2 V7 GEC2/IO185RSB2 V8 IO168RSB2 V9 IO163RSB2 V10 IO157RSB2 V11 IO149RSB2 V12 IO143RSB2 V13 IO138RSB2 V14 IO131RSB2 V15 IO125RSB2 V16 GDB2/IO115RSB2 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 IO109NDB1 FG484 Pin Number A3P1000 Function W1 NC W2 IO191PDB3 W3 NC W4 GND W5 IO183RSB2 W6 GEB2/IO186RSB2 W7 IO172RSB2 W8 IO170RSB2 W9 IO164RSB2 W10 IO158RSB2 W11 IO153RSB2 W12 IO142RSB2 W13 IO135RSB2 W14 IO130RSB2 W15 GDC2/IO116RSB2 W16 IO120RSB2 W17 GDA2/IO114RSB2 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB3 Y2 IO191NDB3 Y3 NC Y4 IO182RSB2 Y5 GND Y6 IO177RSB2 Y7 IO174RSB2 Y8 VCC Y9 VCC Y10 IO154RSB2 Y11 IO148RSB2 Y12 IO140RSB2 Y13 NC Y14 VCC FG484 Pin Number A3P1000 Function

Pin Number A3P1000 Function AB7 IO167RSB2 AB8 IO162RSB2 AB9 IO156RSB2 AB10 IO150RSB2 AB11 IO145RSB2 AB12 IO144RSB2 AB13 IO132RSB2 AB14 IO127RSB2 AB15 IO126RSB2 AB16 IO123RSB2 AB17 IO121RSB2 AB18 IO118RSB2 AB19 NC AB20 VCCIB2 AB21 GND AB22 GND FG484 Pin Number A3P1000 Function

5 – Datasheet Information List of Changes The following table lists critical changes that were made in each version of the ProASIC3 datasheet. Revision Changes Page Revision 13 (January 2013) The "ProASIC3 Ordering Information" section has been updated to mention "Y" as "Blank" mentioning "Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43104). 1-III Added a note to Table 2-2 • Recommended Operating Conditions 1,2 (SAR 43644): The programming temperature range supported is Tambient = 0°C to 85°C. 2-2 The note in Table 2-115 • ProASIC3 CCC/PLL Specification referring the reader to SmartGen was revised to refer instead to the online help associated with the core (SAR 42569). 2-89 Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip (SoC) throughout the document (SAR 40284). Live at Power-Up (LAPU) has been replaced with ’Instant On’. NA Revision 12 (September 2012) The "Security" section was modified to clarify that Microsemi does not support read-back of programmed data. 1-1 Added a Note stating " VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information." to Table 2-1 • Absolute Maximum Ratings and Table 2-2 • Recommended Operating Conditions 1,2 (SAR 38321). 2-1 2-2 Table 2-35 • Duration of Short Circuit Event Before Failure was revised to change the maximum temperature from 110°C to 100°C, with an example of six months instead of three months (SAR 37933). 2-30 In Table 2-93 • Minimum and Maximum DC Input and Output Levels , VIL and VIH were revised so that the maximum is 3. 6 V for all listed values of VCCI (SAR 28549). 2-67 Figure 2-36 • FIFO Read and Figure 2-37 • FIFO Write are new (SAR 28371). 2-98 The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" section in the "Pin Descriptions" chapter: "Within the package, the VMV plane is decoupled from the simultaneous switching no ise originating from the output buffer VCCI domain" and replaced with “Withi n the package, the VMV plane biases the input stage of the I/Os in the I/O banks” (SAR 38321). The datasheet mentions that "VMV pins must be connected to the corresponding VCCI pins" for an ESD enhancement. 3-1

(March 2012) Note indicating that A3P015 is not recommended for new designs has been added. The "Devices Not Recommended For New Designs" section is new (SAR 36760). I to IV The following sentence was removed from the "Advanced Architecture" section: "In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface" (SAR 34687). 1-3 The reference to guidelines for global spines and VersaTile rows, given in the "Global Clock Contribution—PCLOCK" section , was corrected to the "Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide (SAR 34734). 2-12 Figure 2-3 • Input Buffer Timing Model and Delays (example) has been modified for the DIN waveform; the Rise and Fall time label has been changed to tDIN (35430). 2-15 The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section (SAR 34883). 2-31 Added values for minimum pulse width and removed the FRMAX row from Table 2-107 through Table 2-114 in the "Global Tree Timing Characteristics" section. Use the software to determine the FRM AX for the device you are using (SARs 37279, 29269). 2-84 Revision 10 (September 2011) The "In-System Programming (I SP) and Security" section and "Security" section were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs impl ement the best security available in the industry (SAR 32865). I, 1-1 The value of 34 I/Os for the QN48 package in A3P030 was added to the "I/Os Per Package 1" section (SAR 33907). II The Y security option and Licensed DPA Logo were added to the "ProASIC3 Ordering Information" section. The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 32151). III The "Specifying I/O States During Programming" section is new (SAR 21281). 1-7 In Table 2-2 • Recommended Operating Conditions 1,2 , VPUMP programming voltage in programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45" (SAR 30666). It was corrected in v2.0 of this datasheet in April 2007 but inadvertently changed back to “3.0 to 3.6 V” in v1.4 in August 2009. The following changes were made to Table 2-2 • Recommended Operating Conditions 1,2: VCCPLL analog power supply (PLL) was changed from "1.4 to 1.6" to "1.425 to For VCCI and VMV, values for 3.3 V DC and 3.3 V DC Wide Range were corrected. The correct value for 3.3 V DC is "3.0 to 3.6 V" and the correct value for 3.3 V Wide Range is "2.7 to 3.6" (SAR 33848). 2-2 Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings was update to restore values to the correct co lumns. Previously the Slew Rate column was missing and data were aligned incorrectly (SAR 34034). 2-23 The notes regarding drive strength in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section and "3.3 V LVCMOS Wide Range" section tables were revised for clarification. They now state that the minimum drive strength for the default software configuration when run in wide range is ±100 µA. The drive strength displayed in software is support ed in normal range only. For a detailed I/V curve, refer to the IBIS models (SAR 25700). 2-21, 2-38 Revision Changes Page

Revision 9 (Oct 2009) Product Brief v1.3 The CS121 package was added to table under "Features and Benefits" section , the "I/Os Per Package 1" table, Table 1 • ProASIC3 FPGAs Package Sizes Dimensions, "ProASIC3 Ordering Information" , and the "Temperature Grade Offerings" table. I – IV "ProASIC3 Ordering Information" was revised to include the fact that some RoHS compliant packages are halogen-free. III Packaging v1.5 The "CS121" figure and pin table for A3P060 are new. 4-15 Revision 8 (Aug 2009) Product Brief v1.2 All references to M7 devices (CoreMP7) and speed grade –F were removed from this document. N/A Table 1-1 • I/O Standards Supported is new. 1-7 The "I/Os with Advanced I/O Standards" section was revised to add definitions of hot-swap and cold-sparing. 1-7 DC and Switching Characteristics v1.4 3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the datasheet. This affects all tables t hat contained 3.3 V LVCMOS and 1.2 V LVCMOS data. N/A IIL and I IH input leakage current information was added to all "Minimum and Maximum DC Input and Output Levels" tables. N/A –F was removed from the datasheet. The speed grade is no longer supported. N/A The notes in Table 2-2 • Recommended Operating Conditions 1,2 were updated. 2-2 Table 2-4 • Overshoot and Undershoot Limits 1 was updated. 2-3 Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays was updated. 2-6 In Table 2-116 • RAM4K9, the following specifications were removed: tWRO tCCKH 2-94 In Table 2-117 • RAM512X18, the following specifications were removed: tWRO tCCKH 2-96 In the title of Table 2-74 • 1.8 V LVCMOS High Slew , VCCI had a typo. It was changed from 3.0 V to 1.7 V. 2-57 Revision 7 (Feb 2009) Product Brief v1.1 The "Advanced I/O" section was revised to add a bullet regarding wide range power supply voltage support. I The table under "Features and Benefits" section, was updated to include a value for typical equivalent macrocells for A3P250. I The QN48 package was added to the following tables: the table under "Features and Benefits" section , "I/Os Per Package 1" "ProASIC3 FPGAs Package Sizes Dimensions", and "Temperature Grade Offerings". The number of singled-ended I/Os for QN68 was added to the "I/Os Per Package 1" table. N/A The "Wide Range I/O Support" section is new. 1-7 Revision 6 (Dec 2008) Packaging v1.4 The "QN48" section is new. 4-1 The "QN68" pin table for A3P030 is new. 4-5

ProASIC3 Flash Family FPGAs Revision 13 5-5 Revision 5 (Aug 2008) DC and Switching Characteristics v1.3 TJ, Maximum Junction Temperature, was changed to 100° from 110º in the "Thermal Characteristics" section and EQ 2. The calculated result of Maximum Power Allowed has thus changed to 1.463 W from 1.951 W. 2-5 Values for the A3P015 device were added to Table 2-7 • Quiescent Supply Current Characteristics. 2-6 Values for the A3P015 device were added to Table 2-14 • Different Components Contributing to Dynamic Power Co nsumption in ProASIC3 Devices . PAC14 was removed. Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices is new. 2-10, 2-11 The "PLL Contribution—PPLL" section was updated to change the P PLL formula from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT. 2-13 Both fall and rise values were included for t DDRISUD and tDDRIHD in Table 2-102 • Input DDR Propagation Delays. 2-77 Table 2-107 • A3P015 Global Resource is new. 2-85 The typical value for De lay Increments in Progr ammable Delay Blocks was changed from 160 to 200 in Table 2-115 • ProASIC3 CCC/PLL Specification. 2-89 Revision 4 (Jun 2008) DC and Switching Characteristics v1.2 Table note references were added to Table 2-2 • Recommended Operating Conditions 1,2, and the order of the table notes was changed. 2-2 The title for Table 2-4 • Overshoot and Undershoot Limits 1 was modified to remove "as measured on quiet I/Os." Table note 1 was revised to remove "estimated SSO density over cycles." Table note 2 was revised to remove "refers only to overshoot/undershoot limits for simultaneous switching I/Os. 2-3 The "Power per I/O Pin" section was updated to include 3 additional tables pertaining to input buffer power and output buffer power. 2-6 Table 2-29 • I/O Output Buffer Maximum Resistances 1 was revised to include values for 3.3 V PCI/PCI-X. 2-26 Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels was updated. 2-65 Revision 3 (Jun 2008) Packaging v1.3 Pin numbers were added to the "QN68" package diagram. Note 2 was added below the diagram. 4-3 The "QN132" package diagram was updated to include D1 to D4. In addition, note 1 was changed from top view to bottom view, and note 2 is new. 4-6 Revision 2 (Feb 2008) Product Brief v1.0 This document was divided into two sections and given a version number, starting at v1.0. The first section of the docum ent includes features , benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. N/A This document was updated to include A3P015 device information. QN68 is a new package that was added because it is offered in the A3P015. The following sections were updated: "Features and Benefits" "ProASIC3 Ordering Information" "Temperature Grade Offerings" "ProASIC3 Product Family" "A3P015 and A3P030" note "Introduction and Overview" N/A Revision Changes Page

Revision 2 (cont’d) The "ProASIC3 FPGAs Package Sizes Dimensions" table is new. II In the "ProASIC3 Ordering Information" , the QN package measurements were updated to include both 0.4 mm and 0.5 mm. III In the "General Description" section, the number of I/Os was updated from 288 to 300. 1-1 Packaging v1.2 The "QN68" section is new. 4-3 Revision 1 (Feb 2008) DC and Switching Characteristics v1.1 In Table 2-2 • Recommended Operating Conditions 1,2 , T J was listed in the symbol column and was incorrect. It was corrected and changed to TA. 2-2 In Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1, Maximum Operating Junction Temperature was changed from 110°C to 100°C for both commercial and industrial grades. 2-2 The "PLL Behavior at Brownout Condition" section is new. 2-3 In the "PLL Contribution—PPLL" section , the following was deleted: FCLKIN is the input clock frequency. 2-13 In Table 2-21 • Summary of Maximum and Minimum DC Input Levels , the note was incorrect. It previously said TJ and it was corrected and changed to TA. 2-20 In Table 2-115 • ProASIC3 CCC/PLL Specification, the SCLK parameter and note 1 are new. 2-89 Table 2-125 • JTAG 1532 was populated with the parameter data, which was not in the previous version of the document. 2-108 Packaging v1.1 In the "VQ100" A3P030 pin table, the function of pin 63 was incorrect and changed from IO39RSB0 to GDB0/IO38RSB0. 4-19 Revision 0 (Jan 2008) This document was previously in datasheet v2.2. As a result of moving to the handbook format, Actel has restarted the version numbers. N/A v2.2 (July 2007) The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3 Product Family, "I/Os Per Package", "Automot ive ProASIC3 Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix". i, ii, iii, iii, iv The words "ambient temperature" were added to the temperature range in the "Automotive ProASIC3 Ordering Informati on", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix" sections. iii, iv The T J parameter in Table 3-2 • Recommended Operating Conditions was changed to TA, ambient temperature, and table notes 4–6 were added. 3-2 v2.1 (May 2007) In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz). i The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i In the "I/Os Per Package" section, t he A3P030, A3P060, A3P125, ACP250, and A3P600 device I/Os were updated. ii Table 3-5 • Package Thermal Resistivities was updated with A3P1000 information. The note below the table is also new. 3-5 Revision Changes Page

ProASIC3 Flash Family FPGAs Revision 13 5-7 v2.0 (April 2007) In the "Packaging Tables", Ambient was deleted. ii The timing characteristics tables were updated. N/A The "PLL Macro" section was updated to add information on the VCO and PLL outputs during power-up. 2-15 The "PLL Macro" section was updated to include power-up information. 2-15 Table 2-11 • ProASIC3 CCC/PLL Specification was updated. 2-29 Figure 2-19 • Peak-to-Peak Jitter Definition is new. 2-18 The "SRAM and FIFO" section was updated with operation and timing requirement information. 2-21 The "RESET" section was updated with read and write information. 2-25 The "RESET" section was updated with read and write information. 2-25 The "Introduction" in the "Advanced I/Os" section was updated to include information on input and output buffers being disabled. 2-28 PCI-X 3.3 V was added to Table 2-11 • VCCI Voltages and Compatible Standards. 2-29 In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance descriptions were updated for levels 3 and 4. 2-34 Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices was updated. 2-64 Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V– Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum current was updated from 4 x 52.7 to 5 x 52.7. 2-40 The "VCCPLF PLL Supply Voltage" section was updated. 2-50 The "VPUMP Programming Supply Voltage" section was updated. 2-50 The "GL Globals" section was updated to include information about direct input into quadrant clocks. 2-51 VJTAG was deleted from the "TCK Test Clock" section. 2-51 In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK was changed to TCK in note 2. Note 3 was also updated. 2-51 Ambient was deleted from Table 3-2 • Recommended Operating Conditions. 3-2 Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on quiet I/Os)1. 3-2 In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951. 3-5 Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was updated. 3-6 Table 3-5 • Package Thermal Resistivities was updated. 3-5 Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industri al Conditions—Software Default Settings (Advanced) and Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were updated. 3-17 to 3- Revision Changes Page

ProASIC3 Flash Family FPGAs Revision 13 5-9 Advance v0.6 (continued) The "RESET" section was updated. 2-25 The "WCLK and RCLK" section was updated. 2-25 The "RESET" section was updated. 2-25 The "RESET" section was updated. 2-27 The "Introduction" of the "Advanced I/Os" section was updated. 2-28 The "I/O Banks" section is new. This section explains the following types of I/Os: Advanced Standard+ Standard Table 2-12 • Automotive ProASIC3 Bank Types Definition and Differences is new. This table describes the standards listed above. 2-29 PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2- 11 • VCCI Voltages and Compatible Standards 2-29 Table 2-13 • ProASIC3 I/O Features was updated. 2-30 The "Double Data Rate (DDR) Support" section was updated to include information concerning implementation of the feature. 2-32 The "Electrostatic Discharge (ESD) Protection" section was updated to include testing information. 2-35 Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices. 2-64 The notes in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices were updated. 2-64 The "Simultaneous Switching Outputs (SSO s) and Printed Circuit Board Layout" section is new. 2-41 A footnote was added to Table 2-14 • Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum drive strength and high slew selected). 2-30 Table 2-18 • Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications 2-45 Table 2-50 • ProASIC3 Output Drive (O UT_DRIVE) for Standard I/O Bank Type (A3P030 device) 2-83 Table 2-51 • ProASIC3 Output Drive for Standard+ I/O Bank Type was updated. 2-84 Table 2-54 • ProASIC3 Output Drive for Advanced I/O Bank Type was updated. 2-84 The "x" was updated in the "User I/O Naming Convention" section. 2-48 The "VCC Core Supply Voltage" pin description was updated. 2-50 The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include information concerning leaving the pin unconnected. 2-50 The "VJTAG JTAG Supply Voltage" pin description was updated. 2-50 The "VPUMP Programming Supply Voltage" pin description was updated to include information on what happens when the pin is tied to ground. 2-50 The "I/O User Input/Output" pin description was updated to include information on what happens when the pin is unused. 2-50 The "JTAG Pins" section was updated to include information on what happens when the pin is unused. 2-51 Revision Changes Page

Advance v0.6 (continued) The "Programming" section was updated to include information concerning serialization. 2-53 The "JTAG 1532" section was updated to include SAMPLE/PRELOAD information. 2-54 "DC and Switching Characteristics" chapter was updated with new information. 3-1 The A3P060 "100-Pin VQFP" pin table was updated. 4-13 The A3P125 "100-Pin VQFP" pin table was updated. 4-13 The A3P060 "144-Pin TQFP" pin table was updated. 4-16 The A3P125 "144-Pin TQFP" pin table was updated. 4-18 The A3P125 "208-Pin PQFP" pin table was updated. 4-21 The A3P400 "208-Pin PQFP" pin table was updated. 4-25 The A3P060 "144-Pin FBGA" pin table was updated. 4-32 The A3P125 "144-Pin FBGA" pin table is new. 4-34 The A3P400 "144-Pin FBGA" is new. 4-38 The A3P400 "256-Pin FBGA" was updated. 4-48 The A3P1000 "256-Pin FBGA" was updated. 4-54 The A3P400 "484-Pin FBGA" was updated. 4-58 The A3P1000 "484-Pin FBGA" was updated. 4-68 The A3P250 "100-Pin VQFP*" pin table was updated. 4-14 The A3P250 "208-Pin PQFP*" pin table was updated. 4-23 The A3P1000 "208-Pin PQFP*" pin table was updated. 4-29 The A3P250 "144-Pin FBGA*" pin table was updated. 4-36 The A3P1000 "144-Pin FBGA*" pin table was updated. 4-32 The A3P250 "256-Pin FBGA*" pin table was updated. 4-45 The A3P1000 "256-Pin FBGA*" pin table was updated. 4-54 The A3P1000 "484-Pin FBGA*" pin table was updated. 4-68 Advance v0.5 (November 2005) The "I/Os Per Package" table was updated for the following devices and packages: Device Package A3P250/M7ACP250 VQ100 A3P250/M7ACP250 FG144 A3P1000 FG256 ii Advance v0.4 M7 device information is new. N/A The I/O counts in the "I/Os Per Package" table were updated. ii Advance v0.3 The "I/Os Per Package" table was updated. ii M7 device information is new. N/A Table 2-4 • ProASIC3 Globals/Spines/Rows by Device was updated to include the number or rows in each top or bottom spine. 2-16 EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options. 2-24 Revision Changes Page

Advance v0.2, (continued) Table 2-43 was updated. 2-64 Table 2-18 was updated. 2-45 Pin descriptions in the "JTAG Pins" section were updated. 2-51 The "User I/O Naming Convention" section was updated. 2-48 Table 3-7 was updated. 3-6 The "Methodology" section was updated. 3-10 Table 3-40 and Table 3-39 were updated. 3-33,3-32 The A3P250 "100-Pin VQFP*" pin table was updated. 4-14 The A3P250 "208-Pin PQFP*" pin table was updated. 4-23 The A3P1000 "208-Pin PQFP*" pin table was updated. 4-29 The A3P250 "144-Pin FBGA*" pin table was updated. 4-36 The A3P1000 "144-Pin FBGA*" pin table was updated. 4-32 The A3P250 "256-Pin FBGA*" pin table was updated. 4-45 The A3P1000 "256-Pin FBGA*" pin table was updated. 4-54 The A3P1000 "484-Pin FBGA*" pin table was updated. 4-68 Revision Changes Page

ProASIC3 Flash Family FPGAs Revision 13 5-13 Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "ProASIC3 Device Status" table on page III , is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a data sheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, bu t not for production. This label only applies to the DC and Switching Characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subj ect to the Export Administ ration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information.

51700097-13/01.13 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquarter ed in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996

Product Information

A3P1000-FG256 specifications and overview.

Summary

ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Description

ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Source title A3P1000-FG256 Datasheet(PDF) - Microsemi Corporation

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