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Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 33
Technical content
Datasheet sections
- 1 Pinout configuration and function
- 1.1 Pin connections
- 1.2 Functional pin description
- 2 Electrical characteristics
- 2.1 Ratings
- 2.1.1 Maximum ratings
- 2.1.2 Lifetime
- 2.1.3 ESD protection characteristics
- 2.1.4 Moisture sensitivity level
- 2.2 Operating characteristics
- 2.2.1 Nominal DAC settings
- 2.2.2 Functional tests
- 2.2.3 Wideband ruggedness
- 2.2.4 Typical performance
- 3 Register map and OTP memory
- 3.1 One-time programmable memory
- 3.2 Register map
- 4 Power supply sequence
- 5 Autobias functionality
- 5.1 General overview
- 5.2 Operational overview
- 5.3 Tx enable control
- 5.4 Sense_DAC
- 5.5 VGS_DAC
- 5.6 Engineering Mode (EM)
- 6 Ordering information
- 7 Component layout and parts list
- 7.1 Component layout
- 7.2 Component designations and values
- 8 Temperature sensor
- 9 Communication interfaces
- 9.1 SPI
- 9.1.1 SPI timing diagram
- 9.1.2 SPI instruction set definition
- 9.2 I2C
- 9.2.1 I2C addressing
- 9.2.2 I2C instruction set
- 9.2.3 I2C Device ID Read instruction
- 9.3 I2C electrical specification and timing for I/O
- 9.3.1 I2C SCLK and SDA characteristics
- 9.3.2 I2C bus electrical characteristics
- 10 Design considerations
- 10.1 Power on sequence
- 10.2 Programming guidelines to avoid hardware
- 10.3 Group programming
- 11 Product marking
- 12 Package information
- 13 Product software and tools
- 14 Failure analysis
- 15 Revision history
Features
- Advanced high performance in-package Doherty
- Fully matched (50 ohm input/output, DC blocked)
- Designed for low complexity analog or digital linearization systems
- Autobias on power up
- Temperature sensing
- Digital interface (I2C or SPI)
- Embedded registers and DACs for setting bias conditions
- Tx Enable control pin for TDD operation A3M36SL039I A3M36SL039S 3400–3800 MHz, 29 dB, 8 W Avg. Airfast Power Amplifier Module with Autobias Control 10 mm × 8 mm Module A3M36SL039 Airfast Power Amplifier Module with Autobias Control Rev. 0 — December 2021 Data Sheet: Technical Data
1 Pinout configuration and function
1.1 Pin connections
Figure 1. Pin connections
Electrical characteristics
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 4 / 33
1.2 Functional pin description
Table 1. Functional pin description
1 VDC2 Carrier Drain Supply, Stage 2
2 VDC1 Carrier Drain Supply, Stage 1
7 RFin RF Input Signal @ 50 Ohm
9 A1 I2C Address A1 (tri-state, tie to 5 V, tie to ground or leave
10 A0 I2C Address A0 (tri-state, tie to 5 V, tie to ground or leave
16 VCC_+5V 5 V VCC Power Source for Autobias Chip
19 VDP1 Peaking Drain Supply, Stage 1
20 VDP2 Peaking Drain Supply, Stage 2
24 RFout RF Output Signal @ 50 Ohm
2 Electrical characteristics
2.1 Ratings
2.1.1 Maximum ratings
Table 2. Maximum ratings
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 5 / 33
2.1.2 Lifetime
Table 3. Lifetime
2.1.3 ESD protection characteristics
Table 4. Lifetime ESD protection characteristics
2.1.4 Moisture sensitivity level
Table 5. Moisture sensitivity level
2.2 Operating characteristics
2.2.1 Nominal DAC settings
Table 6. Nominal DAC settings1
- Each side of device measured separately.
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 6 / 33
2.2.2 Functional tests
Table 7. Functional tests DAC Settings, Tx_EN = High, Pout = 8 W Avg., 1-tone CW, f = 3400 MHz. DAC Settings, Tx_EN = High, Pout = 8 W Avg., 1-tone CW, f = 3800 MHz.
2.2.3 Wideband ruggedness
Table 8. Wideband ruggedness
2.2.4 Typical performance
Table 9. Typical performance
- Part input and output matched to 50 ohms.
- ATE is a socketed test environment.
- All data measured in fixture with device soldered in NXP reference circuit.
- Gain flatness = Max(G(fLow to fHigh)) – Min(G(fLow to fHigh))
Register map and OTP memory A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 7 / 33
3 Register map and OTP memory
3.1 One-time programmable memory
The A3M36SL039 contains a one-time programmable (OTP) memory array that is used to store register values for the integrated autobias controller. The data sheet IDQ target values are determined and programmed into the OTP memory during NXP’s production testing. When programmed, the OTP memory is used to store these values for automatic loading into autobias registers at power on or reset. These values can be overwritten using the Engineering Mode (EM) sequence; however, the overwritten values do not persist after a power cycle or a reset. The OTP memory can be programmed only by NXP during the manufacturing process and cannot be changed by the user. The values in OTP memory have been selected to allow the device to operate in a wide variety of applications.
3.2 Register map
There are nine 8-bit user accessible registers available in the A3M36SL039. The register mapping is listed in Table 10. Address 0 RW register is designed to control soft reset, refresh OTP and read the chip version. Address 1−6 registers are RW and/or OTP controlled and provide settings for the two RF transistor group DACs. Address 15 is read only for temperature sense functionality. Address 17 is a virtual write only register for enabling Engineering Mode.
Table 10. Register map
0 RW System_Reg N/A Soft
1 OTP
2 OTP
3 OTP
4 OTP
5 OTP
6 OTP
15 RO Temp_ADC Temperature Sensor [7:0] —
17 Virtual W
Table 11. Register overview and bit description
0 System_Reg 7 Not available N/A N/A N/A N/A
0 No RW
4 Not available N/A N/A N/A
1 A_Sense_DAC 6–7 Not available N/A N/A N/A
DS across the reference device. and maximum value is 6'b111111.
2 Yes
2 A_VGS1_DAC 0–7 Sets 8-bit DAC logic value for carrier
3 A_VGS2_DAC 0–7 Sets 8-bit DAC logic value for carrier
Table 11. Register overview and bit description (continued)
4 B_Sense_DAC 6–7 Not available N/A N/A N/A No
VDS across the reference device. and maximum value is 6'b111111.
5 B_VGS3_DAC 0–7 Sets 8-bit DAC logic value for
6 B_VGS4_DAC 0–7 Sets 8-bit DAC logic value for
15 Temp_ADC 0–7 Temperature sensor 8-bit DAC
8'hFF is highest temperature.
16 Reserved N/A Not available N/A N/A N/A No
- At power on or reset, OTP values set by NXP are automatically loaded into registers indicated with a “Yes” in the
only if OTP has not been programmed to prevent damage to the device.
- Register can be read at any time. Can write to register only when in Engineering Mode (EM).
4 Power supply sequence
- SPI/I2C interface is active
- VDP1,VDP2,VDC1,VDC2 power up
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 11 / 33 Power Down Sequence 1. VDP1,VDP2,VDC1,VDC2 power down 2. SPI/I2C interface deactivated 3. VCC_+5V: 5 V power down Note: All digital interfaces (SDA, SCLK, CS_B,Tx_EN) are 1.8 V logic.
5 Autobias functionality
5.1 General overview
After power up, the integrated bias controller develops and applies a thermally compensated quiescent bias voltage to the gate of each of the four RF transistors contained within the power amplifier module (PAM) based on the preset OTP values. See Section 3.1 for more information on the OTP memory. This achieves optimal RF performance over the full temperature range. The standard SPI or I2C interface can be used to read the temperature sensor and overwrite preset DAC values. The device can be used without the programming interface. The thermal compensation circuit is analog and not programmable; however, the preset DAC values can be overwritten to provide an alternate thermal compensation scheme via the SPI or I2C interface. This section describes the operation and programming of the bias controller.
5.2 Operational overview
Figure 2 shows a detailed view of the carrier side (Group A) autobias controller. The peaking side (Group B) controller is a duplicate of the carrier; however, the RF transistor peripheries and quiescent operating points will be different as required by the Doherty operation. The module contains four RF LDMOS field-effect transistors (FET) consisting of a driver and final for the carrier amplifier (on a single IC die) and a driver and final for the peaking amplifier (on a single IC die). Each IC die also contains a small periphery reference FET that is designed to match the properties of the larger RF transistors with regard to part-to-part process and temperature-dependent variations. The bias controller interfaces with each of the RF FETs and provides flexibility to control the biasing of each transistor independently. The bias controller operates by establishing a known current through the reference FET typically in the range of 1−2 mA per reference FET. This in turn establishes a gate-source operating voltage by sensing the voltage drop across an integrated, high tolerance resistor placed between VCC (5 V) and the reference device drain terminal. The bias controller VCC_+5V pin should be operated from a 5 V supply with tolerance of ±5%. The reference voltage across the precision resistor R1 is compared to a voltage programmed in the bias controller (A_Sense_DAC and B_Sense_DAC), thereby providing fine incremental adjustment to the default bias current of the reference FET. Because the reference FET and RF FET are manufactured on the same die in close proximity, they exhibit similar process and temperature dependencies.
Figure 2. Block diagram of carrier (A) autobias functionality. Peaking (B) autobias functionality is identical. final and carrier PA driver directly, or reduced by values set in the A_VGS1_DAC and A_VGS2_DAC to the DAC floor voltage.
5.3 Tx enable control
operation. In Tx OFF mode, RF FET device gates are grounded shutting them OFF. Table 12. TX_EN Off-State Typical Currents
5.4 Sense_DAC
only programmable in Engineering Mode. have been optimized for best power, linearity and efficiency tradeoffs.
Ordering information
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5.5 VGS_DAC
The VGS_DAC voltage is determined via the Sense_DAC setting, creating the top end or ceiling of the VGS_DAC voltage range and a fixed offset voltage creating the bottom end or floor of the VGS_DAC voltage range. With a decimal VGS_DAC setting of 0, the gate voltage developed on the reference FET is buffered with minimum offset to the gates of the RF transistors in the carrier amplifier. As the VGS_DAC value increases, the voltage applied to the gates of the RF transistors decreases, which also reduces IDQ. This allows the operating point of the four RF devices to be set to any desired value, from Class AB to Class C. The reference FETs and RF FETs exhibit approximately the same current density (that is, IDQ/mm gate width). It is important to note that, because the reference device and RF transistors are manufactured on the same die in close proximity, they exhibit similar process and temperature dependencies. Both the peaking amplifier and the carrier amplifier operate in the same way with regard to the reference device and the RF transistors.
5.6 Engineering Mode (EM)
Flexibility exists to overwrite the OTP memory values, if needed. A special Engineering Mode (EM) is available to allow the user to overwrite data that has been placed into the OTP memory space. To enter EM, issue the write address d’17 command with the predefined EM passcode (see Table 10). After entering EM, all DAC OTP registers (address 1–6) can be overwritten with the normal I2C/SPI write instruction. This interface programmed value will be valid so long the VCC supply power is maintained. The VCC power cycle will load OTP programmed DAC settings again. If the user writes the address d’17 register with any value other than the passcode, EM will automatically exit.
6 Ordering information
Table 13. Ordering information
7 Component layout and parts list
7.1 Component layout
Figure 3. A3M36SL039 reference circuit component layout
7.2 Component designations and values
Table 14. A3M36SL039 reference circuit component designations and values Note: Component numbers C3, C5, C6, C7, C8, C9, C11, C13 and C16 are intentionally omitted.
8 Temperature sensor
A plot of this equation is shown in Figure 4. Figure 4. Die temperature versus ADC code Table 15. Temperature sensor accuracy
9 Communication interfaces
shipment. For I2C functionality, order part number A3M36SL039I. For SPI functionality, order part number A3M36SL039S.
9.1 SPI
The A3M36SL039S can be programmed and the Tx bias settings and temperature read through the 3-pin SPI interface.
9.1.1 SPI timing diagram
The SPI interface timing of A3M36SL039S complies with SPI mode3 as shown in Figure 5. Figure 5. Serial interface timing diagram Table 16. Serial interface timing specification
9.1.2 SPI instruction set definition
defined as the register address that is to be accessed.
Figure 6. SPI instruction sets diagram
- R/W read = 1, write = 0
- N1, N0 o 2’b00 1 byte o 2’b01 2 bytes o 2’b10 3 bytes o 2’b11 4 bytes
- A4, A3, A2, A1, A0 decode for address 0–15
- MSB sent first, LSB last
9.2 I2C
I2C standard mode with bit rate up to 100 Kbit/s.
9.2.1 I2C addressing
Table 17. I2C 7-bit address assignment
0 Z 1000 000
1 Z 1000 110
9.2.2 I2C instruction set
Figure 7. I2C Write instruction Figure 8. I2C Read instruction
Figure 9. I2C Write and Read combination sequence
9.2.3 I2C Device ID Read instruction
- The leader sends the Reserved Device ID I2C bus address followed by the R/W bit set to ‘0’ (write): ‘1111 1000’.
- The leader sends the I2C bus follower address of the follower device it must identify. The LSB is a “don’t care” value. Only
one device must acknowledge this byte (the device that has the I2C bus follower address).
- The leader sends a RESTART condition.
follower state machine and the Device ID read cannot be performed.
- The leader sends the Reserved Device ID I2C bus address followed by the R/W bit set to ‘1’ (read): ‘1111 1001’.
- The Device ID read can be completed, starting with the 12 manufacturer bits (first byte + four MSBs of the second byte),
die revision bits (three LSBs of the third byte).
- The leader ends the reading sequence by NACKing the last byte, thus resetting the follower device state machine and
allowing the leader to send the STOP condition. Remark: The reading of the Device ID can be stopped anytime by sending a NACK.
Table 18. I2C Device Read instructions
9.3 I2C electrical specification and timing for I/O stages and bus lines
Figure 10. I2C electrical specification and timing for I/O stages and bus lines
9.3.1 I2C SCLK and SDA characteristics
Table 19. I2C SCLK and SDA
- Note: All values referred to VIH(min) (0.3 VDD) and VIL(max)(0.7 VDD) level.
- tHD:DAT is the data hold time that is measured from the falling edge of SCLK and applies to data in transmission and the
- A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSU:DAT 250 ns must then
Acknowledge timing must meet this setup time.
- A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCLK
signal) to bridge the undefined region of the falling edge of SCLK.
- The maximum tHD:DAT could be 3.45 µs and 0.9 µs for standard mode and fast mode, but must be less than the maximum
- tVD;ACK = time for Acknowledgement signal from SCLK LOW to SDA output (HIGH or LOW, depending on which one is
- tVD:DAT = time for data signal from SCLK LOW to SDA output (HIGH or LOW, depending on which one is longer).
9.3.2 I2C bus electrical characteristics
Table 20. I2C SCLK and SDA
- VDD in this table refers to 1.8 V provided by the Leader.
- The maximum tf for the SDA and SCLK bus lines is specified at 300 ns. This allows series protection resistors to be
connected in between the SDA and the SCLK pins and the SCLK bus lines without exceeding the maximum specified tf.
10 Design considerations
10.1 Power on sequence
Figure 11. Power on sequence timing diagram
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10.2 Programming guidelines to avoid hardware failure or damage
Users must be aware of the following guidelines to avoid potential hardware failure or damage.
- Do not program the Refresh OTP and Soft Reset bits to a 1 state at the same time.
- Soft Reset bit will reset Engineering Mode (EM).
- The Soft Reset bit is easily accessible; therefore, be cautious of the accidental reset.
- Tx_EN must not be active during an OTP refresh or during Engineering Mode.
10.3 Group programming
A common way of grouping A3M36SL039 modules is with parallel data inputs and unique chip CS_B connectivity. In this case, each module can be independently controlled and programmed by its individual CS_B, which has more flexibility to program each module separately as Figure 12 illustrates.
Figure 12. Parallel connectivity of grouping
11 Product marking
Figure 13. Product marking
Package information
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 26 / 33 Figure 14. Package information
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 27 / 33 Figure 14 . Package information
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 28 / 33 Figure 14 . Package information
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 29 / 33 Figure 14 . Package information
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 30 / 33 Figure 14 . Package information
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 31 / 33 Figure 14 . Package information
Revision history
A3M36SL039 Airfast Power Amplifier Module with Autobias Control , Rev. 0, December 2021 Data Sheet: Technical Data 32 / 33
13 Product software and tools
Refer to the following resources to aid your design process. Development Software
- Test, Debug and Analyzer Software Development Tools
- Printed Circuit Boards
14 Failure analysis
At this time, because of the physical characteristics of the part, failure analysis is limited to electrical signature analysis. In cases where NXP is contractually obligated to perform failure analysis (FA) services, full FA may be performed by third party vendors with moderate success. For updates contact your local NXP Sales Office. The following table summarizes revisions to this document. Table 21. Revision history
Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. NXP, the NXP logo and Airfast are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © NXP B.V. 2021 All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: December 2021 Document identifier: A3M36SL039