A3G4250DTR STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Pin description
- 2 Mechanical and electrical characteristics
- 2.1 Mechanical characteristics
- 2.2 Electrical characteristics
- 2.3 Temperature sensor characteristics
- 2.4 Communication interface characteristics
- 2.4.1 SPI - serial peripheral interface
- 2.4.2 I2C - inter IC control interface
- 2.5 Absolute maximum ratings
- 2.6 Terminology
- 2.6.1 Sensitivity
- 2.6.2 Zero-rate level
- 2.6.3 Stability over temperature and time
- 2.7 Soldering information
- 3 Main digital blocks
- 3.1 Block diagram
- 3.2 FIFO
- 3.2.1 Bypass mode
- 3.2.2 FIFO mode
- 3.2.3 Stream mode
- 3.2.4 Retrieve data from FIFO
- 4 Application hints
- 5 Digital interfaces
- 5.1 I2C serial interface
- 5.1.1 I2C operation
- 5.2 SPI bus interface
- 5.2.1 SPI read
- 5.2.2 SPI write
Features
■ Wide supply voltage: 2.4 V to 3.6 V ■ ±245 dps full scale ■ I2C/SPI digital output interface ■ 16-bit rate value data output ■ 8-bit temperature data output ■ Two digital output lines (interrupt and data ready) ■ Integrated low and high-pass filters with user- selectable bandwidth ■ Ultra-stable over temperature and time ■ Low-voltage-compatible IOs (1.8 V) ■ Embedded power-down and sleep mode ■ Embedded temperature sensor ■ Embedded FIFO ■ High shock survivability ■ Extended operating temperature range (-40 °C to +85 °C) ■ ECOPACK® RoHS and “Green” compliant ■ AEC-Q100 qualification
Applications
■ In-dash car navigation ■ Telematics, e-Tolling ■ Motion control with MMI (man-machine interface) ■ Appliances and robotics
Description
The A3G4250D is a low-power 3-axis angular rate sensor able to provide unprecedented stability at zero rate level and sensitivity over temperature and time. It includes a sensing element and an IC interface capable of providing the measured angular rate to the external world through a standard SPI digital interface. An I 2C-compatible interface is also available. The sensing element is manufactured using a dedicated micro-machining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers. The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The A3G4250D has a full scale of ±245 dps and is capable of measuring rates with a user- selectable bandwidth. The A3G4250D is available in a plastic land grid array (LGA) package and can operate within a temperature range of -40 °C to +85 °C. LGA-16 (4x4x1.1 mm3) Table 1. Device summary
1 Block diagram and pin description
Figure 1. Block diagram signal is filtered and appears as a digital signal at the output.
1.1 Pin description
Figure 2. Pin connection
Figure 3. A3G4250D external low-pass filter values (a) Table 2. Pin description
1 Vdd_IO Power supply for I/O pins
2 SCL
4 SDO
6 DRDY/INT2 Data ready/FIFO interrupt
7 INT1 Programmable interrupt
8 Reserved Connect to GND
9 Reserved Connect to GND
10 Reserved Connect to GND
11 Reserved Connect to GND
12 Reserved Connect to GND
13 GND 0 V supply
14 PLLFILT Phase-locked loop filter (see Figure 3)
15 Reserved Connect to Vdd
16 Vdd Power supply
a. Pin 14 PLLFILT maximum voltage level is equal to Vdd.
Table 3. Filter values
2 Mechanical and electrical characteristics
2.1 Mechanical characteristics
b. The product is factory calibrated at 3.0 V. The operational power supply range is specified in Table 5. Table 4. Mechanical characteristics
- Typical specifications are not guar anteed; typical values at +25 °C.
- Across temperature and after MSL3 preconditioning.
2.2 Electrical characteristics
2.3 Temperature sensor characteristics
@ Vdd = 3.0 V, T = 25 °C, unless otherwise noted(d). c. The product is factory calibrated at 3.0 V. Table 5. Electrical characteristics
- Typical specifications are not guar anteed; typical values at +25 °C.
- It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
- Sleep mode introduces a faster turn-on time compared to power-down mode.
d. The product is factory calibrated at 3.0 V. Table 6. Temp. sensor characteristics
- Typical specifications are not guar anteed; typical values at +25 °C.
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top. Figure 4. SPI slave timing diagram (e) Table 7. SPI slave timing values
- Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not
e. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
2.4.2 I 2C - inter IC control interface
Subject to general operating conditions for Vdd and Top. Figure 5. I 2C slave timing diagram(f) Table 8. I 2C slave timing values
- Data based on standard I 2C protocol requirement; not tested in production.
f. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
2.5 Absolute maximum ratings
Table 9. Absolute maximum ratings
A3G4250D Mechanical and electrical characteristics Doc 022768 Rev 3 15/44
2.6 Terminology
2.6.1 Sensitivity
An angular rate gyroscope is a device that produces a positive-going digital output for counter-clockwise rotation around the sensitive axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time.
2.6.2 Zero-rate level
The zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and, therefore, the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time.
2.6.3 Stability over temperature and time
Thanks to the unique single-driving mass approach and optimized design, ST gyroscopes are able to guarantee a perfect match of the MEMS mechanical mass and the ASIC interface, and deliver unprecedented levels of stability over temperature and time. With the zero-rate level and sensitivity performances, up to ten times better than equivalent products currently available on the market, the A3G4250D allows the user to avoid any further compensation and calibration during production for a faster time to market, easy application implementation, higher performance, and cost saving.
2.7 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “pin 1 indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/
3 Main digital blocks
3.1 Block diagram
Figure 6. Block diagram
3.2 FIFO
five different modes. Each mode is selected by the FIFO_MODE bits in FIFO_CTRL_REG. be configured to WTM4: 0 in FIFO_CTRL_REG.
3.2.1 Bypass mode
slots are empty. When new data is available, the old data is overwritten.
Figure 7. Bypass mode
3.2.2 FIFO mode
to write FIFO_CTRL_REG back to bypass mode. FIFO mode is represented in Figure 8.
Figure 8. FIFO mode
3.2.3 Stream mode
generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3). Stream mode is represented in Figure 9.
Figure 9. Stream mode
3.2.4 Retrieve data from FIFO
information from addr OUT_X_L.
- If reading is synchronous, all data should be acquired within one ODR cycle
- If reading is asynchronous, an appropriate FIFO access sequence must be applied:
Figure 10. FIFO access sequence in asynchronous mode If the above sequence is not followed, the acquisition from FIFO may lead to corrupted data.
4 Application hints
Figure 11. A3G4250D electrical connections and external component values as near as possible to the device (common design practice). pass filter component values. Table 10. PLL low-pass filter component values
5 Digital interfaces
CS line must be tied high (i.e., connected to Vdd_IO).
5.1 I 2C serial interface
content can also be read back. The relevant I2C terminology is given in the table below. resistor. When the bus is free both the lines are high. Table 11. Serial interface pin description Table 12. I 2C terminology
5.1.1 I 2C operation
SAD+read/write bit pattern is composed, listing all the possible configurations. Table 13. SAD+read/write patterns Table 14. Transfer when master is writing one byte to slave
terminated by the generation of a STOP (SP) condition. address of the first register to be read.
5.2 SPI bus interface
interface interacts with the external world through 4 wires: CS, SPC, SDI, and SDO. Table 15. Transfer when master is writing multiple bytes to slave Table 16. Transfer when master is receiving (reading) one byte of data from slave Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave
Figure 12. Read and write protocol of SPC and should be captured at the rising edge of SPC. from the device is read. In the latter case, the chip drives SDO at the start of bit 8. Bit 1: MS bit. When 0, the address remains unchanged in multiple read/write commands. When 1, the address is auto-incremented in multiple read/write commands. Bit 2-7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first). Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). bit is 1, the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
5.2.1 SPI read
Figure 13. SPI read protocol
performed by adding blocks of 8 clock pulses to the previous one. Bit 0: READ bit. The value is 1. Bit 2-7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Figure 14. Multiple byte SPI read protocol (2-byte example)
5.2.2 SPI write
Figure 15. SPI write protocol performed by adding blocks of 8 clock pulses to the previous one. Bit 0: WRITE bit. The value is 0. Bit 2 -7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DI(7:0) (write mode). This is the data that is written to the device (MSb first).
Figure 16. Multiple byte SPI wr ite protocol (2-byte example)
5.2.3 SPI read in 3-wire mode
Figure 17. SPI read protocol in 3-wire mode Bit 0: READ bit. The value is 1. Bit 2-7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). The multiple read command is also available in 3-wire mode.
6 Output register mapping
Table 18. Register address map
Output register mapping A3G4250D 30/44 Doc 022768 Rev 3 Registers marked as Reserved must not be changed. Writing to those registers may change calibration data and therefore lead to a non-proper working device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
7 Register description
the data through the serial interface.
7.1 WHO_AM_I (0Fh)
Device identification register.
7.2 CTRL_REG1 (20h)
DR<1:0> is used to set ODR selection. BW <1:0> is used to set Bandwidth selection. Table 19. WHO_AM_I register Table 20. CTRL_REG1 register Table 21. CTRL_REG1 description Table 22. DR and BW configuration setting
(power-down / normal / sleep mode) according to the following table.
7.3 CTRL_REG2 (21h)
Table 23. Power mode selection configuration Table 22. DR and BW configuration setting (continued) Table 24. CTRL_REG2 register
- Value loaded at boot. This value must not be changed.
Table 25. CTRL_REG2 description Table 26. High-pass filter mode configuration
7.4 CTRL_REG3 (22h)
7.5 CTRL_REG4 (23h)
Table 27. High-pass filter cut-off frequency configuration [Hz] Table 28. CTRL_REG1 register Table 29. CTRL_REG3 description Table 30. CTRL_REG4 register
7.6 CTRL_REG5 (24h)
Table 31. CTRL_REG4 description BLE Big/little endian data selection. Default value 0. (0: 4-wire interface; 1: 3-wire interface). Table 32. Self-test mode configuration
- DST sign (absolute value in Ta bl e 4).
Table 33. CTRL_REG5 register Table 34. CTRL_REG5 description
Figure 18. INT1_Sel and Out_Sel configuration block diagram Table 35. Out_Sel configuration settings Table 36. INT_SEL configuration settings
7.7 REFERENCE/DATACAPTURE (25h)
7.8 OUT_TEMP (26h)
7.9 STATUS_REG (27h)
Table 37. REFERENCE register Table 38. REFERENCE register description Table 39. OUT_TEMP register Table 40. OUT_TEMP register description Temp7-Temp0 Temperature data. Table 41. STATUS_REG register Table 42. STATUS_REG description
7.10 OUT_X_L (28h), OUT_X_H (29h)
X-axis angular rate data. The value is expressed as 2’s complement.
7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh)
Y -axis angular rate data. The value is expressed as 2’s complement.
7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh)
Z-axis angular rate data. The value is expressed as 2’s complement.
7.13 FIFO_CTRL_REG (2Eh)
7.14 FIFO_SRC_REG (2Fh)
Table 43. REFERENCE register Table 44. REFERENCE register description Table 45. FIFO mode configuration Table 46. FIFO_SRC register Table 47. FIFO_SRC register description
7.15 INT1_CFG (30h)
Configuration register for interrupt source.
7.16 INT1_SRC (31h)
Table 47. FIFO_SRC register description (continued) Table 48. INT1_CFG register Table 49. INT1_CFG description Cleared by reading the INT1_SRC reg. Table 50. INT1_SRC register
0 I A Z HZ LY HY LX HX L
Interrupt source register. Read only register.
7.17 INT1_THS_XH (32h)
7.18 INT1_THS_XL (33h)
7.19 INT1_THS_YH (34h)
Table 51. INT1_SRC description Table 52. INT1_THS_XH register Table 53. INT1_THS_XH description Table 54. INT1_THS_XL register Table 55. INT1_THS_XL description Table 56. INT1_THS_YH register Table 57. INT1_THS_YH description
7.20 INT1_THS_YL (35h)
7.21 INT1_THS_ZH (36h)
7.22 INT1_THS_ZL (37h)
7.23 INT1_DURATION (38h)
and maximum values depend on the ODR chosen. Wait =’0’: the interrupt falls immediately if signal crosses the selected threshold. Table 58. INT1_THS_YL register Table 59. INT1_THS_YL description Table 60. INT1_THS_ZH register Table 61. INT1_THS_ZH description Table 62. INT1_THS_ZL register Table 63. INT1_THS_ZL description Table 64. INT1_DURATION register Table 65. INT1_DURATION description
8 Package information
specifications, grade definitions and product status are available at www.st.com. Figure 21. LGA-16: mechanical data and package dimensions
9 Revision history
Table 66. Document revision history 02-Feb-2012 1 Initial release. 08-Feb-2012 2 Updated notes in Table 4: Mechanical characteristics.