A34C04 AITSEMI | Alldatasheet
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AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 1 - DESCRIPTION FEATURES The A34C04 is a 512 -byte EEPROM device designed to o perate the SMBus bus in the 1.7V - 3.6V voltage range, with a maximum of 1 MHz. The A34C04 includes a 4 -Kbit serial EEPROM organized as two banks of 256 bytes each, or 512 bytes of total memory. Each bank is composed of two 128 -byte blocks. The device is able to selectively lock the data in any or all of the four 128-byte blocks. Designed specifically for use in DRAM DIMMs (Dual Inline Memory Modules) with Serial Presence Detect, al l the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write -protected in one or more memory blocks. Individually locking a 128 -byte block may be accomplished using a software write p rotection mechanism in conjunction with a high input voltage VHV on input A0. By sending the device a specific SMBus sequence, each block may be protected from writes until the write protection is electrically reversed using a separate SMBus sequence which also requires VHV on input A0. The write protection for all four blocks is cleared simultaneously The A34C04 is available in DFN8 package.
ORDERING INFORMATION
SPQ: 3,000pcs/Reel A34C04J8R-Z A34C04J8VR-Z Note Z: Pin Type A: Type A B: Type B V: Halogen free Package R: Tape & Reel AiT provides all RoHS products ⚫ 512-byte Serial Presence Detect EEPROM compatible with JEDEC EE1004 specification ⚫ Compatible with SMBus serial interface: -up to 1 MHz transfer rate ⚫ Memory array: -4-Kbit organized as two banks of 256 bytes each -Each page is composed of two 128-byte blocks ⚫ Software data protection for each 128 -byte block ⚫ Hardware write protection ⚫ Write: -Byte Write within 3 ms -16 bytes Page Write within 3 ms ⚫ Schmitt Trigger, Filtered Inputs fo r Noise Suppression ⚫ Single supply voltage: -1.7 V to 3.6 V ⚫ High-reliability -Endurance: 1 Million Write Cycles -Data Retention: 100 Years ⚫ Enhanced ESD/latch-up protection -HBM 6000V ⚫ Available in DFN8 package
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 2 - PIN DESCRIPTION Type A - Top View Type B - Top View Pin # Symbol I/O Function DFN8 Type A Type B 1 1 A0 I Address Inputs 2 2 A1 I Address Inputs 3 3 A2 I Address Inputs 4 4 GND P Ground 5 5 SDA I/O Serial Data 6 6 SCL I Serial Clock Input 7 - WP I Write Protect - 7 NC - No Connection 8 8 VCC P Power Supply
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 3 - ABSOLUTE MAXIMUM STRESS RATINGS DC Supply Voltage -0.5V ~ 6.5V Input / Output Voltage GND-0.3V ~ VCC+0.3V Voltage on Pin A0 -0.5V ~ 10V Operating Ambient Temperature -40°C ~ +130°C Storage Temperature -65°C ~ +150°C Electrostatic pulse (Human Body model) 6000V Stress beyond above listed “Absolute Maximum Ratings” may lead permanent damage to the device. These are stress ratings only and operations of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CAPACITANCE Applicable over recommended operating range form: TA = 25℃, f = 1.0MHz, VCC = +1.7V Parameter Symbol Conditions Min. Typ. Max. Unit Input/Output Capacitance (SDA) CI/O VIO=0V - - 8 pF Input Capacitance (A0, A1, A2, SCL) CIN VIN=0V - - 6 pF
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 4 - DC ELECTRICAL CHARACTERISTICS Applicable over recommended operating range form: TA = 0 ℃ to +95 ℃, V CC = +1.7V to +5.5V, unless otherwise noted Parameter Symbol Test condition (in addition to those in Min Max Unit Input Leakage Current (SCL, SDA, A0, A1, A2) ILI VIN = GND or VCC - ± 2 μA Output Leakage Current ILO SDA in Hi -Z, external voltage applied on SDA: GND or VCC - ± 2 μA Supply Current (read) ICC fc = 400kHz or 1MHz - 1 mA Supply Current (write) ICC0 During tW, VIN = GND or VCC - 1NOTE1 mA Standby Supply Current ICC1 Device not selectedNOTE2, VIN = GND or VCC, VCC ≥ 2.2V - 2 μA Device not selectedNOTE2, VIN = GND or VCC, VCC < 2.2V - 1 μA Input Low Voltage (SCL, SDA, WP) VIL -0.45 0.3xVCC V Input High Voltage (SCL, SDA, WP) VIH 0.7xVCC VCC+1V V A0 High Voltage Detect VHV VCC < 2.2V 7 10 V VCC ≥ 2.2V VCC+4.8V 10 V Output Low Voltage VOL IOL = 0.15mA - 0.2 V IOL = 3mA - 0.4 V Power On Reset Threshold VPOR - 1.4NOTE1 V Power Down Reset Threshold VPDR 0.7NOTE2 - V NOTE1: Measured during characterization, not tested in production. NOTE2: The device is not selected after a power -up, after a read command (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command).
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 5 - AC ELECTRICAL CHARACTERISTICS Applicable over recommended operating range form: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF, unless otherwise noted Parameter Symbol VCC < 2.2V VCC ≥ 2.2V Unit 100kHz 400kHz 1000kHz Clock Frequency fSCL fC 10 100 10 400 10 1000 kHz Clock Pulse Width High Time tHIGH tCHCL 4000 - 600 - 260 - ns Clock Pulse Width Low Time tLOWNOTE1 tCLCH 4700 - 1300 - 500 - ns Detect Clock Low Timeout tTIMEOUTNOTE2 25 35 25 35 25 35 ms SDA Rise Time tRNOTE3 tXH1XH2 - 1000 20 300 - 120 ns SDA(out) Fall Time tFNOTE3 tQL1QL2 - 300 20 300 - 120 ns Data In Setup Time tSU:DAT tDXCH 250 - 100 - 50 - ns Data In Hold Time tHD:DI tCLDX 0 - 0 - 0 - ns Data Out Hold Time tHD:DAT tCLQX 200 3450 200 900 0 350 ns Start Condition Setup Time tSU:STANOTE4 tCHDL 4700 - 600 - 260 - ns Stop Condition Hold Time tHD:STA tDLCL 4000 - 600 - 260 - ns Stop Condition Setup Time tSU:STO tCHDH 4000 - 600 - 260 - ns Time between Stop Condition and next Start Condition tBUF tDHDL 4700 - 1300 - 500 - ns Write Time tW - 3 - 3 - 3 ms Time ensuring a Reset when VCC drops below VPDR(min) tPOFFNOTE3 100 - 100 - 100 - μs Time from VCC(min) to the first command tINITNOTE3 0 - 0 - 0 - μs NOTE1: Initiate clock stretching, which is an optional SMBus bus feature. NOTE2: A timeout condition can only be ensured if SCL is driven low for t TIMEOUT(Max) or longer; then the A34C04 is set in Standby mode and is ready to receive a new START condition. If SCL is driven low for less than tTIMEOUT(Min), the A34C04 internal state remains unchanged. NOTE3: Measured during characterization, not tested in production. NOTE4: To avoid spurious START and STOP conditions, a minimum delay is placed between the falling edge of SCL and the falling or rising edge of SDA.
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 6 - BLOCK DIAGRAM
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 7 - DETAILED INFORMATION DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device ad dress inputs that are hard wire for the A34C04. Eight 4K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The A0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open -drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used t o positive edge clock data into each EEPROM device and negative edge clock data out of each device. If SCL is driven low for t TIMEOUT (see AC Electrical Characteristics ) or longer, the A34C04 is set back in Standby mode, ready to receive a new START condition. WRITE PROTECT (WP): The A34C04 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to VCC, the write protection feature is enabled.
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 8 - FUNCTIONAL DESCRIPTION 1. Memory addressing To start a communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 1 (on Serial Data (SDA), most significant bit first). The Device Type Identifier Code (DTIC) consists of a 4-bit device type identifier, and a 3-bit slave address (A2, A1, A0). To address the memory array, the 4-bit device type identifier is 1010b; to access the write-protection settings, it is 0110b. Table 1 Abbr Device type identifier Select address R_W_n SA0 pin b7 b6 b5 b4 b3 b2 b1 b0 Read RSPD 1 0 1 0 LSA2 LSA1 LSA0 0 or 1 Write WSPD 0 Set Write Protection, block 0 SWP0 0 1 1 0 0 0 1 0 VHV Set Write Protection, block 1 SWP1 1 0 0 0 VHV Set Write Protection, block 2 SWP2 1 0 1 0 VHV Set Write Protection, block 3 SWP3 0 0 0 0 VHV Clear All Write Protection CWP 0 1 1 0 VHV Read Protection Status, block 0 RPS0 0 0 1 1 0,1 or VHV Read Protection Status, block 1 RPS1 1 0 0 1 0,1 or VHV Read Protection Status, block 2 RPS2 1 0 1 1 0,1 or VHV Read Protection Status, block 3 RPS3 0 0 0 1 0,1 or VHV Set Page Address to 0 SPA0 1 1 0 0 0,1 or VHV Set Page Address to 1 SPA1 1 1 1 0 0,1 or VHV Read Page Address RPA 1 1 0 1 0,1 or VHV Reserved - All other encodings Up to eight memory devices can be connected on a single serial bus. Each one is g iven a unique 3-bit code on the slave address (A2, A1, A0) inputs. When the device select code is received, the device only responds if the slave address is the same as the value on the slave address (A2, A1, A0) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode.
Figure 3. Output Acknowledge and (b) after the receipt of the STOP bit and the completion of any internal operations.
- Look for SDA high in each cycle while SCL is high.
- Create a start condition.
the entire memory when the WP pin is at VCC. disabled during this write cycle and the EEPROM will not respond until the write is complete ( Figure 4).
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 14 - 5. Setting the write protection There are four independent memory blocks, and each block may be independently protected. The memo ry blocks are: The device has three software commands for setting, clearing, or interrogating the write-protection status. ⚫ Block 0 = memory addresses 0x00 to 0x7F (decimal 0 to 127), page address = 0 ⚫ Block 1 = memory addresses 0x80 to 0xFF (decimal 128 to 255), page address = 0 ⚫ Block 2 = memory addresses 0x00 to 0x7F (decimal 0 to 127), page address = 1 ⚫ Block 3 = memory addresses 0x80 to 0xFF (decimal 128 to 255), page address = 1 The level of write protection (set or cleared), that has been defined using these instructions, remains defined even after a power cycle. ⚫ SWPn: Set Write Protection for block n ⚫ CWP: Clear Write Protection for all blocks ⚫ RPSn: Read Protection status for block n The DTICs of the SWP, CWP and RPS instructions are defined in Table 1. 6. Set and clear the write protection (SWPn and CWP) If the software write protection has been set with the SWPn instruction, it may be cleared again with a CWP instruction. SWPn acts on a single block as specified in the SWPn command , but CWP clears the write protection for all blocks. When decoded, SWPn and CWPn trigger a write cycle lasting tW (see AC Electrical Characteristics). The DTICs of the SWP and CWP instructions are defined in Table 1. 7. Read the protection status (RPSn) The serial bus master issues an RPSn command specifying which block to report upon. If the software write protection has not been set, the device replies to the data byte with an Ack. If it has been set, the device replies to the data byte with a NoAck. The DTIC of the RPSn instruction is defined in Table 1. 8. Set the page address (SPAn) The SPAn command selects the lower 256 bytes (SPA0) or upper 256 bytes (SPA1). After a cold or warm power-on reset, the page address is always 0, selecting the lower 256 bytes. The DTIC of the SPAn instruction is defined in Table 1. 9. Read the page address (RPA) The RPA command determines if the currently selected page is 0 (device returns Ack) or 1 (device returns NoAck). The DTIC of the RPA instruction is defined in Table 1.
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 15 - Use within a DDR4 DRAM module In the application, the A34C04 is soldered directly in the printed circuit module. The three slave address inputs (A2, A1, A0) must be connected to GND or V CC directly (that is without using a serial resistor) through the DRAM module connector (see Table 2). The pull -up resistor on SDA is connected on the SMBus of the motherboard. The Write Protect (WP) of the A34C04 can be left unconnected. However, connecting it to GND is recommended, to maintain full read and write access. Table 2 DIMM position A2 A1 A0
0 VSS VSS VSS
1 VSS VSS VCC
2 VSS VCC VSS
3 VSS VCC VCC
4 VCC VSS VSS
5 VCC VSS VCC
6 VCC VCC VSS
7 VCC VCC VCC
- Programming the A34C04 The situations in which the A34C04 is programmed can be considered under two headings: ⚫ when the DDR4 DRAM is isolated (not inserted on the PCB motherboard) ⚫ when the DDR4 DRAM is inserted on the PCB motherboard Isolated DRAM module: With a specific programming equipment, it is possible to define the A34C04 content, using Byte and Page w rite instructions, and the write -protection SWP(n) and CWP instructions. To issue the SWP(n) and CWP instructions, the signal applied on SA0 must be driven to V HV during the whole instruction. DRAM module inserted in the application mothe rboard: Table 3 and Table 4 show how the Ack bits can be used to identify the write-protection status. Table 3 Status Instruction Ack Address Ack Data byte Ack Write cycle (tW) Protected SWPn NoAck Not significant NoAck Not significant NoAck No CWP Ack Not significant Ack Not significant Ack Yes Page or byte write in protected block Ack Address Ack Data NoAck No Not Protected SWPn or CWP Ack Not significant Ack Not significant Ack Yes Page or byte write Ack Address Ack Data Ack Yes Table 4 SWPn Status Instruction Ack Address Ack Data byte Ack Set RPSn NoAck Not significant NoAck Not significant NoAck Not set RPSn Ack Not significant NoAck Not significant NoAck
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 16 - Figure 9
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 18 -
PACKAGE INFORMATION
Dimension in DFN8 (Unit: mm) Symbol UT:ULTRA THIN Min Max A 0.50 0.60 A1 0.00 0.05 A3 0.15REF D 1.95 2.05 E 2.95 3.05 b 0.20 0.30 L 0.20 0.40 D2 1.25 1.50 E2 1.15 1.40 e 0.50BSC
AiT Semiconductor Inc. www.ait-ic.com A34C04 EEPROM W/PERMANENT SW WRITE PROTECT 4-Kbit (512×8) TWO-WIRE SERIAL EEPROM REV1.0 - APR 2020 RELEASED - - 19 - IMPORTANT NOTICE AiT Semiconductor In c. (AiT) reserves the right to make c hanges to any its product, specifications, to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placin g orders, that the information being relied on is current. AiT Semiconductor Inc. 's integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life support applications, devices or systems or other critical applications. Use of AiT products in such applications is understood to be fully at the risk of the customer. As used herein may involve potential risks of de ath, personal injury, or server e property, or environmental damage. In order to minimize risks ass ociated with the customer's applicatio ns, the customer should provide adequate design and operating safeguards. AiT Semiconductor Inc . assumes to no liability to customer product design or application support. AiT warrants the performance of its products of the specifications applicable at the time of sale.