A32D32 ACTEL | Alldatasheet

Document overview

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Technical content

Features

  • AN SI/VITA 1-1994 com pliant
  • VM E slave controller
  • D ata m odes: D 8, D 16, D 32
  • Address m odes: A16, A24, A32
  • Supports read, w rite, read- m odify-w rite
  • C onfigurable D 8, D 16 or D 32 interrupter
  • Fully synchronous user side interface
  • U ser selectable w ait-states
  • Synchronous design A pplications
  • Industrial control
  • M ilitary
  • Aerospace
  • Telecom
  • M edical O ptim ized for Page 1/2 Family Device Utilization Performance - (speed grade) s-mod c-mod Tiles RAM Total [MHz] APA150 477 8% 67 Axcelerator AX500-3 193 159 4% 119 SXA SX72A-3 193 163 6% 83 RTSX RTSX72S-1 MIL 193 162 6% 43 ProASICPLUS VMEchip INTCmod User Decode VM Ebus Bus Bridge VME Slave Controller TIMERmod GPIOmod UARTmod on-chip bus

Pin N am e Type D escription G lobal Signals clk in System clock reset_n in Asynchronous system reset, active low VM E B us vm e_addr[31:1] in Address bus vm e_am [5:0] in Address m odifier code vm e_data_in[31:0] in D ata bus input vm e_data_out [31:0] out D ata bus output vm e_int_drv_n out Internal i/o driver enable vm e_data_drv_n out External data bus driver enable vm e_data_dir out External data bus driver direction vm e_ds0_n in D ata strobe 0 vm e_ds1_n in D ata strobe 1 vm e_lw ord_n in Long w ord indicator vm e_as_n in Address strobe vm e_w rite_n in R ead w rite not indicator vm e_dtack_n out D ata acknow ledge vm e_berr_n in Bus error vm e_iack_n in Interrupt acknow ledge vm e_iack_in_n in Interrupt acknow ledge chain in Pin N am e Type D escription vm e_iack_out_n out Interrupt acknow ledge chain out vm e_irq_n[6:0] out Interrupt request U ser Side B us user_addr[31:2] out Address bus user_am [5:0] out Address m odifier code user_acc_req out D ata access request user_acc_rdy in D ata access request ready user_data_rd[31:0] in D ata read bus user_data_w r[31:0] out D ata w rite bus user_rw n out D ata read or w rite access user_byte_valid [3:0] out D ata byte valid U ser D ecode int_user_addr[31:1] out Address bus int_user_am [5:0] out Address m odifier code user_access_ebl in Valid user access Interrupt user_iack out Interrupt acknow ledge user_ireq in Interrupt request user_ivec[31:0] in Interrupt vector user_ilevel[2:0] in Interrupt request level INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com A bout Inicore  FPG A and ASIC D esign  Easy-to-use IP C ores  System -on-C hip Solutions  C onsulting Services  ASIC to FPG A M igration  O bsolete ASIC R eplacem ents Inicore is an experienced system design house providing FPG A / ASIC and SoC design services. The com pany's expertise in architecture, intellectual property, m ethodology and tool handling provides a com plete design environm ent that helps custom ers shorten their design cycle and speed tim e to m arket. O ur offering covers feasibility study, concept analysis, architecture definition, code generation and im plem entation. W hen ready, w e deliver you a FPG A or take your design to an ASIC provider, w hatever is m ore suitable for your unique solution. D eliverables The core is available as Actel optim ized netlist or as R TL version. Actel O ptim ized N etlist:

  • N etlist for target FPG A, ED IF, Verilog and VH D L form at
  • U ser G uide R TL Source C ode:
  • VH D L or Verilog source code
  • Funtional verification testbench
  • Synthesis script
  • Tim ing constraints
  • U ser guide Page 2/2 Figure 2: Symbol © 2003, Inicore Inc, All rights reserved. All brands or product names mentioned are the property of their respective holders.

51410.71.02 Sept/2003

reset _ n clk _ sy s v m e_ addr[3 1 :1 ] v m e_ am [5 :0 ] v m e_ dat a_ in [3 1 :0 ] v m e_ dat a_ drv _ n v m e_ dat a_ dir v m e_ ds0 _ n v m e_ ds1 _ n v m e_ lwo rd_ n v m e_ as_ n v m e_ writ e_ n v m e_ dt ack _ n v m e_ berr_ n v m e_ ia ck _ n v m e_ ia ck _ in _ n v m e_ ia ck _ o ut _ n v m e_ ir q_ n [6 :0 ] v m e_ dat a_ o ut [3 1 :0 ] v m e_ dat a_ in t _ drv _ n in t _ user_ am [5 :0 ] in t _ user_ addr[3 1 :1 ] user_ access_ ebl user_ ia ck user_ ir eq user_ ile v [2 :0 ] user_ iv ec[3 1 :0 ] user_ addr[3 1 :2 ] user_ am [5 :0 ] user_ acc_ req user_ acc_ rdy user_ dat a_ rd[3 1 :0 ] user_ dat a_ wr[3 1 :0 ] user_ rwn user_ by t e_ v alid[3 :0 ] VM E Bus Interrupts Us er Side BusDecode