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Features

Advanced high performance in--package Doherty
Greater negative gate--source voltage range for improved Class C operation
Designed for digital predistortion error correction systems Document Number: A2T14H450--23N Rev. 0, 01/2017 NXPSemiconductors Technical Data 1452–1511MHz,93WAVG.,31V AIRFASTRFPOWERLDMOS TRANSISTOR A2T14H450--23NR6 Figure1.PinConnections (Top View) RF outA/V DSA RF outB/V DSB RF inA/V GSA RF inB/V GSB VBW A(1)6 1 5 2 4 Carrier Peaking VBW B(1) Note: Exposed backside of the package is the source terminal for the transistor. OM--1230--4L2S PLASTIC 1. Device cannot operate with VDD current supplied through pin 3 and pin 6.  2017 NXP B.V.

Table1.MaximumRatings Rating Symbol Value Unit Drain--Source Voltage VDSS –0.5, +65 Vdc Gate--Source Voltage VGS –6.0, +10 Vdc Operating Voltage VDD 32, +0 Vdc Storage Temperature Range Tstg –65 to +150 °C Case Operating Temperature Range TC –40 to +150 °C Operating Junction Temperature Range (1,2) TJ –40 to +225 °C Table2.ThermalCharacteristics Characteristic Symbol Value (2,3) Unit Thermal Resistance, Junction to Case Case Temperature 74 °C, 93 W Avg., W--CDMA, 31 Vdc, IDQA = 1000 mA, VGSB = 0.5 Vdc, 1482 MHz RθJC 0.27 °C/W Table3.ESDProtectionCharacteristics TestMethodology Class Human Body Model (per JESD22--A114) 2 Charge Device Model (per JESD22--C101) IV Table4.MoistureSensitivityLevel TestMethodology Rating PackagePeakTemperature Unit Per JESD22--A113, IPC/JEDEC J--STD--020 3 260 °C Table5.ElectricalCharacteristics (T A = 25 °C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OffCharacteristics (4) Zero Gate Voltage Drain Leakage Current (V DS = 65 Vdc, VGS= 0 Vdc) IDSS — — 10 µAdc Zero Gate Voltage Drain Leakage Current (V DS = 32 Vdc, VGS= 0 Vdc) IDSS — — 1 µAdc Gate--Source Leakage Current (V GS= 5 Vdc, VDS = 0 Vdc) IGSS — — 1 µAdc OnCharacteristics -- SideA,Carrier Gate Threshold Voltage (V DS = 10 Vdc, ID = 200 µAdc) VGS(th) 1.05 1.2 2.2 Vdc Gate Quiescent Voltage (V DD = 31 Vdc, ID = 1000 mAdc, Measured in Functional Test) VGSA(Q) 2.1 2.5 2.9 Vdc Drain--Source On--Voltage (V GS= 10 Vdc, ID = 2.0 Adc) VDS(on) 0.05 0.15 0.3 Vdc OnCharacteristics -- SideB,Peaking Gate Threshold Voltage (V DS = 10 Vdc, ID = 300 µAdc) VGS(th) 0.8 1.2 1.6 Vdc Drain--Source On--Voltage (V GS= 10 Vdc, ID = 3.0 Adc) VDS(on) 0.05 0.15 0.3 Vdc 1. Continuous use at maximum temperature will affect MTTF. 2. MTTF calculator available at http://www.nxp.com/RF/calculators . 4. Each side of device measured separately. (continued)

Table5.ElectricalCharacteristics (T A = 25 °C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit FunctionalTests–1452MHz (1,2)(In NXP Doherty Test Fixture, 50 ohm system) VDD = 31 Vdc, IDQA = 1000 mA, VGSB = 0.5 Vdc, Pout= 93 W Avg.,f= 1452MHz,Single--CarrierW--CDMA,IQMagnitude Clipping,InputSignalPAR =9.9 dB@ 0.01%Probability onCCDF. ACPR measured in 3.84 MHz Channel Bandwidth @±5 MHz Offset. Power Gain Gps 17.0 18.8 20.0 dB Drain Efficiency ηD 45.0 48.2 — % Output Peak--to--Average Ratio @ 0.01% Probability on CCDF PAR 7.3 8.1 — dB Adjacent Channel Power Ratio ACPR — –38.2 –32.0 dBc FunctionalTests–1511MHz (1,2)(In NXP Doherty Test Fixture, 50 ohm system) VDD = 31 Vdc, IDQA = 1000 mA, VGSB = 0.5 Vdc, Pout= 93 W Avg.,f= 1511 MHz,Single--Carrier W--CDMA,IQ Magnitude Clipping,InputSignal PAR =9.9 dB@ 0.01%Probability onCCDF. ACPR measured in 3.84 MHz Channel Bandwidth @±5 MHz Offset. Power Gain Gps 17.0 19.0 20.0 dB Drain Efficiency ηD 45.0 48.7 — % Output Peak--to--Average Ratio @ 0.01% Probability on CCDF PAR 7.3 7.7 — dB Adjacent Channel Power Ratio ACPR — –38.6 –32.0 dBc LoadMismatch (2)(In NXP Doherty Test Fixture, 50 ohm system) IDQA = 1000 mA, VGSB = 0.5 Vdc, f = 1480 MHz, 12 µsec(on), 10% Duty Cycle VSWR 10:1 at 32 Vdc, 560 W Pulsed CW Output Power (3 dB Input Overdrive from 417 W Pulsed CW Rated Power) No Device Degradation TypicalPerformance (2)(In NXP Doherty Test Fixture, 50 ohm system) VDD = 31 Vdc, IDQA = 1000 mA, VGSB = 0.5 Vdc, 1452–1511 MHz Bandwidth Pout@ 3 dB Compression Point (3) P3dB — 560 — W AM/PM (Maximum value measured at the P3dB compression point across the 1452–1511 MHz frequency range) Φ — –10 — ° VBW Resonance Point (IMD Third Order Intermodulation Inflection Point) VBW res — 68 — MHz Gain Flatness in 59 MHz Bandwidth @ Pout= 93 W Avg. GF — 0.3 — dB Gain Variation over Temperature (–30 °C to +85 °C) Output Power Variation over Temperature (–30 °C to +85 °C) ∆P1dB — 0.021 — dB/ °C Table6.OrderingInformation Device TapeandReelInformation Package A2T14H450--23NR6 R6 Suffix = 150 Units, 56 mm Tape Width, 13--inch ReelOM--1230--4L2S 1. Part internally matched both on input and output. 2. Measurements made with device in an asymmetrical Dohertyconfiguration. 3. P3dB=P avg+7.0dBwhereP avgistheaverageoutputpowermeasured usingan unclippedW--CDMAsingle--carrierinputsignalwhere output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.

Figure2.A2T14H450--23NR6TestCircuitComponentLayout D79052 A2T14H450--23N Rev.2 C18 C19 C10 C11 C16 C17 C25 C12 C14 C15 C13 C20 C21 C23 C24 C22 C26 C27 C3 C5 C8 C6 CUTOUTAREA VGGA VGGB VDDB VDDA C P Table7.A2T14H450--23NR6TestCircuitComponentDesignationsandValues Part Description PartNumber Manufacturer C1, C2 470 µF, 63 V Electrolytic Capacitor MCGPR63V477M13X26RH Multicomp C3, C4, C5, C6, C7, C8, C9 10 µF Chip Capacitor C5750X7S2A106M230KE TDK C10, C11 220 nF Chip Capacitor C1812C224K5RACTU Kemet C12, C13 10 µF Chip Capacitor GRM32ER61H106KA12L Murata C14, C15, C16, C17 18 pF Chip Capacitor GQM2195C2E180JB12D Murata C18, C19, C20, C21, C22, C23 18 pF Chip Capacitor ATC100B180GT500XT ATC C24 8.2 pF Chip Capacitor ATC100B8R2BT500XT ATC C25 1.8 pF Chip Capacitor ATC100B1R8BT500XT ATC C26 0.2 pF Chip Capacitor ATC100B0R2BT500XT ATC C27 0.4 pF Chip Capacitor ATC100B0R4BT500XT ATC R1, R2 3.3 Ω, 1/4 W Chip Resistor WCR1206-3R3FI Welwyn R3 50 Ω, 8 W Surface Mount Terminator C8A50Z4A Anaren Z1 1800–2200 MHz Band, 90 °, 2 dB Doherty Coupler X3C20F1-02S Anaren PCB Rogers RO4360G2, 0.020 ″,εr= 6.15 D79052 MTL

TYPICALCHARACTERISTICS—1452–1511MHz 1420 ACPR f,FREQUENCY(MHz) Figure3.Single--CarrierOutputPeak--to--AverageRatioCompression (PARC)BroadbandPerformance@Pout=93WattsAvg. 18.4 19.4 19.3 19.2 –42 –32 –34 –36 –38 ηD,DRAIN EFFICIENCY(%) ηD Gps,POWERGAIN(dB) 19.1 19.0 18.9 18.8 18.7 18.6 18.5 1440 1460 1480 1500 1520 1540 –40 ACPR(dBc) PARC Figure4.IntermodulationDistortionProducts versusTwo--ToneSpacing TWO--TONESPACING(MHz) –75 –15 –30 –60 1 100 IMD,INTERMODULATIONDISTORTION(dBc) –45 IM5--UIM5--L IM7--L IM7--U Figure5.OutputPeak--to--AverageRatio Compression(PARC)versusOutputPower Pout,OUTPUTPOWER(WATTS) OUTPUTCOMPRESSIONAT0.01% PROBABILITYONCCDF(dB) 0 80 120 200 ηD,DRAINEFFICIENCY(%) –1dB=63W 160 ηD ACPR PARC ACPR(dBc) –55 –25 –30 –35 –45 –40 –50

19.6 Gps,POWERGAIN(dB)

19.4 19.2 19.0 18.8 18.6 18.4 G ps –3dB=120W –2dB=93W PARC(dB) –2.8 –1.6 –1.9 –2.2 –3.1 Gps InputSignalPAR=9.9dB@0.01%ProbabilityonCCDF IM3--L VDD =31Vdc,IDQA =1000mA,VGSB =0.5Vdc, f=1482MHz –2.5 200 IM3--U VDD =31Vdc,Pout=50W(PEP),IDQA =1000mA VGSB =0.5Vdc,Two--ToneMeasurements (f1+f2)/2=CenterFrequencyof1482MHz InputSignalPAR=9.9dB@0.01%ProbabilityonCCDF Single--CarrierW--CDMA 3.84MHzChannelBandwidth VDD =31Vdc,Pout=93W(Avg.),IDQA =1000mA,VGSB =0.5Vdc Single--CarrierW--CDMA,3.84MHzChannelBandwidth

TYPICALCHARACTERISTICS—1452–1511MHz Gps Pout,OUTPUTPOWER(WATTS)AVG. –20 –30 ηD,DRAINEFFICIENCY(%) ηD Gps,POWERGAIN(dB) 10 100 500 ACPR(dBc) –10 –40 –50 –60 VDD =31Vdc,IDQA =1000mA,VGSB =0.5Vdc Single--CarrierW--CDMA,3.84MHz ChannelBandwidthInputSignal PAR=9.9dB@0.01%ProbabilityonCCDF Figure6.Single--CarrierW--CDMAPowerGain,Drain EfficiencyandACPRversusOutputPower Figure7.BroadbandFrequencyResponse f,FREQUENCY(MHz) VDD =31Vdc Pin=0dBm IDQA =1000mA VGSB =0.5Vdc

12 GAIN(dB)

1000 1100 1200 1300 1400 1500 1600 1700 1800 Gain 1511MHz 1452MHz 1482MHz 1452MHz 1511MHz 1482MHz 1511MHz 1482MHz 1452MHz ACPR

Table8.CarrierSideLoadPullPerformance—MaximumPowerT uning VDD = 30 Vdc, IDQA = 880 mA ,Pulsed CW, 10 µsec(on), 10% Duty Cycle f (MHz) Zsource (ΩΩ ΩΩ ) Zin (ΩΩ ΩΩ ) MaxOutputPower P1dB Zload(1) (ΩΩ ΩΩ ) Gain(dB) (dBm) (W) ηη ηηD (%) AM/PM (°° °°) f (MHz) Zsource (ΩΩ ΩΩ ) Zin (ΩΩ ΩΩ ) MaxOutputPower P3dB Zload(2) (ΩΩ ΩΩ ) Gain(dB) (dBm) (W) ηη ηηD (%) AM/PM (°° °°) (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Z source= Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device atthe package reference plane. Table9.CarrierSideLoadPullPerformance—MaximumEfficiencyTuning VDD = 30 Vdc, IDQA = 880 mA ,Pulsed CW, 10 µsec(on), 10% Duty Cycle f (MHz) Zsource (ΩΩ ΩΩ ) Zin (ΩΩ ΩΩ ) MaxDrainEfficiency P1dB Zload(1) (ΩΩ ΩΩ ) Gain(dB) (dBm) (W) ηη ηηD (%) AM/PM (°° °°) f (MHz) Zsource (ΩΩ ΩΩ ) Zin (ΩΩ ΩΩ ) MaxDrainEfficiency P3dB Zload(2) (ΩΩ ΩΩ ) Gain(dB) (dBm) (W) ηη ηηD (%) AM/PM (°° °°) (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. Z source= Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device atthe package reference plane. InputLoadPull TunerandTest Circuit Device Under Test Zsource Zin Zload OutputLoadPull TunerandTest Circuit

P1dB–TYPICALCARRIERSIDELOADPULLCONTOURS—1475MHz IMAGINAR Y(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 NOTE: = Maximum Output Power = Maximum Drain Efficiency P E Gain Drain Efficiency Linearity Output Power Figure8.P1dBLoadPullOutputPowerContours(dBm) Figure9 .P1dBLoadPullEfficiencyContours(%) Figure10.P1dBLoadPullGainContours(dB) Figure11.P1dBLoadPullAM/PMContours( °° °°) P E 49.5 52.5 50.5 51.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINARY(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINAR Y(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINARY(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 54 52 E P 58 60 62 P E 23.5 22.5 21.5 20.520 19.5 P E–26 –20 –14 –16 –18 –24 –22 –28 –12

P3dB–TYPICALCARRIERSIDELOADPULLCONTOURS—1475MHz IMAGINAR Y(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 NOTE: = Maximum Output Power = Maximum Drain Efficiency P E Gain Drain Efficiency Linearity Output Power Figure12.P3dBLoadPullOutputPowerContours(dBm) Figure 13.P3dBLoadPullEfficiencyContours(%) Figure14.P3dBLoadPullGainContours(dB) Figure15.P3dBLoadPullAM/PMContours( °° °°) IMAGINARY(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINAR Y(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINARY(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 P E 53.5 53 52.5 51.5 50.5 60 62 54 52 E P P E 17.5 19.5 18.518 20.5 21.5 P E –26 –22 –20 –28 –30 –24 –18 –32 –34

Table10.PeakingSideLoadPullPerformance—MaximumPower Tuning VDD = 30 Vdc, VGSB = 0.5 Vdc ,Pulsed CW, 10 µsec(on), 10% Duty Cycle f (MHz) Zsource (ΩΩ ΩΩ ) Zin (ΩΩ ΩΩ ) MaxOutputPower P1dB Zload(1) (ΩΩ ΩΩ ) Gain(dB) (dBm) (W) ηη ηηD (%) AM/PM (°° °°) f (MHz) Zsource (ΩΩ ΩΩ ) Zin (ΩΩ ΩΩ ) MaxOutputPower P3dB Zload(2) (ΩΩ ΩΩ ) Gain(dB) (dBm) (W) ηη ηηD (%) AM/PM (°° °°) (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Z source= Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device atthe package reference plane. Table11.PeakingSideLoadPullPerformance—MaximumEffic iencyTuning VDD = 30 Vdc, VGSB = 0.5 Vdc ,Pulsed CW, 10 µsec(on), 10% Duty Cycle f (MHz) Zsource (ΩΩ ΩΩ ) Zin (ΩΩ ΩΩ ) MaxDrainEfficiency P1dB Zload(1) (ΩΩ ΩΩ ) Gain(dB) (dBm) (W) ηη ηηD (%) AM/PM (°° °°) f (MHz) Zsource (ΩΩ ΩΩ ) Zin (ΩΩ ΩΩ ) MaxDrainEfficiency P3dB Zload(2) (ΩΩ ΩΩ ) Gain(dB) (dBm) (W) ηη ηηD (%) AM/PM (°° °°) (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. Z source= Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device atthe package reference plane. InputLoadPull TunerandTest Circuit Device Under Test Zsource Zin Zload OutputLoadPull TunerandTest Circuit

P1dB–TYPICALPEAKINGSIDELOADPULLCONTOURS—1475MHz IMAGINAR Y(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 NOTE: = Maximum Output Power = Maximum Drain Efficiency P E Gain Drain Efficiency Linearity Output Power Figure16.P1dBLoadPullOutputPowerContours(dBm) Figure 17.P1dBLoadPullEfficiencyContours(%) Figure18.P1dBLoadPullGainContours(dB) Figure19.P1dBLoadPullAM/PMContours( °° °°) –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINARY(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINAR Y(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINARY(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 P E 52.5 54.5 53 55 53.554 51.5 53.552.5 E P P E17 16.5 15.5 15 14.5 13.5 P E –30 –36 –42 –40 –38 –32 –34 –28 –44

P3dB–TYPICALPEAKINGSIDELOADPULLCONTOURS—1475MHz IMAGINAR Y(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 NOTE: = Maximum Output Power = Maximum Drain Efficiency P E Gain Drain Efficiency Linearity Output Power Figure20.P3dBLoadPullOutputPowerContours(dBm) Figure 21.P3dBLoadPullEfficiencyContours(%) Figure22.P3dBLoadPullGainContours(dB) Figure23.P3dBLoadPullAM/PMContours( °° °°) IMAGINARY(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINAR Y(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 IMAGINARY(Ω ) 0.5 1.0 2.0 3.0 –0.5 2.5 –3.5 REAL(Ω ) 3.5 –1.0 –1.5 –2.0 –3.0 –2.5 1.5 P E 53.5 53 52.5 55 55.5 54.5 60 62 E P P E 14.5 12.5 13.5 11.5 P E –46 –50 –52 –44 –42 –48 –40 –38 –36

PRODUCTDOCUMENTATION,SOFTWAREANDTOOLS Refer to the following resources to aid your design process. ApplicationNotes

AN1907: Solder Reflow Attach Method for High Power RF Devices in Plastic Packages
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
AN3789: Clamping of High Power RF Transistors and RFICs in Over--Molded Plastic Packages EngineeringBulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices Software
Electromigration MTTF Calculator
.s2p File DevelopmentTools
Printed Circuit Boards ToDownloadResourcesSpecifictoaGivenPartNumber: 1.Go to http://www .nxp.com/RF 2.Search by part number 3.Click part number link 4.Choose the desired resource from the drop down menu REVISIONHISTORY The following table summarizes revisions to this document. Revision Date Description 0 Jan. 2017 • Initial release of data sheet

How to Reach Us: HomePage: nxp.com WebSupport: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume anyliability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidentaldamages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/ SalesTermsandConditions . NXP, the NXP logo, Freescale, the Freescale logo, and Airfast are trademarks of NXP B.V. All other product or service names are the property of their respective owners. /C00692017 NXP B.V. Document Number: A2T14H450--23N Rev. 0, 01/2017

Product Information

A2T14H450-23NR6 specifications and overview.

Summary

N--Channel Enhancement--Mode Lateral MOSFET Rev. 0, 01/2017

Description

N--Channel Enhancement--Mode Lateral MOSFET Rev. 0, 01/2017

Source title A2T14H450-23NR6 Datasheet(PDF) - NXP Semiconductors

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