A2631

OPA2631 BURR-BROWN | Alldatasheet

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International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

FEATURES

l HIGH BANDWIDTH: 75MHz (G = +2) l LOW SUPPLY CURRENT: 6mA/ch l +3V AND +5V OPERATION l INPUT RANGE INCLUDES GROUND l 4.8V OUTPUT SWING ON +5V SUPPLY l HIGH SLEW RATE: 100V/ µs l LOW INPUT VOLTAGE NOISE: 6nV/ √Hz © 1999 Burr-Brown Corporation PDS-1378A Printed in U.S.A. August, 1999 Dual, Low Power, Single-Supply OPERATIONAL AMPLIFIER

APPLICATIONS

l DIFFERENTIAL RECEIVERS/DRIVERS l ACTIVE FILTERS l MATCHED I AND Q CHANNEL AMPLIFIERS l CCD IMAGING CHANNELS l LOW POWER ULTRASOUND l PORTABLE CONSUMER ELECTRONICS TM

DESCRIPTION

The OPA2631 is a dual, low power, voltage-feedback amplifier designed to operate on a single +3V or +5V supply. Operation on ±5V or +10V supplies is also supported. The input range extends below ground and to within 1V of the positive supply. Using complemen- tary common-emitter outputs provides an output swing to within 30mV of ground and 130mV of the positive supply. The high output drive current and low differen- tial gain and phase errors also make it ideal for single- supply consumer video products. Low distortion operation is ensured by the high gain bandwidth (68MHz) and slew rate (100V/µs), making the OPA2631 an ideal input buffer stage to 3V and 5V CMOS converters. Unlike other low power, single- supply amplifiers, distortion performance improves as the signal swing is decreased. A low 6nV/ √Hz input voltage noise supports wide dynamic range operation. The OPA2631 is available in an industry standard SO-8 package. Where a single channel, single-supply operational amplifier is required, consider the OPA631 and OPA632. Where higher full-power bandwidth and lower distortion are required, consider the OPA2634. SINGLES DUALS Medium Speed, No Disable OPA631 OPA2631 With Disable OPA632 — High Speed, No Disable OPA634 OPA2634 With Disable OPA635 —

RELATED PRODUCTS

For most current data sheet and other product information, visit www.burr-brown.com SPICE model available at www.burr-brown.com OPA2631 VIN 750Ω562Ω 2.26kΩ 374Ω 22pF +3V 100Ω +3V ADS901 10-Bit 20Msps

0°C to –40 °C to MIN/ TEST PARAMETER CONDITIONS +25 °C +25 °C7 0 °C +85 °C UNITS MAX LEVEL (1) SPECIFICATIONS: V S = +5V At TA = 25°C, G = +2, RF = 750Ω , and RL = 150Ω to VS /2, unless otherwise noted. AC PERFORMANCE (Figure 1) Small-Signal Bandwidth G = +2, V O ≤ 0.5Vp-p 75 50 40 32 MHz min B G = +5, VO ≤ 0.5Vp-p 16 12 10 8.5 MHz min B Gain Bandwidth Product G ≥ +10 68 51 40 36 MHz min B Peaking at a Gain of +1 V O ≤ 0.5Vp-p 5 — — — dB typ C Slew Rate G = +2, 2V Step 100 64 52 47 V/ µs min B Rise Time 0.5V Step 5.3 8.0 11 12.8 ns max B Fall Time 0.5V Step 5.4 7.5 10 11.6 ns max B Settling Time to 0.1% G = +2, 1V Step 17 28 38 42 ns max B Spurious Free Dynamic Range V O = 2Vp-p, f = 5MHz 44 40 38 35 dB min B VO = 2Vp-p, f = 1MHz, RL = 1kΩ 84 68 66 62 dB min B Input Voltage Noise f > 1MHz 6.0 6.8 7.6 7.9 nV/ √Hz max B Input Current Noise f > 1MHz 1.9 2.6 2.9 3.6 pA/ √Hz max B NTSC Differential Gain 0.5 — — — % typ C NTSC Differential Phase 1.2 — — — degrees typ C Channel-to-Channel Isolation Input Referred, f = 5MHz 93 — — — dB typ C DC PERFORMANCE Open-Loop Voltage Gain 62 56 50 46 dB min A Input Offset Voltage 2.5 6 8 11 mV max A Average Offset Voltage Drift — — — 50 µV/°C max B Input Bias Current V CM = 2.0V 11 21 27 40 µA max A Input Offset Current V CM = 2.0V 0.3 1 1.3 2 µA max A Input Offset Current Drift — — — 7 nA/ °C max B INPUT Least Positive Input Voltage –0.5 –0.1 –0.1 –0.1 V max B Most Positive Input Voltage 4.0 3.7 3.7 3.5 V min A Common-Mode Rejection Ratio (CMRR) Input Referred 74 70 68 60 dB min A Input Impedance Differential-Mode 10 || 2.1 — — — k Ω || pF typ C Common-Mode 400 || 1.2 — — — k Ω || pF typ C OUTPUT Current Output, Sourcing 80 25 20 5 mA min A Current Output, Sinking 90 38 24 10 mA min A Short-Circuit Current (output shorted to either supply) 100 — — — mA typ C Closed-Loop Output Impedance Figure 1, f ≤ 50kHz 0.6 — — — Ω typ C POWER SUPPLY Minimum Operating Voltage — 2.7 2.7 2.7 V min A Maximum Operating Voltage — 10.5 10.5 10.5 V max A Maximum Quiescent Current V S = +5V 6 6.4 6.7 6.9 mA/chan max A Minimum Quiescent Current V S = +5V 6 5.8 5.5 4.8 mA/chan min A Power Supply Rejection Ratio (PSRR) Input Referred 59 52 49 48 dB min A THERMAL CHARACTERISTICS Specification: U –40 to +85 ——— °C typ C Thermal Resistance U SO-8 125 — — — °C/W typ C NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.

SPECIFICATIONS: V S = +3V At TA = 25°C, G = +2, RF = 750Ω , and RL = 150Ω to VS /2, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. OPA2631U TYP GUARANTEED 0°C to MIN/ TEST PARAMETER CONDITIONS +25 °C +25 °C7 0 °C UNITS MAX LEVEL (1) AC PERFORMANCE (Figure 2) Small-Signal Bandwidth G = +2, V O ≤ 0.5Vp-p 61 45 35 MHz min B G = +5, VO ≤ 0.5Vp-p 15 11 9 MHz min B G = +10, VO ≤ 0.5Vp-p 7.7 4.6 4.0 MHz min B Gain Bandwidth Product G ≥ +10 63 47 34 MHz min B Peaking at a Gain of +1 V O ≤ 0.5Vp-p 5 — — dB typ C Slew Rate 1V Step 95 52 46 V/ µs min B Rise Time 0.5V Step 5.6 9 11.3 ns max B Fall Time 0.5V Step 5.6 9 11.3 ns max B Settling Time to 0.1% 1V Step 40 63 85 ns max B Spurious Free Dynamic Range V O = 1Vp-p, f = 5MHz 44 37 34 dB min B VO = 1Vp-p, f = 1MHz, RL = 1kΩ 8 46 76 5 dB min B Input Voltage Noise f > 1MHz 6.2 7.0 7.8 nV/ √Hz max B Input Current Noise f > 1MHz 2.0 2.6 2.9 pA/ √Hz max B Channel-to-Channel Isolation Input Reference, f = 5MHz 93 — — dB typ C DC PERFORMANCE Open-Loop Voltage Gain 60 54 50 dB min A Input Offset Voltage 0.5 3.5 4 mV max A Average Offset Voltage Drift ——4 5 µV/°C max B Input Bias Current V CM = 1.0V 12 21 26 µA max A Input Offset Current V CM = 1.0V 0.3 1 1.3 µA max A Input Offset Current Drift — — 2 nA/ °C max B INPUT Least Positive Input Voltage –0.5 –0.3 –0.1 V max B Most Positive Input Voltage 2 1.75 1.3 V min A Common-Mode Rejection Ratio (CMRR) Input Referred 72 66 65 dB min A Input Impedance Differential-Mode 10 || 2.1 — — k Ω || pF typ C Common-Mode 400 || 1.2 — — k Ω || pF typ C OUTPUT Least Positive Output Voltage R L = 1kΩ to 1.5V 0.03 0.05 0.05 V max A R L = 150Ω to 1.5V 0.05 0.15 0.16 V max A Most Positive Output Voltage R L = 1kΩ to 1.5V 2.95 2.85 2.84 V min A R L = 150Ω to 1.5V 2.85 2.66 2.60 V min A Current Output, Sourcing 55 21 14 mA min A Current Output, Sinking 55 21 14 mA min A Short Circuit Current (output shorted to either supply) 80 — — mA typ C Closed-Loop Output Impedance Figure 2, f < 50kHz 0.6 — — Ω typ C POWER SUPPLY Minimum Operating Voltage — 2.7 2.7 V min A Maximum Operating Voltage — 10.5 10.5 V max A Maximum Quiescent Current V S = +3V 5.3 5.7 6.2 mA/chan max A Minimum Quiescent Current V S = +3V 5.3 5.0 4.8 mA/chan min A Power Supply Rejection Ratio (PSRR) Input Referred 57 50 48 dB min A THERMAL CHARACTERISTICS Specification: U –40 to +85 °C typ C Thermal Resistance U SO-8 125 °C/W typ C NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.

+V S Out B –In B +In B Out A –In A +In A GND OPA2631 ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from perfor- mance degradation to complete device failure. Burr-Brown Corpo- ration recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER (1) RANGE MARKING NUMBER (2) MEDIA OPA2631U SO-8 Surface-Mount 182 –40 °C to +85°C OPA2631 OPA2631U Rails "" " " " OPA2631U/2K5 Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA2631U/2K5” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION

TYPICAL PERFORMANCE CURVES: V S = +5V At TA = 25°C, G = +2, RF = 750Ω , and RL = 150Ω to VS /2, unless otherwise noted (see Figure 2). –12 –15 –18 –21 –24 SMALL-SIGNAL FREQUENCY RESPONSE Frequency (MHz) Normalized Gain (dB) 1 10 100 300 VO = 200mVp-p G = +10 G = +5 G = +2 –12 –15 –18 LARGE-SIGNAL FREQUENCY RESPONSE Frequency (MHz) Gain (dB) 1 10 100 300 VO = 0.2Vp-p VO = 4Vp-p VO = 2Vp-p VO = 1Vp-p SMALL-SIGNAL PULSE RESPONSE Time (10ns/div) Input and Output Voltage (50mV/div) VO = 200mVp-p VO VIN 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 OUTPUT SWING vs LOAD RESISTANCE R L (Ω ) 50 100 1000 Maximum Output Voltage (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Minimum Output Voltage (V) Maximum V O Minimum VO LARGE-SIGNAL PULSE RESPONSE Time (10ns/div) Input and Output Voltage (500mV/div) VO = 4Vp-p VO VIN –40 –50 –60 –70 –80 –90 –100 CHANNEL-TO-CHANNEL CROSSTALK Frequency (MHz) 1 10 100 Input-Refered Isolation (dB)

TYPICAL PERFORMANCE CURVES: V S = +5V (Cont.) At TA = 25°C, G = +2, RF = 750Ω , and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1). –30 –40 –50 –60 –70 –80 HARMONIC DISTORTION vs OUTPUT VOLTAGE Output Voltage (Vp-p) 0.1 1 f = 5MHz Harmonic Distortion (dBc) 3rd Harmonic 2nd Harmonic –30 –40 –50 –60 –70 –80 HARMONIC DISTORTION vs INVERTING GAIN Gain Magnitude (V/V) 11 0 Harmonic Distortion (dBc) VO = 2Vp-p f = 5MHz 3rd Harmonic 2nd Harmonic –30 –40 –50 –60 –70 –80 HARMONIC DISTORTION vs FREQUENCY Frequency (MHz) 10.1 10 Harmonic Distortion (dBc) VO = 2Vp-p 3rd Harmonic 2nd Harmonic –30 –40 –50 –60 –70 –80 HARMONIC DISTORTION vs LOAD RESISTANCE R L (Ω ) 100 1000 Harmonic Distortion (dBc) VO = 2Vp-p fO = 5MHz 3rd Harmonic 2nd Harmonic –30 –40 –50 –60 –70 –80 HARMONIC DISTORTION vs SUPPLY VOLTAGE Single Supply Voltage (V) 38 9 76541 0 Harmonic Distortion (dBc) VO = 2Vp-p fO = 5MHz 3rd Harmonic 2nd Harmonic –30 –40 –50 –60 –70 –80 HARMONIC DISTORTION vs NON-INVERTING GAIN Gain Magnitude (V/V) 11 0 Harmonic Distortion (dBc) VO = 2Vp-p f = 5MHz 3rd Harmonic 2nd Harmonic

TYPICAL PERFORMANCE CURVES: V S = +5V (Cont.) At TA = 25°C, G = +2, RF = 750Ω , and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1). –30 –40 –50 –60 –70 –80 –90 TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS Single-Tone Load Power (dBm) 3rd-Order Spurious Level (dBc) Load Power at Matched 50Ω Load fO = 1MHz fO = 5MHz fO = 10MHz 100 INPUT NOISE DENSITY vs FREQUENCY Frequency (Hz) 100 1K 10K 100K 1M 10M Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) Voltage Noise, eni = 6.0nV/√Hz Current Noise, ini = 1.9pA/√Hz 100 –10 –20 OPEN-LOOP GAIN AND PHASE Frequency (Hz) 1K 10K 100K 1M 10M 100M 1G Open-Loop Gain (dB) –30 –60 –90 –120 –150 –180 –210 –240 –270 –300 –330 –360 Open-Loop Phase (°) Open-Loop Phase Open-Loop Gain –30 –40 –50 –60 –70 –80 HARMONIC DISTORTION vs NON-INVERTING GAIN Gain Magnitude (V/V) 11 0 Harmonic Distortion (dBc) VO = 2Vp-p f = 5MHz 3rd Harmonic 2nd Harmonic FREQUENCY RESPONSE vs CAPACITIVE LOAD Frequency (MHz) 1 10 100 300 Normalized Gain (dB) R S1/2 OPA2631 VO 1kΩC L +VS/2 C L = 100pF R S = 35.7Ω C L =1000pF R S = 10Ω C L = 10pF R S = 249Ω 1000 100 RECOMMENDED R S vs CAPACITIVE LOAD Capacitive Load (pF) 1 10 100 1000 R S (Ω )

TYPICAL PERFORMANCE CURVES: V S = +5V (Cont.) At TA = 25°C, G = +2, RF = 750Ω , and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1). 100 0.1 CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY Frequency (Hz) 1k 10k 100k 1M 10M 100M Output Impedance (Ω ) G = +1 R F = 25Ω 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 INPUT DC ERRORS vs TEMPERATURE Temperature (°C) –40 –20 0 20 40 60 80 100 Input Offset Voltage (mV) Input Bias Current (µA) 10x Input Offset Current (µA) Input Offset Voltage Input Bias Current 10X Input Offset Current POWER SUPPLY AND OUTPUT CURRENT vs TEMPERATURE Temperature (°C) –40 –20 0 20 40 60 80 100 Quiescent Supply Current (mA) 120 100 Output Current (mA) Sinking Output Current Sourcing Output Current Quiescent Supply Current

–12 –15 –18 –21 –24 SMALL-SIGNAL FREQUENCY RESPONSE Frequency (MHz) Normalized Gain (dB) 1 10 100 300 VO = 200mVp-p G = +10 G = +2 G = +5 –12 –15 –18 LARGE-SIGNAL FREQUENCY RESPONSE Frequency (MHz) Gain (dB) 1 10 100 300 VO = 2Vp-p VO = 200mVp-p VO = 1Vp-p TYPICAL PERFORMANCE CURVES: V S = +3V At TA = 25°C, G = +2, RF = 750Ω , and RL = 150Ω to VS /2, unless otherwise noted (see Figure 1). –30 –40 –50 –60 –70 –80 –90 TWO-TONE, 3rd-ORDER INTERMODULATION SPURIOUS Single-Tone Load Power (dBm) 3rd-Order Spurious Level (dBc) Load Power at Matched 50Ω Load fO = 10MHz fO = 1MHz fO = 5MHz 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 OUTPUT SWING vs LOAD RESISTANCE R L (Ω ) 50 100 1000 Maximum Output Voltage (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Minimum Output Voltage (V) Maximum V O Minimum VO –12 –15 –18 –21 –24 FREQUENCY RESPONSE vs CAPACITIVE LOAD Frequency (MHz) 1 10 100 300 Normalized Gain (dB) VO = 0.2Vp-p R S1/2 OPA2631 VO 1kΩC L +VS/2 C L = 100pF R S = 35.7Ω C L = 1000pF R S = 10Ω C L = 10pF R S = 249Ω 1000 100 RECOMMENDED R S vs CAPACITIVE LOAD Capacitive Load (pF) 1 10 100 1000 R S (Ω )

TYPICAL PERFORMANCE CURVES: V S = +3V (Cont.) At TA = 25°C, G = +2, RF = 750Ω , and RL = 150Ω to VS /2, unless otherwise noted (see Figure 2). 120 100 SLEW RATE AND GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE Supply Voltage (V) 34 56 78 9 1 0 Slew Rate (V/µs) 120 100 Gain Bandwidth Product (MHz) Slew Rate Gain Bandwidth Product SUPPLY AND OUTPUT CURRENTS vs SUPPLY VOLTAGE Supply Voltage (V) 34 56 78 9 1 0 Quiescent Supply Current (mA/chan) 200 180 160 140 120 100 Output Current (mA) Quiescent Supply Current Output Current, Sourcing Output Current, Sinking

reduce the output DC error caused by this current. This is done by matching the DC source resistances appearing at the two inputs. Evaluating the configuration of Figure 1 (which has matched DC input resistances), using worst-case +25°C input offset voltage and current specifications, gives a worst- case output offset voltage equal to: (NG = non-inverting signal gain at DC) ±(NG • V OS(MAX) ) ± (RF • IOS(MAX) ) = ±6.8mV = Output Offset Range for Figure 1 A fine scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most of these techniques are based on adding a DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the non-inverting input may be considered. Bring the DC offsetting current into the inverting input node through resistor values that are much larger than the signal path resistors. This will insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response. THERMAL ANALYSIS Maximum desired junction temperature will set the maxi- mum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (T J) is given by TA + PD •θJA. The total internal power dissipation (PD ) is the sum of quiescent power (PDQ ) and additional power dissipated in the output stage (PDL ) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. P DL will depend on the required output signal and load but would, for resistive load connected to mid-supply (V S/2), be at a maximum when the output is fixed at a voltage equal to VS/4 or 3VS/4. Under this condition, PDL = VS2/(16 • RL), where RL includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a 150Ω load at mid-supply, for both channels: P Maximum T J = +85°C + (0.16W • 150°C/W) = 109°C. Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower guaranteed junction temperatures. The highest possible internal dissipation will occur if the load requires current to be forced into the output at high output voltages or sourced from the output at low output voltages. This puts a high current through a large internal voltage drop in the output transistors. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier like the OPA2631 requires careful attention to board layout parasitics and external component types. Rec- ommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the non- inverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted ca- pacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbro- ken elsewhere on the board. b) Minimize the distance (<0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capaci- tors. An optional supply decoupling capacitor (0.1µF) across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external compo- nents will preserve the high frequency performance. Resistors should be a very low reactance type. Surface- mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board traces as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface- mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ , this parasitic capaci-