A25D40 AITSEMI | Alldatasheet
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AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 1 - DESCRIPTION FEATURES The A25D40 is 4 M-bit Serial Peripheral Interface (SPI) Flash memory, and supports the Dual SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO). The Dual Output data is transferred with speed of 108Mbits/s. The device uses a single low voltage power supply, ranging from 2.7 Volt to 3.6 Volt. Additionally, the device supports JEDEC standard manufacturer and device ID. The A25D40 is available in SOP8, TSSOP8 and DFN8(2x3) packages.
ORDERING INFORMATION
SPQ: 2,500pcs/Reel SPQ: 100pcs/Tube 208mil SPQ: 2,000pcs/Reel SPQ: 95pcs/Tube A25D40M8R-X A25D40M8U-X A25D40M8VR-X A25D40M8VU-X TSSOP8 173mil SPQ: 5,000pcs/Reel SPQ: 100pcs/Tube TMX8 A25D40TMX8R A25D40TMX8U A25D40TMX8VR A25D40TMX8VU DFN8(2x3) SPQ: 3,000pcs/Reel A25D40J8R A25D40J8VR Note X: Package Type A: 150mil B: 208mil V: Halogen free Package R: Tape & Reel U: Tube AiT provides all RoHS products Serial Peripheral Interface (SPI) -Standard SPI: SCLK, /CS, SI, SO, /WP -Dual SPI: SCLK, /CS, IO0, IO1, /WP Read -Normal Read (Serial): 55MHz clock rate -Fast Read (Serial): 108MHz clock rate -Dual Read: 108MHz clock rate Program -Serial-input Page Program up to 256bytes Erase -Block erase (64/32 kB) -Sector erase (4 kB) -Chip erase Program/Erase Speed -Page Program time: 0.7ms typical -Sector Erase time: 100ms typical -Block Erase time: 0.3/0.5s typical -Chip Erase time: 3s typical Flexible Architecture -Sector of 4k-byte -Block of 32/64k-byte Low Power Consumption -20mA maximum active current -5uA maximum power down current Software/Hardware Write Protection -Enable/Disable protection with WP Pin -Write protect all/portion of memory via software -Top or Bottom, Sector or Block selection Single Supply Voltage -Full voltage range: 2.7~3.6V Temperature Range -Commercial (0℃ to +70℃) -Industrial (-40℃ to +85℃) Cycling Endurance/Data Retention -Typical 100k Program -Erase cycles on any sector -Typical 20-year data retention at +55℃ Available in SOP8, TSSOP8 and DFN8 (2x3) packages
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 2 - PIN DESCRIPTION Top View Top View Top View Pin # Symbol I/O Function SOP8 TSSOP8 DFN8 (2x3) 1 1 1 /CS I Chip Select 2 2 2 SO (IO1) I/O Serial Output for single bit data Instructions. IO1 for Dual Instructions. 3 3 3 /WP (IO2) I Write Protect in single bit 4 4 4 VSS - Ground. 5 5 5 SI (IO0) I/O Serial Input for single bit data Instructions. IO0 for Dual Instructions. 6 6 6 SCLK I Serial Clock 7 7 7 /HOLD - It must be higher than VIH 8 8 8 VCC - Core and I/O Power Supply SIGNAL DESCRIPTION During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of V IH, VOH, VIL or VOL, DC Electrical Characteristics on page 5). These signals are described next.
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 3 - ABSOLUTE MAXIMUM RATINGS VCC, Supply Voltage -0.5V～4V VIO , Voltage Applied to Any Pin Relative to Ground -0.5V～4V VIOT, Transient Voltage on Any Pin <20ns Transient Relative to Ground -2.0V ~ VCC+2.0V TSTG, Storage Temperature -65°C ～+150°C VESD, Electrostatic Discharge Voltage Human Body ModelNOTE1 -2000V ~ +2000V Stress beyond above listed “Absolute Maximum Ratings” may lead permanent damage to the device. These are stress ratings only and operations of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE1: JEDEC Std JESD22-A114 (C1=100pF, R1=1500 ohms, R2=500 ohms) OPERATING RANGES Parameter Symbol Conditions Min. Typ. Max. Unit Supply Voltage VCC 2.7 - 3.6 V Temperature Operating TA Commercial Industrial -40 +70 +85 DATA RETENTION AND ENDURANCE Parameter Conditions Min. Typ. Max. Unit Minimum Pattern Data Retention Time 150°C 10 - - Years 125°C 20 - - Years Erase/Program Endurance -40 to 85°C 100k - - Cycles
Figure 1. Power-up Timing and Voltage Levels
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 5 - DC ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min. Typ. Max. Unit. Input Leakage Current ILI - - ±2 µA Output Leakage Current ILO - - ±2 µA Standby Current ICC1 /CS=VCC, VIN=VCC or VSS - 13 25 µA Deep Power-Down Current ICC2 /CS=VCC, VIN=VCC or VSS - 2 5 µA Operation Current: (Read) ICC3 SCLK=0.1VCC/0.9VCC NOTE1 at 108MHz, Q=Open(*1,*2,*4 I/O) - 13 18 mA Operating Current(PP) ICC4 /CS=VCC - - 15 mA Operating Current (WRSR) ICC5 /CS=VCC - - 5 mA Operating Current (Sector Erase) ICC6 /CS=VCC - - 20 mA Operating Current (Block Erase) ICC7 /CS=VCC - - 20 mA Operating Current (Chip Erase) ICC8 /CS=VCC - - 20 mA Input Low Voltage VIL -0.5 - 0.2VCC V Input High Voltage VIH 0.8VCC - VCC+0.4 V Output Low Voltage VOL IOL=100µA - - 0.4 V Output High Voltage VOH IOH=-100µA VCC-0.2 - - V NOTE1: ICC3 is measured with ATE loading AC MEASUREMENT CONDITIONS Parameter Symbol Conditions Min Typ. Max Unit Load Capacitance CL - - 30 pF Input Rise and Fall Time tR, tF - - 5 ns Input Pause Voltage VIN 0.2VCC to 0.8VCC V Input Timing Reference Voltage IN 0.5VCC V Output Timing Reference Voltage OUT 0.5VCC V
Figure 2. AC Measurement I/O Waveform Parameter Symbol Min. Typ. Max. Unit.
Table 1. Block/Sector Addresses of A25D40 NOTE1: Block = Uniform Block, and the size is 64k bytes. NOTE2: Half block = Half Uniform Block, and the size is 32k bytes. NOTE3: Sector = Uniform Sector, and the size is 4k bytes.
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 9 - LOGIC DIAGRAM SPI OPERATION Standard SPI Instructions The A25D40 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI Instructions The A25D40 supports Dual SPI operation when using the “Dual Output Fast Read” (3BH) instructions. These instructions allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 10 - OPERATION FEATURES 1. Supply Voltage Operating Supply Voltage Prior to selecting the memory and issuing instructions to it, a valid and stable V CC voltage within the specified [VCC(min), VCC(max)] range must be applied (s ee operating ranges of page 3). In order to secure a stable DC supply voltage, it is recommended to decouple the V CC line with a suitable capaci tor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins. This voltage must remain stable a nd valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). Power-up Conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to VCC via a suitable pull-up resistor. In addition, the Chip Select (/CS) input offers a built -in safety fea ture, as the /CS input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been high, prior to going Low to start the first operation. Device Reset In order to prevent inadvertent Write operations during power -up (continuous rise of V CC), a power on reset (POR) circuit is included. At Power -up, the device does not respond to any instruction until V CC has reached the power on reset threshold voltage (this threshold is lower than the minimum V CC operating voltage defined in operating ranges of page 3). When VCC has passed the POR threshold, the device is reset. Power-down At Power-down (continuous decrease in V CC), as soon as V CC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should b e allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress).
- Active Power and Standby Power Modes
device then goes in to the Standby Power mode, and the device consumption drops to I CC1. Table 2. Status Register when WIP bit sets 0, means the device is not in program/erase/write status register progress. Program or Erase instruction is accepted. BP0) bits can be written provided that the Hardware Protected mode has not been set. Status Register (WRSR) instruction is not execution. The default value of SRP is 0.
- Software Protection: The Block Protect (BP2, BP1, BP0) bits define the section of the memory array that
- Hardware Protection: /WP going low to protected the BP0~BP2 bits and SRP bits.
- Deep Pow er-Down: In Deep Power -Down Mode, all instructions are ignored except the Release from
deep Power-Down Mode instruction.
- Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program, Sector Erase,
Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.
- Status Register Memory Protection
Table 3. A25D40 Status Register Memory Protection
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 13 - DEVICE IDENTIFICATION Three legacy Instructions are supported to access device identification that can indicate the manufacturer, device type, and capacity (density). The returned data bytes provide the information as shown in the below table. A25D40 ID Definition table Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH 68 40 13 90H 68 12 ABH 12 INSTRUCTIONS DESCRIPTION All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 4, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by dat a bytes, or by both or none. /CS must be driven high after the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read Status Register or Release from Deep Power Down, and Read Device ID, the shifted -in instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the data -out sequence is being shifted out. For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must drive high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
Table 4. Instruction Set Table
incremented to the next higher address after each byte of data is shifted out. Figure 11. Dual Output Fast Read Sequence Diagram
- ID and Security Instructions
Figure 12. Read Manufacture ID/ Device ID Sequence Diagram not be issued while the device is in Deep Power-Down Mode. receive, decode and execute instructions.
driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 15. protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 15. Deep Power-Down Sequence Diagram release the device from the Power-Down state or obtain the devices electronic identification (ID) number. instruction are accepted. The /CS pin must remain high during the tRES1 time duration. are then shifted out on the falling edg e of SCLK with most significant bit (MSB) first as shown in Figure 16b. can be read continuously. The instruction is completed by driving /CS high.
- Program and Erase Instructions
have been executed to set the Write Enable Latch bit before sending the Page Program instruction. instruction is not executed. Figure 17. Page Program Sequence Diagram
valid address for the Sector Erase instruction. /CS must be driven low for the entire duration of the sequence. sector which is protected by the Block Protect (BP2, BP1, BP0) bits is not executed. Figure 18. Sector Erase Sequence Diagram
“C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 21. still be accessed to check the status of the WIP bit. the Block Protect (BP2, BP1, and BP0) bits. Figure 21. Chip Erase Sequence Diagram
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 27 -
PACKAGE INFORMATION
Dimension in SOP8 150-mil (Unit: mm) Symbol Min Max A - 1.75 A1 0.10 0.225 A2 1.30 1.50 b 0.39 0.47 C 0.20 0.24 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 e 1.27 BSC L 0.50 0.80 L1 1.05 BSC S 0.41 0.67 θ 0° 8°
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 28 - Dimension in SOP8 208-mil (Unit: mm) Symbol Min Max A - 1.95 A1 0.10 0.18 A2 1.75 1.90 b 0.42 0.48 C 0.20 0.24 D 5.00 5.25 E 7.85 7.98 E1 5.16 5.26 e 1.27 BSC L 0.60 0.70 L1 1.31 1.41 S 0.62 0.88 θ 0° 8°
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 29 - Dimension in TSSOP8 173-mil (Unit: mm) Symbol Min Max A - 1.20 A1 0.05 0.15 A2 0.90 1.05 A3 0.39 0.49 b 0.20 0.28 b1 0.19 0.25 c 0.13 0.17 c1 0.12 0.14 D 2.90 3.10 E 6.20 6.60 E1 4.30 4.50 e 0.65 BSC L 0.45 0.75 L1 1.00 BSC θ 0° 8°
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 30 - Dimension in DFN8(2x3mm) (Unit: mm) Symbol Min Max A 0.45 0.55 A1 0.00 0.05 b 0.20 0.30 c 0.10 0.20 D 1.90 2.10 D2 1.50 1.70 e 0.50 BSC Nd 1.50 BSC E 2.90 3.10 E2 0.10 0.30 L 0.30 0.40 L1 0.05 0.15 h 0.05 0.25
AiT Semiconductor Inc. www.ait-ic.com A25D40 MEMORY SPI NOR FLASH 4M BIT REV1.0 - SEP 2019 RELEASED - - 31 - IMPORTANT NOTICE AiT Semiconductor Inc. (AiT) reserves the right to make changes to any its product, specifications, to discontinue any integrated circuit product or service without n otice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AiT Semiconductor Inc. 's integrated circuit products are not designed, intended, autho rized, or warranted to be suitable for use in life support applications, devices or systems or other critical applications. Use of AiT products in such applications is understood to be fully at the risk of the customer. As used herein may involve potential risks of death, personal injury, or servere property, or environmental damage. In order to minimize risks associated with the customer's applications, the customer should provide adequate design and operating safeguards. AiT Semiconductor Inc . assumes to no liability to customer product design or application support. AiT warrants the performance of its products of the specifications applicable at the time of sale.