A21SP16 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 37
Technical content
Datasheet sections
- 1 Absolute maximum ratings
- 2 Application component informati on
- 3 Electrical characteristics
- 4 Electrical characteristic curves
- 5 Application information
- 5.1 Differential configuration principle
- 5.2 Gain in typical application schematic
- 5.3 Common mode feedback loop limi tations
- 5.4 Low frequency response
- 5.5 Decoupling of the circuit
- 5.6 Wake-up time (t WU)
- 5.7 Shutdown time (t STBY)
- 5.8 Consumption in shutdown mode
- 5.9 Single-ended input configuration
- 5.10 Output filter considerations
- 5.11 Different examples with su mmed inputs
- 6 Footprint recommendations
- 7 Package information
- 8 Revision history
Features
Operating from VCC = 2.4 V to 5.5 V Standby mode active low Output power: 3 W into 4 and 1.75 W into 8 with 10% THD+N max and 5 V power supply Output power: 2.3 W @ 5 V or 0.75 W @ 3 V into 4 with 1% THD+N max Output power: 1.4 W @ 5 V or 0.45 W @ 3 V into 8 with 1% THD+N max Adjustable gain via external resistors Low current consumption 2 mA @ 3 V Efficiency: 88% typ. Signal to noise ratio: 85 dB typ. PSRR: 63 dB typ. @ 217 Hz with 6 dB gain PWM base frequency: 250 kHz Low pop & click noise Thermal shutdown protection Available in flip-chip 9 x 300 m (Pb-free)
Applications
Wearable Fitness and healthcare Cellular phone PDA
Description
The A21SP16 is a differential class-D BTL power amplifier. It is able to drive up to 2.3 W into a 4 load and 1.4 W into a 8 load at 5 V. It achieves outstanding efficiency (88% typ.) compared to classical Class-AB audio amps. The gain of the device can be controlled via two external gain-setting resistors. Pop & click reduction circuitry provides low on/off switch noise while allowing the device to start within 5 ms. A standby function (active low) allows the reduction of current consumption to 10 nA typ. VDD 1/A1 7/C1 8/C2 9/C3 4/B1 6/B3 2/A2 3/A3 5/B2 VDD IN- IN+ GND STBY GND OUT+ OUT- VDD 1/A1 7/C1 8/C2 9/C3 4/B1 6/B3 2/A2 3/A3 5/B2 VDD IN- IN+ GND STBY GND OUT+ OUT- Pin connection IN+: positive differential input IN-: negative differential input VDD: analog power supply GND: power supply ground STBY: standby pin (active low) OUT+: positive differential output OUT-: negative differential outputIn- Stdby In+ Out- Out+ Vcc B1 B2 GND Internal Bias PWM Output Bridge H Oscillator 150k 150k - 300k Block diagram Table 1. Order codes
1 Absolute maximum ratings
Table 2. Absolute maximum ratings
- Caution: This device is not protected in the event of abnormal operating conditions, such as for example,
between individual output pins.
- All voltage values are measured with respect to the ground pin.
- The magnitude of the input signal must never exceed V CC + 0.3V / GND - 0.3V.
- The device is protected in case of over te mperature by a thermal shutdown active @ 150°C.
- Exceeding the power derating curves dur ing a long period causes abnormal operation.
- The magnitude of the standby signal must never exceed V CC + 0.3V / GND - 0.3V.
Table 3. Operating conditions
- For V CC from 2.4V to 2.5V, the operating temperature range is reduced to 0°C Tamb 70°C.
- For V CC from 2.4V to 2.5V, the common mode input range must be set at VCC/2.
- Without any signal on V STBY, the device will be in standby.
- Minimum current consumption is obtained when V STBY = GND.
- With heat sink surface = 125mm2.
2 Application component information
Figure 1. Typical application schematics Table 4. Component information added to enhance the power supply filtering at high frequency. Due to common mode feedback, these input capacitors are optional. -3dB cut-off frequency = 1/(2**Rin*Cin).
4 Ohms LC Output Filter
8 Ohms LC Output Filter
3 Electrical characteristics
Table 5. VCC = +5V, GND = 0V, VIC = 2.5V, tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217Hz.
Table 5. VCC = +5V, GND = 0V, VIC = 2.5V, tamb = 25°C (unless otherwise specified) (continued)
Table 6. VCC = +4.2V, GND = 0V, VIC =2 . 5 V , Tamb = 25°C (unless otherwise specified)(1)
- All electrical values are guaranteed with correlation measurements at 2.5 V and 5 V.
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217Hz.
Table 6. VCC = +4.2V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified)(1) (continued)
Table 7. VCC = +3.6V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified)(1)
- All electrical values are guaranteed with correlation measurements at 2.5V and 5V.
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217Hz.
Table 7. VCC = +3.6V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified)(1) (continued)
Table 8. VCC = +3V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified)(1)
- All electrical values are guaranteed with correlation measurements at 2.5 V and 5 V.
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217Hz.
Table 8. VCC = +3V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified)(1) (continued)
Table 9. VCC = +2.5V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
- Dynamic measurements - 20*log(rms(V out)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217Hz.
Table 9. VCC = +2.5V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified) (continued)
Table 10. VCC = +2.4V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified)
- Standby mode is active when V STBY is tied to GND.
4 Electrical characteristic curves
Figure 2. Test diagram for measurements Figure 3. Test diagram for PSRR measurements
5 Application information
5.1 Differential configuration principle
The A21SP16 is a monolithic fully-differential input/output class D power amplifier. The A21SP16 also includes a common-mode feedback loop that controls the output bias value to average it at VCC/2 for any DC common mode input voltage. This allows the device to always have a maximum output voltage swing, and by consequence, maximizes the output power. Moreover, as the load is connected differentially compared to a single-ended topology, the output is four times higher for the same power supply voltage. The advantages of a full-differential amplifier are: High PSRR (power supply rejection ratio). High common mode noise rejection. Virtually zero pop without additional circuitry, giving a faster start-up time compared to conventional single-ended input amplifiers. Easier interfacing with differential output audio DAC. No input coupling capacitors required due to common mode feedback loop. The main disadvantage is: As the differential function is directly linked to external resistor mismatching, paying particular attention to this mismatching is mandatory in order to obtain the best performance from the amplifier.
5.2 Gain in typical application schematic
Typical differential applications are shown in Figure 1 on page 4. In the flat region of the frequency-response curve (no input coupling capacitor effect), the differential gain is expressed by the relation: with Rin expressed in k Due to the tolerance of the internal 150 k feedback resistor, the differential gain will be in the range (no tolerance on Rin): AVdiff Out + Out -– In+ In-– Rin 273 Rin 327 Rin
Application information A21SP16
5.3 Common mode feedback loop limitations
As explained previously, the common mode feedback loop allows the output DC bias voltage to be averaged at VCC/2 for any DC common mode bias input voltage. However, due to Vicm limitation in the input stage (see Table 3: Operating conditions on page 3), the common mode feedback loop can ensure its role only within a defined range. This range depends upon the values of VCC and Rin (AVdiff). To have a good estimation of the Vicm value, we can apply this formula (no tolerance on Rin): with and the result of the calculation must be in the range: Due to the +/-9% tolerance on the 150k resistor, it’s also important to check Vicm in these conditions: If the result of Vicm calculation is not in the previous range, input coupling capacitors must be used (with VCC from 2.4 V to 2.5 V, input coupling capacitors are mandatory). For example: With VCC =3 V , Rin = 150 k and VIC = 2.5 V, we typically find Vicm = 2 V and this is lower So, no input coupling capacitors are required.
5.4 Low frequency response
If a low frequency bandwidth limitation is requested, it is possible to use input coupling capacitors. In the low frequency region, Cin (input coupling capacitor) starts to have an effect. Cin forms, with Rin, a first order high-pass filter with a -3dB cut-off frequency: So, for a desired cut-off frequency we can calculate Cin, with Rin in and FCL in Hz. Vicm VCC Rin 2V IC 150k+ VIC In+ In-+ 0.5V V icm VCC 0.8V– VCC Rin 2V IC 136.5k+ VCC Rin 2V IC 163.5k+ FCL Cin
5.5 Decoupling of the circuit
A power supply capacitor, referred to as CS, is needed to correctly bypass the A21SP16. The A21SP16 has a typical switching frequency at 250 kHz and output fall and rise time about 5 ns. Due to these very fast transients, careful decoupling is mandatory. A 1 µF ceramic capacitor is enough, but it must be located very close to the A21SP16 in order to avoid any extra parasitic inductance created an overly long track wire. In relation with dI/dt, this parasitic inductance introduces an overvoltage that decreases the global efficiency and, if it is too high, may cause a breakdown of the device. In addition, even if a ceramic capacitor has an adequate high frequency ESR value, its current capability is also important. A 0603 size is a good compromise, particularly when a 4 load is used. Another important parameter is the rated voltage of the capacitor. A 1 µF/6.3 V capacitor used at 5 V, loses about 50% of its value. In fact, with a 5 V power supply voltage, the decoupling value is about 0.5 µF instead of 1 µF. As C S has particular influence on the THD+N in the medium-high frequency region, this capacitor variation becomes decisive. In addition, less decoupling means higher overshoots, which can be problematic if they reach the power supply AMR value (6 V).
5.6 Wake-up time (t WU)
When the standby is released to set the device ON, there is a wait of about 5 ms. The A21SP16 has an internal digital delay that mutes the outputs and releases them after this time in order to avoid any pop noise.
5.7 Shutdown time (t STBY)
When the standby command is set, the time required to put the two output stages into high impedance and to put the internal circuitry in shutdown mode, is about 5 ms. This time is used to decrease the gain and avoid any pop noise during shutdown.
5.8 Consumption in shutdown mode
Between the shutdown pin and GND there is an internal 300 k resistor. This resistor forces the A21SP16 to be in standby mode when the standby input pin is left floating. However, this resistor also introduces additional power consumption if the shutdown pin voltage is not 0 V. For example, with a 0.4 V standby voltage pin, Table 3: Operating conditions on page 3, shows that you must add 0.4 V/300 k= 1.3 µA in typical (0.4 V/273 k= 1.46 µA in maximum) to the shutdown current specified in Table 5 on page 5.
5.9 Single-ended input configuration
It is possible to use the A21SP16 in a single-ended input configuration. However, input coupling capacitors are needed in this configuration. The schematic in Figure 61 shows a single-ended input typical application.
same rule, that is, to equalize impedance on both A21SP16 inputs.
5.10 Output filter considerations
different for each configuration, it is difficult to provide a one-size-fits-all solution. Use ground planes for “shielding” sensitive wires. possible examples of devices you can use. ground (see the schematics in Figure 63). Figure 63. Method for shorting pertubations to ground
5.11 Different example s with summed inputs
Figure 64. Typical application schematic with dual differential inputs
Figure 65. Typical application schematic with one differential input plus one single-
6 Footprint recommendations
Figure 66. Footprint recommendations
7 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 67. Pin-out for 9-bump flip-chip (top view) Figure 68. Marking for 9-bump flip-chip (top view) Figure 69. Mechanical data for 9-bump flip-chip
8 Revision history
Table 11. Document revision history 06-Mar-2014 1 Initial release.