A1425

Actel Corporation

Highly Predictable Performance with 100% Automatic Placement and Routing

Manufacturer: Actel Corporation

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A1010B-PLG68I ACTEL | Alldatasheet

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Features

Highly Predictable Performance with 100% Automatic Placement and Routing
Device Sizes from 1,200 to 20,000 Gates
Up to 6 Fast, Low-Skew Clock Networks
Up to 202 User-Programmable I/O Pins
More Than 500 Macro Functions
Up to 1,276 Dedicated Flip-Flops
I/O Drive to 10 mA
Devices Available to DSCC SMD
CQFP and CPGA Packaging
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
100% Military Temperature Tested (–55°C to +125°C)
QML Certified Devices
Proven Reliability Data Available
Successful Military/Avionics Supplier for Over 10 Years ACT 3 Features
Highest-Performance, Highest-Capacity FPGA Family
System Performance to 60 MHz over Military Temperature
Low-Power 0.8µ CMOS Technology 3200DX Features
100 MHz System Logic Integration
Highest Speed FPGA SRAM, up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Low-Power 0.6µ CMOS Technology 1200XL Features
Pin for Pin Compatible with ACT 2
System Performance to 50 MHz over Military Temperature
Low-Power 0.6µ CMOS Technology ACT 2 Features
Best-Value, High-Capacity FPGA Family
System Performance to 40 MHz over Military Temperature
Low-Power 1.0µ CMOS Technology ACT 1 Features
Lowest-Cost FPGA Family
System Performance to 20 MHz over Military Temperature
Low-Power 1.0µ CMOS Technology Product Family Profile (more devices on page 2) Family 3200DX ACT 3 1200XL Device A32100DX A32200DX A1425A A1460A A14100A A1280XL Capacity System Gates Logic Gates SRAM Bits 15,000 10,000 2,048 30,000 20,000 2,560 3,750 2,500 NA 9,000 6,000 NA 15,000 10,000 NA 12,000 8,000 Logic Modules S-Modules C-Modules Decode 1,362 700 662 2,414 1,230 1,184 310 160 150 NA 848 432 416 NA 1,377 697 680 NA 1,232 624 608 NA Flip-Flops (Maximum) 738 1,276 435 976 1,493 998 User I/Os (Maximum) 152 202 100 168 228 140 Performance System Speed (maximum) 55 MHz 55 MHz 60 MHz 60 MHz 60 MHz 50 MHz Packages (by Pin Count) CPGA CQFP 84 208, 256 133 132 207 196 257 256 176 172

High-Reliability, Low-Risk Solution Actel builds the most reliable field programmable gate arrays (FPGAs) in the industry, with overall antifuse reliability ratings of less than 10 Failures-In-Time (FITs), corresponding to a useful life of more than 40 years. Actel FPGAs have been production proven, with more than five million devices shipped and more than one trillion antifuses manufactured. Actel devices are fully tested prior to shipment, with an outgoing defect level of less than 100 ppm. (Further reliability data is available in the Actel Device Reliability Report, at http://www.actel.com/hirel). Benefits Minimized Cost Risk With Actel’s line of development tools, designers can produce as many chips as they choose for just the cost of the device itself. There will be no NRE charges to cut into the development budget each time a new design is tried. Minimized Time Risk After the design is entered, placement and routing is automatic, and programming the device takes only about 5 to 15 minutes for an average design. Designers save time in the design entry process by using tools with which they are familiar. Minimized Reliability Risk The PLICE antifuse is a one-time programmable, nonvolatile connection. Since Actel devices are permanently programmed, no downloading from EPROM or SRAM storage is required. Inadvertent erasure is impossible, and there is no need to reload the program after power disruptions. Fabrication using a low-power CMOS process means cooler junction temperatures. Actel’s non-PLD architecture delivers lower dynamic operating current. Our reliability tests show a very low failure rate of 6.6 FITs at 90°C junction temperature with no degradation in AC performance. Special stress testing at wafer test eliminates infant mortalities prior to packaging. Minimized Security Risk Reverse engineering of programmed Actel devices from optical or electrical data is extremely difficult. Programmed antifuses cannot be identified from a photograph or by using an SEM. The antifuse map cannot be deciphered either electrically or by microprobing. Each device has a silicon signature that identifies its origins, down to the wafer lot and fabrication facility. Minimized Testing Risk Unprogrammed Actel parts are extensively tested at the factory. Routing tracks, logic modules, and programming, debug and test circuits are 100 percent tested before shipment. AC performance is ensured by special speed path tests, and programming circuitry is verified on test antifuses. During the programming process, an algorithm is run to ensure that all antifuses are correctly programmed. In addition, Actel’s Silicon Explorer diagnostic tool uses ActionProbe circuitry, allowing 100 percent observability of all internal nodes to check and debug the design. Actel FPGA Description The Actel families of FPGAs offer a variety of packages, speed/performance characteristics, and processing levels for use in all high reliability and military applications. Devices are implemented in a silicon gate, two-level metal CMOS process, utilizing Actel’s PLICE antifuse technology. This Product Family Profile Family ACT 2 ACT 1 Device A1240A A1280A A1010B A1020B Capacity System Gates Logic Gates SRAM Bits 6,000 4,000 NA 12,000 8,000 NA 1,800 1,200 NA 3,000 2,000 NA Logic Modules S-Modules C-Modules Decode 684 348 336 NA 1,232 624 608 NA 295 295 NA 547 547 NA Flip-Flops (maximum) 568 998 147 273 User I/Os (maximum) 104 140 57 69 Packages (by pin count) CPGA CQFP 132 176 172 Performance System Speed (maximum) 40 MHz 40 MHz

20 MHz 20 MHz

unique architecture offers gate array flexibility, high performance, and quick turnaround through user programming. Device utilization is typically 95 percent of available logic modules. All Actel devices include on-chip clock drivers and a hard-wired distribution network. User-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages for the military are the Ceramic Quad Flat Pack (CQFP) and the Ceramic Pin Grid Array (CPGA). See the “Product Plan” section on page 6 for details. QML Certification Actel has achieved full QML certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the Department of Defense for monolithic integrated circuits. QML certification is a good example of Actel's commitment to supplying the highest quality products for all types of high-reliability, military and space applications. Many suppliers of microelectronics components have implemented QML as their primary worldwide business system. Appropriate use of this system not only helps in the implementation of advanced technologies, but also allows for a quality, reliable and cost-effective logistics support throughout QML products’ life cycles. Development Tool Support The HiRel devices are fully supported by Actel’s line of FPGA development tools, including the Actel DeskTOP series and Designer Advantage tools. The Actel DeskTOP Series is an integrated design environment for PCs that includes design entry, simulation, synthesis, and place and route tools. Designer Advantage is Actel’s suite of FPGA development point tools for PCs and Workstations that includes the ACTgen Macro Builder, Designer with DirectTime timing driven place and route and analysis tools, and device programming software. In addition, the HiRel devices contain ActionProbe circuitry that provides built-in access to every node in a design, enabling 100 percent real-time observation and analysis of a device’s internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer, an easy to use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer attaches to a PC’s standard COM port, turning the PC into a fully functional 18 channel logic analyzer. Silicon Explorer allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. ACT 3 Description The ACT 3 family is the third-generation Actel FPGA family. This family offers the highest-performance and highest-capacity devices, ranging from 2,500 to 10,000 gates, with system performance up to 60 MHz over the military temperature range. The devices have four clock distribution networks, including dedicated array and I/O clocks. In addition, the ACT 3 family offers the highest I/O-to-gate ratio available. ACT 3 devices are manufactured using 0.8µ CMOS technology. 1200XL/3200DX Description 3200DX and 1200XL FPGAs were designed to integrate system logic which is typically implemented in multiple CPLDs, PALs, and FPGAs. These devices provide the features and performance required for today’s complex, high-speed digital logic systems. The 3200DX family offers the industry’s fastest dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. ACT 2 Description The ACT 2 family is the second-generation Actel FPGA family. This family offers the best-value, high-capacity devices, ranging from 4,000 to 8,000 gates, with system performance up to 40 MHz over the military temperature range. The devices have two routed array clock distribution networks. ACT 2 devices are manufactured using 1.0µ CMOS technology. ACT 1 Description The ACT 1 family is the first Actel FPGA family and the first antifuse-based FPGA. This family offers the lowest-cost logic integration, with devices ranging from 1,200 to 2,000 gates, with system performance up to 20 MHz over the military temperature range. The devices have one routed array clock distribution network. ACT 1 devices are manufactured using 1.0µ CMOS technology.

Military Device Ordering Information Application (Temperature Range) C= Commercial (0 to +70°C) M = Military (–55 to +125°C) B = MIL-STD-883 Class B E = Extended Flow (Space Level) Package T ype CQ = Ceramic Quad Flat Pack (CQFP) PG = Ceramic Pin Grid Array (CPGA) Speed Grade Std = Standard Speed –1 = Approximately 15% faster than Standard Part Number A1010 = 1,200 Gates—ACT 1 A1020 = 2,000 Gates—ACT 1 A1240 = 4,000 Gates—ACT 2 A1280 = 8,000 Gates—ACT 2/1200XL A1425 = 2,500 Gates—ACT 3 A1460 = 6,000 Gates—ACT 3 A14100 = 10,000 Gates—ACT 3 A32100 = 10,000 Gates—3200DX A32200 = 20,000 Gates—3200DX Device Revision Package Lead Count A14100 CQ 256 B 1A –

DESC SMD/Actel Part Number Cross Reference Actel Part Number DSCC SMD DSCC SMD (Gold Leads) (Gold Leads) (Solder Dipped) A1010B-PG84B 5962-9096403MXC 5962-9096403MXA A1010B-1PG84B 5962-9096404MXC 5962-9096404MXA A1020B-PG84B 5962-9096503MUC 5962-9096503MUA A1020B-1PG84B 5962-9096504MUC 5962-9096504MUA A1020B-CQ84B 5962-9096503MTC 5962-9096503MTA A1020B-1CQ84B 5962-9096504MTC 5962-9096504MTA A1240A-PG132B 5962-9322101MXC 5962-9322101MXA A1240A-1PG132B 5962-9322102MXC 5962-9322102MXA A1280A-PG176B 5962-9215601MXC 5962-9215601MXA A1280A-1PG176B 5962-9215602MXC 5962-9215602MXA A1280A-CQ172B 5962-9215601MYC 5962-9215601MYA A1280A-1CQ172B 5962-9215602MYC 5962-9215602MYA A1425A-PG133B 5962-9552001MXC N/A A1425A-1PG133B 5962-9552002MXC N/A A1425A-CQ132B 5962-9552001MYC N/A A1425A-1CQ132B 5962-9552002MYC N/A A1460A-PG207B 5962-9550801MXC N/A A1460A-1PG207B 5962-9550802MXC N/A A1460A-CQ196B 5962-9550801MYC N/A A1460A-1CQ196B 5962-9550802MYC N/A A14100A-PG257B 5962-9552101MXC N/A A14100A-1PG257B 5962-9552102MXC N/A A14100A-CQ256B 5962-9552101MYC N/A A14100A-1CQ256B 5962-9552102MYC N/A A32100DX-CQ84B 5962-9875901QXC N/A A32100DX-1CQ84B 5962-9857902QXC N/A A32200DX-CQ256B 5962-9952701QXC N/A A32200DX-1CQ256B 5962-9952702QXC N/A A32200DX-CQ208B 5962-9952701QYC N/A A32200DX-1CQ208B 5962-9952702QYC N/A

Applications: C = Commercial Availability: ✔ = Available *Speed Grade: –1 = Approx. 15% faster than Standard M= M i l i t a r y — = Not Planned B = MIL-STD-883 E = Extended Flow Speed Grade Application 3200DX Family Std –1* C M B E A32100DX Device 84-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔ — A32200DX Device 208-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔ — 256-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔ — ACT 3 Family A1425A Device 132-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔ 133-pin Ceramic Pin Grid Array (CPGA) ✔✔ ✔✔✔✔ A1460A Device 196-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔ 207-pin Ceramic Pin Grid Array (CPGA) ✔✔ ✔✔✔✔ A14100A Device 256-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔ 257-pin Ceramic Pin Grid Array (CPGA) ✔✔ ✔✔✔✔ 1200XL Family A1280XL Device 172-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔ — 176-pin Ceramic Pin Grid Array (CPGA) ✔✔ ✔✔✔ — ACT 2 Family A1240A Device 132-pin Ceramic Pin Grid Array (CPGA) ✔✔ ✔✔✔ — A1280A Device 172-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔ 176-pin Ceramic Pin Grid Array (CPGA) ✔✔ ✔✔✔✔ ACT 1 Family A1010B Device 84-pin Ceramic Pin Grid Array (CPGA) ✔✔ ✔✔✔ — A1020B Device 84-pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔ 84-pin Ceramic Pin Grid Array (CPGA) ✔✔ ✔✔✔✔

A32100DX 1,362 10,000 60 —— A32200DX 2,414 20,000 — 176 202 User I/Os FPGA Device Type Logic Modules Gate Array Equivalent Gates CQFP CPGA 132-pin 196-pin 256-pin 133-pin 207-pin 257-pin A1425A 310 2,500 100 — — 100 — — A1460A 848 6,000 — 168 — — 168 — A14100A 1,377 10,000 — — 228 — — 228 User I/Os FPGA Device Type Logic Modules Gate Array Equivalent Gates CQFP CPGA 172-pin 176-pin A1280XL 1,232 8,000 140 140 User I/Os FPGA Device Type Logic Modules Gate Array Equivalent Gates CQFP CPGA 172-pin 132-pin 176-pin A1240A 684 4,000 — 104 — A1280A 1,232 8,000 140 — 140 User I/Os FPGA Device Type Logic Modules Gate Array Equivalent Gates CQFP CPGA 84-pin 84-pin A1010B 295 1,200 — 57 A1020B 547 2,000 69 69

Actel MIL-STD-883 Product Flow Step Screen 883 Method 883—Class B Requirement 1. Internal Visual 2010, T est Condition B 100% 2. T emperature Cycling 1010, T est Condition C 100% 3. Constant Acceleration 2001, T est Condition D or E, Y 1, Orientation Only 100% 4. Seal a. Fine b. Gross 1014 100% 100% 5. Visual Inspection 2009 100% 6. Pre-Burn-In Electrical Parameters In accordance with applicable Actel device specification 100% 7. Burn-in T est 1015, Condition D, 160 hours @ 125°C or 80 hours @ 150°C 100% 8. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification 100% 9. Percent Defective Allowable 5% All Lots 10. Final Electrical T est a. Static Tests (1) 25°C (Subgroup 1, Table I) (2) –55°C and +125°C (Subgroups 2, 3, T able I) b. Functional Tests (1) 25°C (Subgroup 7, Table I) (2) –55°C and +125°C (Subgroups 8A and 8B, T able I) c. Switching Tests at 25°C (Subgroup 9, Table I) In accordance with applicable Actel device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 11. External Visual 2009 100% Note: When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method 2018 must be waived.

Notes: 1. Actel offers the extended flow for customers who require additional screening beyond the requirements of the MIL-STD-833, Cla ss B. Actel is compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flo w incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004 are shown in notes 2 and 3 below. 2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived. 3. MIL-STD-883, Method 5004 requires 100 percent Radiation latch-up testing (Method 1020). Actel will not be performing any radiation testing, and this requirement must be waived in its entirety. Step Screen Method Require- ment 1. Wafer Lot Acceptance 2 5007 with Step Coverage Waiver All Lots 2. Destructive In-Line Bond Pull3 2011, Condition D Sample 3. Internal Visual 2010, Condition A 100% 4. Serialization 100% 5. Temperature Cycling 1010, Condition C 100% 6. Constant Acceleration 2001, Condition D or E, Y

1 Orientation Only 100%

Particle Impact Noise Detection 2020, Condition A 100% 8. Radiographic 2012 (one view only) 100% 9. Pre-Burn-In Test In accordance with applicable Actel device specification 100% 10. Burn-in Test 1015, Condition D, 240 hours @ 125°C minimum 100% 11. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification 100% 12. Reverse Bias Burn-In 1015, Condition C, 72 hours @ 150°C minimum 100% 13. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification 100% 14. Percent Defective Allowable (PDA) Calculation 5%, 3% Functional Parameters @ 25°C All Lots 15. Final Electrical Test a. Static T ests (1) 25°C (Subgroup 1, T able1) (2) –55°C and +125°C (Subgroups 2, 3, Table 1) b. Functional Tests (1) 25°C (Subgroup 7, T able 15) (2) –55°C and +125°C (Subgroups 8A and B, Table 1) c. Switching Tests at 25°C (Subgroup 9, Table 1) In accordance with Actel applicable device specification which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 100% 16. Seal a. Fine b. Gross 1014 100% 17. External Visual 2009 100%

Absolute Maximum Ratings 1 Free air temperature range Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions. 2. V PP = VCC , except during device programming. 3. V SV = VCC , except during device programming. 4. V KS = GND , except during device programming. 5. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5V or less than GND – 0.5V, the internal protection diode will be forward biased and can draw excessive current. Recommended Operating Conditions Notes: 1. Ambient temperature (T A) is used for commercial and industrial; case temperature (TC) is used for military. 2. All power supplies must be in the recommended operating range. For more information, refer to the Power-Up Design Considerations application note at http://www.actel.com/appnotes. Electrical Specifications Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. Tested one output at a time, V CC = min. 3. Not tested; for information only. 4. V OUT = 0V, f = 1 MHz Symbol Parameter Limits Units VCC DC Supply Voltage2, 3, 4 –0.5 to +7.0 V VI Input Voltage –0.5 to V CC +0.5 V VO Output Voltage –0.5 to V CC +0.5 V IIO I/O Source Sink Current5 ±20 mA TSTG Storage Temperature –65 to +150 °C Parameter Commercial Military Units T emperature Range 1 0 to +70 –55 to +125 °C Power Supply T olerance2 ±5 ±10 %V CC Symbol Parameter Test Condition Commercial Military UnitsMin. Max. Min. Max. VOH 1, 2 HIGH Level Output I OH = –4 mA (CMOS) 3.7 V IOH = –6 mA (CMOS) 3.84 V VOL 1, 2 LOW Level Output I OL = +6 mA (CMOS) 0.33 0.4 V VIH HIGH Level Input TTL Inputs 2.0 V CC + 0.3 2.0 V CC + 0.3 V VIL LOW Level Input TTL Inputs –0.3 0.8 –0.3 0.8 V IIN Input Leakage V I = VCC or GND –10 +10 –10 +10 µA IOZ 3-state Output Leakage V O = VCC or GND –10 +10 –10 +10 µA C IO I/O Capacitance3, 4 10 10 pF ICC(S) Standby VCC Supply Current VI = VCC or GND, IO = 0 mA ACT 1 3 20 mA ACT 2/3/1200XL/3200DX 2 20 mA I CC(D) Dynamic VCC Supply Current See the “Power Dissipation” section on page 11.

Package Thermal Characteristics The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. Maximum junction temperature is 150°C. A sample calculation of the absolute maximum power dissipation allowed for a CPGA 176-pin package at military temperature is as follows: Power Dissipation General Power Equation P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * (VCC – VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, on the design, and on the system I/O. The power can be divided into two components—static and active. Static Power Component Actel FPGAs have small static power components that result in power dissipation lower than that of PALs or PLDs. By integrating multiple PALs or PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst-case conditions. The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totempole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that Package Type Pin Count θjc θja Still Air θja 300 ft/min Units Ceramic Pin Grid Array 84 132 133 176 207 257 6.0 4.8 4.8 4.6 3.5 2.8 °C/W °C/W °C/W °C/W °C/W °C/W Ceramic Quad Flat Pack 84 132 172 196 256 7.8 7.2 6.8 6.4 6.2 °C/W °C/W °C/W °C/W °C/W Max. junction temp. (°C) – Max. military temp. Family I CC VCC Power ACT 3 2 mA 5.25V 10.5 mW 1200XL/3200DX 2 mA 5.25V 10.5 mW ACT 2 2 mA 5.25V 10.5 mW ACT 1 3 mA 5.25V 15.8 mW

can be combined with frequency and voltage to represent active power dissipation. Equivalent Capacitance The power dissipated by a CMOS circuit can be expressed by Equation 1: Power (uW) = C EQ * VCC 2 * F (1) where: Equivalent capacitance is calculated by measuring I CCactive at a specified frequency and voltage for each circuit component of interest. Measurements are made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below. CEQ Values for Actel FPGAs To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piecewise linear summation over all components that applies to all ACT 1, 1200XL, 3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has only one routed array clock, the terms labeled routed_Clk2, dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2 family has two routed array clocks, and the dedicated_Clk and IO_Clk terms do not apply. For ACT 3 devices, all terms will apply. Power = V CC 2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk]( 2 ) where: CEQ = Equivalent capacitance in pF VCC = Power supply in volts (V) F = Switching frequency in MHz ACT 3 1200XL 3200DX ACT 2 ACT 1 Modules (CEQM) 6.7 5.2 5.8 3.7 Input Buffers (CEQI) 7.2 11.6 12.9 22.1 Output Buffers (CEQO) 10.4 23.8 23.8 31.2 Routed Array Clock Buffer Loads (CEQCR) 1.6 3.5 3.9 4.6 Dedicated Clock Buffer Loads (CEQCD) 0 . 7 N / A N / A N / A I/O Clock Buffer Loads (CEQCI) 0 . 9 N / A N / A N / A m = Number of logic modules switching at f m n = Number of input buffers switching at f n p = Number of output buffers switching at f p q1 = Number of clock loads on the first routed array clock (all families) q2 = Number of clock loads on the second routed array clock (ACT 2, 1200XL, 3200DX, ACT 3 only) r 1 = Fixed capacitance due to first routed array clock (all families) r2 = Fixed capacitance due to second routed array clock (ACT 2, 1200XL, 3200DX, ACT 3 only) s1 = Fixed number of clock loads on the dedicated array clock (ACT 3 only) s2 = Fixed number of clock loads on the dedicated I/O clock (ACT 3 only) CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CEQCD = Equivalent capacitance of dedicated array clock in pF CEQCI = Equivalent capacitance of dedicated I/O clock in pF CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz (all families) fq2 = Average second routed array clock rate in MHz (ACT 2, 1200XL, 3200DX, ACT 3 only) fs1 = Average dedicated array clock rate in MHz (ACT 3 only) fs2 = Average dedicated I/O clock rate in MHz (ACT 3 only)

Fixed Capacitance Values for Actel FPGAs (pF) Fixed Clock Loads (s 1/s 2—ACT 3 Only) Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data values input to the circuit. The guidelines in the table below are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. Device Type r routed_Clk1 routed_Clk2 A1010B 41 n/a A1020B 69 n/a A1240A 134 134 A1280A 168 168 A1280XL 168 168 A1425A 75 75 A1460A 165 165 A14100A 195 195 A32100DX 178 178 A32200DX 230 230 Device Type s Clock Loads on Dedicated Array Clock Clock Loads on Dedicated I/O Clock A1425A 160 100 A1460A 432 168 A14100A 697 228 Type ACT 3 3200DX/ACT 2/1200XL ACT 1 Logic modules (m) 80% of modules 80% of modules 90% of modules Input switching (n) # inputs/4 # inputs/4 # inputs/4 Outputs switching (p) #outputs/4 #outputs/4 #outputs/4 First routed array clock loads (q 1) 40% of sequential modules 40% of sequential modules 40% of modules Second routed array clock loads (q2) 40% of sequential modules 40% of sequential modules n/a Load capacitance (CL) 35 pF 35 pF 35 pF Average logic module switching rate (fm ) F/10 F/10 F/10 Average input switching rate (fn) F/5 F/5 F/5 Average output switching rate (fp) F/10 F/10 F/10 Average first routed array clock rate (fq1)F / 2 F F Average second routed array clock rate (fq2) F/2 F/2 n/a Average dedicated array clock rate (fs1)F n / a n / a Average dedicated I/O clock rate (fs2)F n / a n / a

3200DX Timing Model (Logic Functions using Array Clocks)* *Values shown for A32100DX–1 at worst-case military conditions. Output DelaysInternal DelaysInput Delays tINH = 0.0 ns tINSU = 0.7 ns I/O Module D Q tINGO = 4.0 ns tINPY = 1.9 nstIRD1 = 2.2 ns Combinatorial Module tPD = 3.1 ns Sequential Logic Module I/O Module tRD1 = 1.3 ns tDLH = 6.3 ns I/O Module ARRAY CLOCKS FMAX = 140 MHz Combin- atorial Logic included in tSUD D Q D Q tLH = 0.0 ns tLSU = 0.4 ns tGHL = 12.4 ns tDLH = 6.3 ns tENHZ = 11.5 ns tRD1 = 1.3 ns tCO = 3.1 nstSU = 0.5 ns tHD = 0.0 ns Predicted Routing Delays G G Decode Module tPDD = 3.3 ns tRDD = 0.5 ns tRD2 = 1.9 ns tRD4 = 3.3 ns tCKH = 6.5 ns

3200DX Timing Model (Logic Functions using Quadrant Clocks)* * Values shown for A32100DX–1 at worst-case military conditions. Load dependent. Output DelaysInternal DelaysInput Delays tINH = 0.0 ns tINSU = 0.7 ns I/O Module D Q tINGO = 4.0 ns tINPY = 1.9 nstIRD1 = 2.2 ns Combinatorial Module tPD = 3.1 ns Sequential Logic Module I/O Module tRD1 = 1.3 ns tDLH = 6.3 ns I/O Module QUADRANT CLOCKS FMAX = 100 MHz Combin- atorial Logic included in tSUD D Q D Q tLH = 0.0 ns tLSU = 0.4 ns tGHL = 12.4 ns tDLH = 6.3 ns tENHZ = 11.5 ns tRD1 = 1.3 ns tCO = 3.1 nstSU = 0.5 ns tHD = 0.0 ns Predicted Routing Delays G G Decode Module tPDD = 3.3 ns tRDD = 0.5 ns tRD2 = 1.9 ns tRD4 = 3.3 ns tCKH = 12 ns

3200DX Timing Model (SRAM Functions)* *Values shown for A32100DX–1 at worst-case military conditions. tINH = 0.0 ns tINSU = 0.7 ns Input Delays I/O Module D Q tINGO = 4.0 ns tINPY = 1.9 nstIRD1 = 2.2 ns ARRAY CLOCKS FMAX = 140 MHz G tGHL = 12.4 ns tLSU = 0.4 ns I/O Module D Q tLH = 0.0 ns tDLH = 6.3 ns G WD [7:0] WRAD [5:0] BLKEN WEN WCLK tADSU = 2.1 ns tADH = 0.0 ns tWENSU = 3.5 ns tBENS = 3.6 ns RD [7:0] RDAD [5:0] REN RCLK tADSU = 2.1 ns tADH = 0.0 ns tRENSU = 0.8 ns tRD1 = 1.3 ns Predicted Routing Delays tRCO = 4.4 ns

1200XL Timing Model* *Values shown for A1280XL–1 at worst-case military conditions. † Input module predicted routing delay. Output DelaysInternal DelaysInput Delays tINH = 0.0 ns tINSU = 0.4 ns I/O Module D Q tINGL = 3.7 ns tINYL = 1.7 nstIRD2 = 5.2 ns† Combinatorial Logic Module tPD = 3.7 ns Sequential Logic Module I/O Module tRD1 = 1.7 ns tDLH = 6.6 ns I/O Module ARRAY CLOCKS FMAX = 110 MHz Combin- atorial Logic included in tSUD D Q D Q tOUTH = 0.0 ns tOUTSU = 0.4 ns tGLH = 5.9 ns tDLH = 6.6 ns tENHZ = 7.5 nstRD1 = 1.7 ns tCO = 3.7 nstSU = 0.4 ns tHD = 0.0 ns tRD4 = 3.7 ns tRD8 = 7.0 ns Predicted Routing Delays tCKH = 7.1 ns G G FO = 256 tRD2 = 2.5 ns tLCO = 10.7 ns (64 loads, pad-pad)

Input Buffer Delays Combinatorial Macro Delays PAD To AC test loads (shown below)D E TRIBUFF In VCC GND50% PAD VOL VOH 1.5V tDLH 50% 1.5V tDHL E VCC GND50% PAD VOL 1.5V tENZL 50% 10% tENLZ E VCC GND50% PA D GND VOH 1.5V tENZH 50% 90% tENHZ VCC PAD Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) 50 pF T o the output under test VCC GND 50 pF T o the output under test R to VCC for tPLZ /tPZL R to GND for tPHZ /tPZH R = 1 kΩ PAD YINBUF PAD 0V1.5V Y GND VCC 50% tINYH 1.5V 50% tINYL PAD S A B Y S, A, or B Y GND VCC 50% tPLH Y GND GND VCC 50% 50% 50% VCC 50% 50% tPHL tPHLtPLH

Sequential Timing Characteristics Flip-Flops and Latches (ACT 3) Note: 1. D represents all data functions involving A, B, and S for multiplexed flip-flops. (Positive edge triggered) D E CLK CLR Y D 1 G, CLK E Q CLR tWCLKA tWASYN tHD tSUENA tSUD tCLR tA tCO tHENA

Sequential Timing Characteristics (continued) Flip-Flops and Latches (1200XL/3200DX, ACT 2, and ACT 1) Note: 1. D represents all data functions involving A, B, and S for multiplexed flip-flops. (Positive edge triggered) D E CLK CLR PRE Y D 1 G, CLK E Q PRE, CLR tWCLKA tWASYN tHD tSUENA tSUD tRS tA tCO tHENA

Sequential Timing Characteristics (continued) Input Buffer Latches (ACT 2 and 1200XL/3200DX) Output Buffer Latches (ACT 2 and 1200XL/3200DX) G PAD PADCLK PAD G CLK tINH CLKBUF tINSU tSUEXT tHEXT IBDL D G tOUTSU tOUTH PAD OBDLHS D G

SRAM Timing Characteristics A–G, H Y tPLH 50% VCC VCC tPHL Y A B C D E F G H WRAD [5:0] BLKEN WEN WCLK RDAD [5:0] LEW REN RCLK RD [7:0]WD [7:0] Write Port Read Port RAM Array 32x8 or 64x4 (256 bits)

Dual-Port SRAM Timing Waveforms 3200DX SRAM Write Operation Note: Identical timing for falling-edge clock. 3200DX SRAM Synchronous Read Operation Note: Identical timing for falling-edge clock. WCLK WD[7:0] WRAD[5:0] WEN BLKEN Valid Valid tRCKHLtRCKHL tWENSU tBENSU tWENH tBENH tADSU tADH RCLK REN RDAD[5:0] RD[7:0] Old Data Valid tRCKHLtCKHL tRENH tRCO tADH tDOH tADSU New Data tRENSU

3200DX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled) 3200DX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled) RDAD[5:0] RD[7:0] Data 1 tRDADV tDOH ADDR2ADDR1 Data 2 tRPD WEN WD[7:0] WCLK RD[7:0] Old Data Valid tWENH tRPD tWENSU New Data tDOH tADSU WRAD[5:0] BLKEN tADH

ACT 1 Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Propagation Delays tPD1 Single Module 4.7 5.5 ns tPD2 Dual Module Macros 10.8 12.7 ns tCO Sequential Clk to Q 4.7 5.5 ns tGO Latch G to Q 4.7 5.5 ns tRS Flip-Flop (Latch) Reset to Q 4.7 5.5 ns Logic Module Predicted Routing Delays1 tRD1 FO=1 Routing Delay 1.5 1.7 ns tRD2 FO=2 Routing Delay 2.3 2.7 ns tRD3 FO=3 Routing Delay 3.4 4.0 ns tRD4 FO=4 Routing Delay 5.0 5.9 ns tRD8 FO=8 Routing Delay 10.6 12.5 ns Logic Module Sequential Timing 2 tSUD Flip-Flop (Latch) Data Input Setup 8.8 10.4 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 8.8 10.4 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 10.9 12.9 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 10.9 12.9 ns tA Flip-Flop Clock Input Period 23.2 27.3 ns fMAX Flip-Flop (Latch) Clock Frequency 44 37 MHz Input Module Propagation Delays t INYH Pad to Y High 4.9 5.8 ns tINYL Pad to Y Low 4.9 5.8 ns Input Module Predicted Routing Delays1, 3 tIRD1 FO=1 Routing Delay 1.5 1.7 ns tIRD2 FO=2 Routing Delay 2.3 2.7 ns tIRD3 FO=3 Routing Delay 3.4 4.0 ns tIRD4 FO=4 Routing Delay 5.0 5.9 ns tIRD8 FO=8 Routing Delay 10.6 12.5 ns Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. Setup times assume fanout of 3. Further derating information can be obtained from the DirectTime Analyzer utility. 3. Optimization techniques may further reduce delays by 0 to 4 ns.

ACT 1 Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Global Clock Network tCKH Input Low to High FO = 16 FO = 128 7.8 8.9 9.2 10.5 ns tCKL Input High to Low FO = 16 FO = 128 10.3 11.2 12.1 13.2 ns tPWH Minimum Pulse Width High FO = 16 FO = 128 10.4 10.9 12.2 12.9 ns tPWL Minimum Pulse Width Low FO = 16 FO = 128 10.4 10.9 12.2 12.9 ns tCKSW Maximum Skew FO = 16 FO = 128 1.9 2.9 2.2 3.4 ns tP Minimum Period FO = 16 FO = 128 21.7 23.2 25.6 27.3 ns fMAX Maximum Frequency FO = 16 FO = 128

37 MHz

tDLH Data to Pad High 12.1 14.2 ns tDHL Data to Pad Low 13.8 16.3 ns tENZH Enable Pad Z to High 12.0 14.1 ns tENZL Enable Pad Z to Low 14.6 17.1 ns tENHZ Enable Pad High to Z 16.0 18.8 ns tENLZ Enable Pad Low to Z 14.5 17.0 ns dTLH Delta Low to High 0.09 0.11 ns/pF dTHL Delta High to Low 0.12 0.15 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 15.1 17.7 ns tDHL Data to Pad Low 11.5 13.6 ns tENZH Enable Pad Z to High 12.0 14.1 ns tENZL Enable Pad Z to Low 14.6 17.1 ns tENHZ Enable Pad High to Z 16.0 18.8 ns tENLZ Enable Pad Low to Z 14.5 17.0 ns dTLH Delta Low to High 0.16 0.18 ns/pF dTHL Delta High to Low 0.09 0.11 ns/pF Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

A1240A Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Propagation Delays1 tPD1 Single Module 5.2 6.1 ns tCO Sequential Clk to Q 5.2 6.1 ns tGO Latch G to Q 5.2 6.1 ns tRS Flip-Flop (Latch) Reset to Q 5.2 6.1 ns Logic Module Predicted Routing Delays2 tRD1 FO=1 Routing Delay 1.9 2.2 ns tRD2 FO=2 Routing Delay 2.4 2.8 ns tRD3 FO=3 Routing Delay 3.1 3.7 ns tRD4 FO=4 Routing Delay 4.3 5.0 ns tRD8 FO=8 Routing Delay 6.6 7.7 ns Logic Module Sequential Timing3, 4 tSUD Flip-Flop (Latch) Data Input Setup 0.5 0.5 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 1.3 1.3 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 7.4 8.1 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 7.4 8.1 ns tA Flip-Flop Clock Input Period 14.8 18.6 ns tINH Input Buffer Latch Hold 2.5 2.5 ns tINSU Input Buffer Latch Setup –3.5 –3.5 ns tOUTH Output Buffer Latch Hold 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.5 0.5 ns fMAX Flip-Flop (Latch) Clock Frequency 63 54 MHz Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External set up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

A1240A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Input Module Propagation Delays tINYH Pad to Y High 4.0 4.7 ns tINYL Pad to Y Low 3.6 4.3 ns tINGH G to Y High 6.9 8.1 ns tINGL G to Y Low 6.6 7.7 ns Input Module Predicted Routing Delays1 tIRD1 FO=1 Routing Delay 5.8 6.9 ns tIRD2 FO=2 Routing Delay 6.7 7.8 ns tIRD3 FO=3 Routing Delay 7.5 8.8 ns tIRD4 FO=4 Routing Delay 8.2 9.7 ns tIRD8 FO=8 Routing Delay 10.9 12.9 ns Global Clock Network t CKH Input Low to High FO = 32 FO = 256 13.3 16.3 15.7 19.2 ns tCKL Input High to Low FO = 32 FO = 256 13.3 16.5 15.7 19.5 ns tPWH Minimum Pulse Width High FO = 32 FO = 256 5.7 6.0 6.7 7.1 ns tPWL Minimum Pulse Width Low FO = 32 FO = 256 5.7 6.0 6.7 7.1 ns tCKSW Maximum Skew FO = 32 FO = 256 0.6 3.1 0.6 3.1 ns tSUEXT Input Latch External Setup FO = 32 FO = 256 0.0 0.0 0.0 0.0 ns tHEXT Input Latch External Hold FO = 32 FO = 256 8.6 13.8 8.6 13.8 ns tP Minimum Period FO = 32 FO = 256 11.5 12.2 13.5 14.3 ns fMAX Maximum Frequency FO = 32 FO = 256

70 MHz

Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.

A1240A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 11.0 13.0 ns tDHL Data to Pad Low 13.9 16.4 ns tENZH Enable Pad Z to High 12.3 14.4 ns tENZL Enable Pad Z to Low 16.1 19.0 ns tENHZ Enable Pad High to Z 9.8 11.5 ns tENLZ Enable Pad Low to Z 11.5 13.6 ns tGLH G to Pad High 12.4 14.6 ns tGHL G to Pad Low 15.5 18.2 ns dTLH Delta Low to High 0.09 0.11 ns/pF dTHL Delta High to Low 0.17 0.20 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 14.0 16.5 ns tDHL Data to Pad Low 11.7 13.7 ns tENZH Enable Pad Z to High 12.3 14.4 ns tENZL Enable Pad Z to Low 16.1 19.0 ns tENHZ Enable Pad High to Z 9.8 11.5 ns tENLZ Enable Pad Low to Z 11.5 13.6 ns tGLH G to Pad High 12.4 14.6 ns tGHL G to Pad Low 15.5 18.2 ns dTLH Delta Low to High 0.17 0.20 ns/pF dTHL Delta High to Low 0.12 0.15 ns/pF Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

A1280A Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Propagation Delays1 tPD1 Single Module 5.2 6.1 ns tCO Sequential Clk to Q 5.2 6.1 ns tGO Latch G to Q 5.2 6.1 ns tRS Flip-Flop (Latch) Reset to Q 5.2 6.1 ns Logic Module Predicted Routing Delays2 tRD1 FO=1 Routing Delay 2.4 2.8 ns tRD2 FO=2 Routing Delay 3.4 4.0 ns tRD3 FO=3 Routing Delay 4.2 4.9 ns tRD4 FO=4 Routing Delay 5.1 6.0 ns tRD8 FO=8 Routing Delay 9.2 10.8 ns Logic Module Sequential Timing3, 4 tSUD Flip-Flop (Latch) Data Input Setup 0.5 0.5 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 1.3 1.3 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 7.4 8.6 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 7.4 8.6 ns tA Flip-Flop Clock Input Period 16.4 22.1 ns tINH Input Buffer Latch Hold 2.5 2.5 ns tINSU Input Buffer Latch Setup –3.5 –3.5 ns tOUTH Output Buffer Latch Hold 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.5 0.5 ns fMAX Flip-Flop (Latch) Clock Frequency 60 41 MHz Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtai ned from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

A1280A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Input Module Propagation Delays tINYH Pad to Y High 4.0 4.7 ns tINYL Pad to Y Low 3.6 4.3 ns tINGH G to Y High 6.9 8.1 ns tINGL G to Y Low 6.6 7.7 ns Input Module Predicted Routing Delays1 tRD1 FO=1 Routing Delay 6.2 7.3 ns tRD2 FO=2 Routing Delay 7.2 8.4 ns tRD3 FO=3 Routing Delay 7.7 9.1 ns tRD4 FO=4 Routing Delay 8.9 10.5 ns tRD8 FO=8 Routing Delay 12.9 15.2 ns Global Clock Network t CKH Input Low to High FO = 32 FO = 384 13.3 17.9 15.7 21.1 ns tCKL Input High to Low FO = 32 FO = 384 13.3 18.2 15.7 21.4 ns tPWH Minimum Pulse Width High FO = 32 FO = 384 6.9 7.9 8.1 9.3 ns tPWL Minimum Pulse Width Low FO = 32 FO = 384 6.9 7.9 8.1 9.3 ns tCKSW Maximum Skew FO = 32 FO = 384 0.6 3.1 0.6 3.1 ns tSUEXT Input Latch External Setup FO = 32 FO = 384 0.0 0.0 0.0 0.0 ns tHEXT Input Latch External Hold FO = 32 FO = 384 8.6 13.8 8.6 13.8 ns tP Minimum Period FO = 32 FO = 384 13.7 16.0 16.2 18.9 ns fMAX Maximum Frequency FO = 32 FO = 384

53 MHz

A1280A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 11.0 13.0 ns tDHL Data to Pad Low 13.9 16.4 ns tENZH Enable Pad Z to High 12.3 14.4 ns tENZL Enable Pad Z to Low 16.1 19.0 ns tENHZ Enable Pad High to Z 9.8 11.5 ns tENLZ Enable Pad Low to Z 11.5 13.6 ns tGLH G to Pad High 12.4 14.6 ns tGHL G to Pad Low 15.5 18.2 ns dTLH Delta Low to High 0.09 0.11 ns/pF dTHL Delta High to Low 0.17 0.20 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 14.0 16.5 ns tDHL Data to Pad Low 11.7 13.7 ns tENZH Enable Pad Z to High 12.3 14.4 ns tENZL Enable Pad Z to Low 16.1 19.0 ns tENHZ Enable Pad High to Z 9.8 11.5 ns tENLZ Enable Pad Low to Z 11.5 13.6 ns tGLH G to Pad High 12.4 14.6 ns tGHL G to Pad Low 15.5 18.2 ns dTLH Delta Low to High 0.17 0.20 ns/pF dTHL Delta High to Low 0.12 0.15 ns/pF Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

A1280XL Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Propagation Delays1 tPD1 Single Module 3.7 4.3 ns tCO Sequential Clk to Q 3.7 4.3 ns tGO Latch G to Q 3.7 4.3 ns tRS Flip-Flop (Latch) Reset to Q 3.7 4.3 ns Logic Module Predicted Routing Delays2 tRD1 FO=1 Routing Delay 1.7 2.1 ns tRD2 FO=2 Routing Delay 2.5 3.0 ns tRD3 FO=3 Routing Delay 3.1 3.6 ns tRD4 FO=4 Routing Delay 3.7 4.3 ns tRD8 FO=8 Routing Delay 7.0 8.3 ns Logic Module Sequential Timing3, 4 tSUD Flip-Flop (Latch) Data Input Setup 0.4 0.5 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 1.1 1.2 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 5.3 6.1 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 5.3 6.1 ns tA Flip-Flop Clock Input Period 10.7 12.3 ns tINH Input Buffer Latch Hold 0.0 0.0 ns tINSU Input Buffer Latch Setup 0.4 0.4 ns tOUTH Output Buffer Latch Hold 0.0 0.0 ns tOUTSU Output Buffer Latch Setup 0.4 0.4 ns fMAX Flip-Flop (Latch) Clock Frequency 90 75 MHz Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtai ned from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set up/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

A1280XL Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Input Module Propagation Delays tINYH Pad to Y High 1.5 1.7 ns tINYL Pad to Y Low 1.7 2.1 ns tINGH G to Y High 2.8 3.3 ns tINGL G to Y Low 3.7 4.3 ns Input Module Predicted Routing Delays1 tRD1 FO=1 Routing Delay 4.6 5.3 ns tRD2 FO=2 Routing Delay 5.2 6.1 ns tRD3 FO=3 Routing Delay 5.5 6.5 ns tRD4 FO=4 Routing Delay 6.4 7.5 ns tRD8 FO=8 Routing Delay 9.2 10.8 ns Global Clock Network t CKH Input Low to High FO = 32 FO = 384 7.1 8.0 8.4 9.5 ns tCKL Input High to Low FO = 32 FO = 384 7.0 8.0 8.3 9.5 ns tPWH Minimum Pulse Width High FO = 32 FO = 384 4.3 4.8 5.3 5.7 ns tPWL Minimum Pulse Width Low FO = 32 FO = 384 4.3 4.8 5.3 5.7 ns tCKSW Maximum Skew FO = 32 FO = 384 1.1 1.1 1.2 1.2 ns tSUEXT Input Latch External Setup FO = 32 FO = 384 0.0 0.0 0.0 0.0 ns tHEXT Input Latch External Hold FO = 32 FO = 384 3.6 4.6 4.2 5.3 ns tP Minimum Period FO = 32 FO = 384 9.1 9.8 10.7 11.8 ns fMAX Maximum Frequency FO = 32 FO = 384 110 100

85 MHz

A1280XL Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 5.3 6.2 ns tDHL Data to Pad Low 5.7 6.6 ns tENZH Enable Pad Z to High 5.3 6.2 ns tENZL Enable Pad Z to Low 5.8 6.8 ns tENHZ Enable Pad High to Z 7.5 8.9 ns tENLZ Enable Pad Low to Z 7.5 8.9 ns tGLH G to Pad High 5.9 6.9 ns tGHL G to Pad Low 6.6 7.8 ns dTLH Delta Low to High 0.05 0.06 ns/pF dTHL Delta High to Low 0.05 0.09 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 6.6 7.9 ns tDHL Data to Pad Low 4.7 5.5 ns tENZH Enable Pad Z to High 5.3 6.2 ns tENZL Enable Pad Z to Low 5.8 6.8 ns tENHZ Enable Pad High to Z 7.5 8.9 ns tENLZ Enable Pad Low to Z 7.5 8.9 ns tGLH G to Pad High 5.9 6.9 ns tGHL G to Pad Low 6.6 7.8 ns dTLH Delta Low to High 0.07 0.09 ns/pF dTHL Delta High to Low 0.06 0.09 ns/pF Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

A1425A Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Propagation Delays1 tPD Internal Array Module 3.0 3.5 ns tCO Sequential Clock to Q 3.0 3.5 ns tCLR Asynchronous Clear to Q 3.0 3.5 ns Logic Module Predicted Routing Delays2 tRD1 FO=1 Routing Delay 1.3 1.5 ns tRD2 FO=2 Routing Delay 1.9 2.1 ns tRD3 FO=3 Routing Delay 2.1 2.5 ns tRD4 FO=4 Routing Delay 2.6 2.9 ns tRD8 FO=8 Routing Delay 4.2 4.9 ns Logic Module Sequential Timing t SUD Flip-Flop (Latch) Data Input Setup 0.9 1.0 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 0.9 1.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 3.8 4.4 ns tWCLKA Flip-Flop Clock Pulse Width 3.8 4.4 ns tA Flip-Flop Clock Input Period 7.9 9.3 ns fMAX Flip-Flop Clock Frequency 125 100 MHz Input Module Propagation Delays tINY Input Data Pad to Y 4.2 4.9 ns tICKY Input Reg IOCLK Pad to Y 7.0 8.2 ns tOCKY Output Reg IOCLK Pad to Y 7.0 8.2 ns tICLRY Input Asynchronous Clear to Y 7.0 8.2 ns tOCLRY Output Asynchronous Clear to Y 7.0 8.2 ns Input Module Predicted Routing Delays1, 3 tIRD1 FO=1 Routing Delay 1.3 1.5 ns tIRD2 FO=2 Routing Delay 1.9 2.1 ns tIRD3 FO=3 Routing Delay 2.1 2.5 ns tIRD4 FO=4 Routing Delay 2.6 2.9 ns tIRD8 FO=8 Routing Delay 4.2 4.9 ns Notes: 1. For dual-module macros, use t PD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Optimization techniques may further reduce delays by 0 to 4 ns.

A1425A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units I/O Module Sequential Timing tINH Input F-F Data Hold tINSU Input F-F Data Setup tIDEH Input Data Enable Hold tIDESU Input Data Enable Setup tOUTH Output F-F Data Hold tOUTSU Output F-F Data Setup tODEH Output Data Enable Hold tODESU Output Data Enable Setup TTL Output Module Timing1 tDHS Data to Pad, High Slew 7.5 8.9 ns tDLS Data to Pad, Low Slew 11.9 14.0 ns tENZHS Enable to Pad, Z to H/L, High Slew 6.0 7.0 ns tENZLS Enable to Pad, Z to H/L, Low Slew 10.9 12.8 ns tENHSZ Enable to Pad, H/L to Z, High Slew 9.9 11.6 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 9.9 11.6 ns tCKHS IOCLK Pad to Pad H/L, High Slew 10.5 11.6 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 15.7 17.4 ns dTLHHS Delta Low to High, High Slew 0.04 0.04 ns/pF dTLHLS Delta Low to High, Low Slew 0.07 0.08 ns/pF dTHLHS Delta High to Low, High Slew 0.05 0.06 ns/pF dTHLLS Delta High to Low, Low Slew 0.07 0.08 ns/pF Note: 1. Delays based on 35 pF loading.

A1425A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units CMOS Output Module Timing1 tDHS Data to Pad, High Slew 9.2 10.8 ns tDLS Data to Pad, Low Slew 17.3 20.3 ns tENZHS Enable to Pad, Z to H/L, High Slew 7.7 9.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 13.1 15.5 ns tENHSZ Enable to Pad, H/L to Z, High Slew 9.9 11.6 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 10.5 11.6 ns tCKHS IOCLK Pad to Pad H/L, High Slew 12.5 13.7 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 18.1 20.1 ns dTLHHS Delta Low to High, High Slew 0.06 0.07 ns/pF dTLHLS Delta Low to High, Low Slew 0.11 0.13 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.06 ns/pF Dedicated (Hard-Wired) I/O Clock Network t IOCKH Input Low to High (Pad to I/O Module Input) 3.0 3.5 ns tIOPWH Minimum Pulse Width High 3.9 4.4 ns tIOPWL Minimum Pulse Width Low 3.9 4.4 ns tIOSAPW Minimum Asynchronous Pulse Width 3.9 4.4 ns tIOCKSW Maximum Skew 0.5 0.5 ns tIOP Minimum Period 7.9 9.3 ns fIOMAX Maximum Frequency 125 100 MHz Dedicated (Hard-Wired) Array Clock Network tHCKH Input Low to High (Pad to S-Module Input) 4.6 5.3 ns tHCKL Input High to Low (Pad to S-Module Input) 4.6 5.3 ns tHPWH Minimum Pulse Width High 3.9 4.4 ns tHPWL Minimum Pulse Width Low 3.9 4.4 ns tHCKSW Maximum Skew 0.4 0.4 ns tHP Minimum Period 7.9 9.3 ns fHMAX Maximum Frequency 125 100 MHz Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

A1425A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Routed Array Clock Networks tRCKH Input Low to High (FO=64) 5.5 6.4 ns tRCKL Input High to Low (FO=64) 6.0 7.0 ns tRPWH Min. Pulse Width High (FO=64) 4.9 5.7 ns tRPWL Min. Pulse Width Low (FO=64) 4.9 5.7 ns tRCKSW Maximum Skew (FO=128) 1.1 1.2 ns tRP Minimum Period (FO=64) 10.1 11.6 ns fRMAX Maximum Frequency (FO=64) 100 85 MHz Clock-to-Clock Skews t IOHCKSW I/O Clock to H-Clock Skew 0.0 3.0 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew 0.0 3.0 0.0 3.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns

A1460A Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Propagation Delays1 tPD Internal Array Module 3.0 3.5 ns tCO Sequential Clock to Q 3.0 3.5 ns tCLR Asynchronous Clear to Q 3.0 3.5 ns Logic Module Predicted Routing Delays2 tRD1 FO=1 Routing Delay 1.3 1.5 ns tRD2 FO=2 Routing Delay 1.9 2.1 ns tRD3 FO=3 Routing Delay 2.1 2.5 ns tRD4 FO=4 Routing Delay 2.6 2.9 ns tRD8 FO=8 Routing Delay 4.2 4.9 ns Logic Module Sequential Timing tSUD Flip-Flop (Latch) Data Input Setup 0.9 1.0 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 0.0 ns tSUENA Flip-Flop (Latch) Enable Setup 0.9 1.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 4.8 5.6 ns tWCLKA Flip-Flop Clock Pulse Width 4.8 5.6 ns tA Flip-Flop Clock Input Period 9.9 11.6 ns fMAX Flip-Flop Clock Frequency 100 85 MHz Input Module Propagation Delays tINY Input Data Pad to Y 4.2 4.9 ns tICKY Input Reg IOCLK Pad to Y 7.0 8.2 ns tOCKY Output Reg IOCLK Pad to Y 7.0 8.2 ns tICLRY Input Asynchronous Clear to Y 7.0 8.2 ns tOCLRY Output Asynchronous Clear to Y 7.0 8.2 ns Input Module Predicted Routing Delays2, 3 tIRD1 FO=1 Routing Delay 1.3 1.5 ns tIRD2 FO=2 Routing Delay 1.9 2.1 ns tIRD3 FO=3 Routing Delay 2.1 2.5 ns tIRD4 FO=4 Routing Delay 2.6 2.9 ns tIRD8 FO=8 Routing Delay 4.2 4.9 ns Notes: 1. For dual-module macros, use t PD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Optimization techniques may further reduce delays by 0 to 4 ns.

A1460A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units I/O Module Sequential Timing tINH Input F-F Data Hold tINSU Input F-F Data Setup tIDEH Input Data Enable Hold tIDESU Input Data Enable Setup tOUTH Output F-F Data Hold tOUTSU Output F-F Data Setup tODEH Output Data Enable Hold tODESU Output Data Enable Setup TTL Output Module Timing1 tDHS Data to Pad, High Slew 7.5 8.9 ns tDLS Data to Pad, Low Slew 11.9 14.0 ns tENZHS Enable to Pad, Z to H/L, High Slew 6.0 7.0 ns tENZLS Enable to Pad, Z to H/L, Low Slew 10.9 12.8 ns tENHSZ Enable to Pad, H/L to Z, High Slew 11.5 13.5 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 10.9 12.8 ns tCKHS IOCLK Pad to Pad H/L, High Slew 11.6 13.4 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 17.8 19.8 ns dTLHHS Delta Low to High, High Slew 0.04 0.04 ns/pF dTLHLS Delta Low to High, Low Slew 0.07 0.08 ns/pF dTHLHS Delta High to Low, High Slew 0.05 0.06 ns/pF dTHLLS Delta High to Low, Low Slew 0.07 0.08 ns/pF Note: 1. Delays based on 35 pF loading.

A1460A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units CMOS Output Module Timing1 tDHS Data to Pad, High Slew 9.2 10.8 ns tDLS Data to Pad, Low Slew 17.3 20.3 ns tENZHS Enable to Pad, Z to H/L, High Slew 7.7 9.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 13.1 15.5 ns tENHSZ Enable to Pad, H/L to Z, High Slew 10.9 12.8 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 10.9 12.8 ns tCKHS IOCLK Pad to Pad H/L, High Slew 14.1 16.0 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 20.2 22.4 ns dTLHHS Delta Low to High, High Slew 0.06 0.07 ns/pF dTLHLS Delta Low to High, Low Slew 0.11 0.13 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.06 ns/pF Dedicated (Hard-Wired) I/O Clock Network t IOCKH Input Low to High (Pad to I/O Module Input) 3.5 4.1 ns tIOPWH Minimum Pulse Width High 4.8 5.7 ns tIOPWL Minimum Pulse Width Low 4.8 5.7 ns tIOSAPW Minimum Asynchronous Pulse Width 3.9 4.4 ns tIOCKSW Maximum Skew 0.9 1.0 ns tIOP Minimum Period 9.9 11.6 ns fIOMAX Maximum Frequency 100 85 MHz Dedicated (Hard-Wired) Array Clock Network t HCKH Input Low to High (Pad to S-Module Input) 5.5 6.4 ns tHCKL Input High to Low (Pad to S-Module Input) 5.5 6.4 ns tHPWH Minimum Pulse Width High 4.8 5.7 ns tHPWL Minimum Pulse Width Low 4.8 5.7 ns tHCKSW Maximum Skew 0.9 1.0 ns tHP Minimum Period 9.9 11.6 ns fHMAX Maximum Frequency 100 85 MHz Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

A1460A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Routed Array Clock Networks tRCKH Input Low to High (FO=256) 9.0 10.5 ns tRCKL Input High to Low (FO=256) 9.0 10.5 ns tRPWH Min. Pulse Width High (FO=256) 6.3 7.1 ns tRPWL Min. Pulse Width Low (FO=256) 6.3 7.1 ns tRCKSW Maximum Skew (FO=128) 1.9 2.1 ns tRP Minimum Period (FO=256) 12.9 14.5 ns fRMAX Maximum Frequency (FO=256) 75 65 MHz Clock-to-Clock Skews t IOHCKSW I/O Clock to H-Clock Skew 0.0 3.0 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew 0.0 5.0 0.0 5.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns

A14100A Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Propagation Delays1 tPD Internal Array Module 3.0 3.5 ns tCO Sequential Clock to Q 3.0 3.5 ns tCLR Asynchronous Clear to Q 3.0 3.5 ns Logic Module Predicted Routing Delays2 tRD1 FO=1 Routing Delay 1.3 1.5 ns tRD2 FO=2 Routing Delay 1.9 2.1 ns tRD3 FO=3 Routing Delay 2.1 2.5 ns tRD4 FO=4 Routing Delay 2.6 2.9 ns tRD8 FO=8 Routing Delay 4.2 4.9 ns Logic Module Sequential Timing tSUD Flip-Flop (Latch) Data Input Setup 1.0 1.0 ns tHD Flip-Flop (Latch) Data Input Hold 0.6 0.6 ns tSUENA Flip-Flop (Latch) Enable Setup 1.0 1.0 ns tHENA Flip-Flop (Latch) Enable Hold 0.6 0.6 ns tWASYN Asynchronous Pulse Width 4.8 5.6 ns tWCLKA Flip-Flop Clock Pulse Width 4.8 5.6 ns tA Flip-Flop Clock Input Period 9.9 11.6 ns fMAX Flip-Flop Clock Frequency 100 85 MHz Input Module Propagation Delays tINY Input Data Pad to Y 4.2 4.9 ns tICKY Input Reg IOCLK Pad to Y 7.0 8.2 ns tOCKY Output Reg IOCLK Pad to Y 7.0 8.2 ns tICLRY Input Asynchronous Clear to Y 7.0 8.2 ns tOCLRY Output Asynchronous Clear to Y 7.0 8.2 ns Input Module Predicted Routing Delays2, 3 tIRD1 FO=1 Routing Delay 1.3 1.5 ns tIRD2 FO=2 Routing Delay 1.9 2.1 ns tIRD3 FO=3 Routing Delay 2.1 2.5 ns tIRD4 FO=4 Routing Delay 2.6 2.9 ns tIRD8 FO=8 Routing Delay 4.2 4.9 ns Notes: 1. For dual-module macros, use t PD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Optimization techniques may further reduce delays by 0 to 4 ns.

A14100A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units I/O Module Sequential Timing tINH Input F-F Data Hold tINSU Input F-F Data Setup tIDEH Input Data Enable Hold tIDESU Input Data Enable Setup tOUTH Output F-F Data Hold tOUTSU Output F-F Data Setup tODEH Output Data Enable Hold tODESU Output Data Enable Setup TTL Output Module Timing1 tDHS Data to Pad, High Slew 7.5 8.9 ns tDLS Data to Pad, Low Slew 11.9 14.0 ns tENZHS Enable to Pad, Z to H/L, High Slew 6.0 7.0 ns tENZLS Enable to Pad, Z to H/L, Low Slew 10.9 12.8 ns tENHSZ Enable to Pad, H/L to Z, High Slew 11.9 14.0 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 10.9 12.8 ns tCKHS IOCLK Pad to Pad H/L, High Slew 12.2 14.0 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 17.8 17.8 ns dTLHHS Delta Low to High, High Slew 0.04 0.04 ns/pF dTLHLS Delta Low to High, Low Slew 0.07 0.08 ns/pF dTHLHS Delta High to Low, High Slew 0.05 0.06 ns/pF dTHLLS Delta High to Low, Low Slew 0.07 0.08 ns/pF Note: 1. Delays based on 35 pF loading.

A14100A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units CMOS Output Module Timing1 tDHS Data to Pad, High Slew 9.2 10.8 ns tDLS Data to Pad, Low Slew 17.3 20.3 ns tENZHS Enable to Pad, Z to H/L, High Slew 7.7 9.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 13.1 15.5 ns tENHSZ Enable to Pad, H/L to Z, High Slew 11.6 14.0 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 10.9 12.8 ns tCKHS IOCLK Pad to Pad H/L, High Slew 14.4 16.0 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 20.2 22.4 ns dTLHHS Delta Low to High, High Slew 0.06 0.07 ns/pF dTLHLS Delta Low to High, Low Slew 0.11 0.13 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.06 ns/pF Dedicated (Hard-Wired) I/O Clock Network tIOCKH Input Low to High (Pad to I/O Module Input) 3.5 4.1 ns tIOPWH Minimum Pulse Width High 4.8 5.7 ns tIOPWL Minimum Pulse Width Low 4.8 5.7 ns tIOSAPW Minimum Asynchronous Pulse Width 3.9 4.4 ns tIOCKSW Maximum Skew 0.9 1.0 ns tIOP Minimum Period 9.9 11.6 ns fIOMAX Maximum Frequency 100 85 MHz Dedicated (Hard-Wired) Array Clock Network t HCKH Input Low to High (Pad to S-Module Input) 5.5 6.4 ns tHCKL Input High to Low (Pad to S-Module Input) 5.5 6.4 ns tHPWH Minimum Pulse Width High 4.8 5.7 ns tHPWL Minimum Pulse Width Low 4.8 5.7 ns tHCKSW Maximum Skew 0.9 1.0 ns tHP Minimum Period 9.9 11.6 ns fHMAX Maximum Frequency 100 85 MHz Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

A14100A Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Routed Array Clock Networks tRCKH Input Low to High (FO=256) 9.0 10.5 ns tRCKL Input High to Low (FO=256) 9.0 10.5 ns tRPWH Min. Pulse Width High (FO=256) 6.3 7.1 ns tRPWL Min. Pulse Width Low (FO=256) 6.3 7.1 ns tRCKSW Maximum Skew (FO=128) 1.9 2.1 ns tRP Minimum Period (FO=256) 12.9 14.5 ns fRMAX Maximum Frequency (FO=256) 75 65 MHz Clock-to-Clock Skews t IOHCKSW I/O Clock to H-Clock Skew 0.0 3.5 0.0 3.5 ns tIORCKSW I/O Clock to R-Clock Skew 0.0 5.0 0.0 5.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns

A32100DX Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Combinatorial Functions tPD Internal Array Module Delay 3.1 4.1 ns tPDD Internal Decode Module Delay 3.3 4.3 ns Logic Module Predicted Routing Delays1 tRD1 FO=1 Routing Delay 1.3 1.8 ns tRD2 FO=2 Routing Delay 1.9 2.6 ns tRD3 FO=3 Routing Delay 2.6 3.4 ns tRD4 FO=4 Routing Delay 3.3 4.3 ns tRD5 FO=8 Routing Delay 0.6 0.8 ns tRDD Decode-to-Output Routing Delay 0.5 0.6 ns Logic Module Sequential Timing tCO Flip-Flop Clock-to-Output 3.1 4.1 ns tGO Latch Gate-to-Output 3.1 4.1 ns tSU Flip-Flop (Latch) Setup Time 0.5 0.6 ns tH Flip-Flop (Latch) Hold Time 0.0 0.0 ns tRO Flip-Flop (Latch) Reset to Output 3.1 4.1 ns tSUENA Flip-Flop (Latch) Enable Setup 0.9 1.2 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 4.3 5.8 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 5.6 7.5 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.

A32100DX Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ’–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Synchronous SRAM Operations tRC Read Cycle Time 8.8 11.8 ns tWC Write Cycle Time 8.8 11.8 ns tRCKHL Clock High/Low Time 4.4 5.9 ns tRCO Data Valid After Clock High/Low 4.4 5.9 ns tADSU Address/Data Setup Time 2.1 2.8 ns tADH Address/Data Hold Time 0.0 0.0 ns tRENSU Read Enable Setup 0.8 1.1 ns tRENH Read Enable Hold 4.4 5.9 ns tWENSU Write Enable Setup 3.5 4.7 ns tWENH Write Enable Hold 0.0 0.0 ns tBENS Block Enable Setup 3.6 4.8 ns tBENH Block Enable Hold 0.0 0.0 ns Asynchronous SRAM Operations tRPD Asynchronous Access Time 10.6 14.1 ns tRDADV Read Address Valid 11.5 15.3 ns tADSU Address/Data Setup Time 2.1 2.8 ns tADH Address/Data Hold Time 0.0 0.0 ns tRENSUA Read Enable Setup to Address Valid 0.8 1.1 ns tRENHA Read Enable Hold 4.4 5.9 ns tWENSU Write Enable Setup 3.5 4.7 ns tWENH Write Enable Hold 0.0 0.0 ns tDOH Data Out Hold Time 1.6 2.1 ns

A32100DX Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Input Module Propagation Delays tINPY Input Data Pad to Y 1.9 2.6 ns tINGO Input Latch Gate-to-Output 4.0 5.3 ns tINH Input Latch Hold 0.0 0.0 ns tINSU Input Latch Setup 0.7 0.9 ns tILA Latch Active Pulse Width 6.1 8.1 ns Input Module Predicted Routing Delays1 tIRD1 FO=1 Routing Delay 2.2 2.9 ns tIRD2 FO=2 Routing Delay 2.8 3.8 ns tIRD3 FO=3 Routing Delay 3.5 4.7 ns tIRD4 FO=4 Routing Delay 3.5 4.7 ns tIRD8 FO=8 Routing Delay 5.6 7.5 ns Global Clock Network tCKH Input Low to High FO=32 FO=635 6.5 7.9 8.7 10.6 ns ns tCKL Input High to Low FO=32 FO=635 6.6 8.8 8.8 11.8 ns ns tPWH Minimum Pulse Width High FO=32 FO=635 4.1 4.6 5.5 6.1 ns ns tPWL Minimum Pulse Width Low FO=32 FO=635 4.1 4.6 5.5 6.1 ns ns tCKSW Maximum Skew FO=32 FO=635 1.8 1.8 2.4 2.4 ns ns tSUEXT Input Latch External Setup FO=32 FO=635 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO=32 FO=635 3.0 3.8 4.0 5.1 ns ns tP Minimum Period (1/fmax) FO=32 FO=635 7.1 7.9 9.5 10.5 ns ns fHMAX Maximum Datapath Frequency FO=32 FO=635 140 126 105 MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.

A32100DX Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 5.1 6.8 ns tDHL Data to Pad Low 6.3 8.3 ns tENZH Enable Pad Z to High 6.6 8.8 ns tENZL Enable Pad Z to Low 7.1 9.4 ns tENHZ Enable Pad High to Z 11.5 15.3 ns tENLZ Enable Pad Low to Z 11.5 15.3 ns tGLH G to Pad High 11.5 15.3 ns tGHL G to Pad Low 12.4 16.6 ns tLSU I/O Latch Output Setup 0.4 0.5 ns tLH I/O Latch Output Hold 0.0 0.0 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 11.5 15.4 ns tACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 16.3 21.7 ns dTLH Capacitive Loading, Low to High 0.04 0.06 ns/pF dTHL Capacitive Loading, High to Low 0.06 0.08 ns/pF tWDO Hard-Wired Wide Decode Output 0.05 0.07 ns CMOS Output Module Timing1 tDLH Data to Pad High 6.3 8.3 ns tDHL Data to Pad Low 5.1 6.8 ns tENZH Enable Pad Z to High 6.6 8.8 ns tENZL Enable Pad Z to Low 7.1 9.4 ns tENHZ Enable Pad High to Z 11.5 15.3 ns tENLZ Enable Pad Low to Z 11.5 15.3 ns tGLH G to Pad High 11.5 15.3 ns tGHL G to Pad Low 12.4 16.6 ns tLSU I/O Latch Setup 0.4 0.5 ns tLH I/O Latch Hold 0.0 0.0 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 13.7 18.2 ns tACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 19.2 25.6 ns dTLH Capacitive Loading, Low to High 0.06 0.08 ns/pF dTHL Capacitive Loading, High to Low 0.05 0.07 ns/pF tWDO Hard-Wired Wide Decode Output 0.05 0.07 ns Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

A32200DX Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Logic Module Combinatorial Functions tPD Internal Array Module Delay 2.8 3.8 ns tPDD Internal Decode Module Delay 3.4 4.6 ns Logic Module Predicted Routing Delays1 tRD1 FO=1 Routing Delay 1.6 2.1 ns tRD2 FO=2 Routing Delay 2.3 3.1 ns tRD3 FO=3 Routing Delay 2.9 3.9 ns tRD4 FO=4 Routing Delay 3.5 4.7 ns tRD5 FO=8 Routing Delay 6.2 8.2 ns tRDD Decode-to-Output Routing Delay 0.8 1.1 ns Logic Module Sequential Timing Characteristics tCO Flip-Flop Clock-to-Output 3.2 4.2 ns tGO Latch Gate-to-Output 2.8 3.8 ns tSU Flip-Flop (Latch) Setup Time 0.5 0.6 ns tH Flip-Flop (Latch) Hold Time 0.0 0.0 ns tRO Flip-Flop (Latch) Reset to Output 3.2 4.2 ns tSUENA Flip-Flop (Latch) Enable Setup 0.9 1.2 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 4.3 5.8 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 5.7 7.6 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.

A32200DX Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Synchronous SRAM Operations tRC Read Cycle Time 8.8 11.8 ns tWC Write Cycle Time 8.8 11.8 ns tRCKHL Clock High/Low Time 4.4 5.9 ns tRCO Data Valid After Clock High/Low 4.4 5.9 ns tADSU Address/Data Setup Time 2.1 2.8 ns tADH Address/Data Hold Time 0.0 0.0 ns tRENSU Read Enable Setup 0.8 1.1 ns tRENH Read Enable Hold 4.4 5.9 ns tWENSU Write Enable Setup 3.5 4.7 ns tWENH Write Enable Hold 0.0 0.0 ns tBENS Block Enable Setup 3.6 4.8 ns tBENH Block Enable Hold 0.0 0.0 ns Asynchronous SRAM Operations tRPD Asynchronous Access Time 10.6 14.1 ns tRDADV Read Address Valid 11.5 15.3 ns tADSU Address/Data Setup Time 2.1 2.8 ns tADH Address/Data Hold Time 0.0 0.0 ns tRENSUA Read Enable Setup to Address Valid 0.8 1.1 ns tRENHA Read Enable Hold 4.4 5.9 ns tWENSU Write Enable Setup 3.5 4.7 ns tWENH Write Enable Hold 0.0 0.0 ns tDOH Data Out Hold Time 1.6 2.1 ns

A32200DX Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units Input Module Propagation Delays tINPY Input Data Pad to Y 1.9 2.6 ns tINGO Input Latch Gate-to-Output 4.6 6.0 ns tINH Input Latch Hold 0.0 0.0 ns tINSU Input Latch Setup 0.7 0.9 ns tILA Latch Active Pulse Width 6.1 8.1 ns Input Module Predicted Routing Delays1 tIRD1 FO=1 Routing Delay 2.6 3.5 ns tIRD2 FO=2 Routing Delay 3.4 4.6 ns tIRD3 FO=3 Routing Delay 4.6 6.1 ns tIRD4 FO=4 Routing Delay 5.4 7.2 ns tIRD5 FO=8 Routing Delay 7.0 9.3 ns Global Clock Network tCKH Input Low to High FO=32 FO=635 7.3 8.5 9.8 11.3 ns ns tCKL Input High to Low FO=32 FO=635 7.2 9.3 9.6 12.5 ns ns tPWH Minimum Pulse Width High FO=32 FO=635 3.2 3.9 4.3 5.2 ns ns tPWL Minimum Pulse Width Low FO=32 FO=635 3.2 3.9 4.3 5.2 ns ns tCKSW Maximum Skew FO=32 FO=635 1.8 1.8 2.4 2.4 ns ns tSUEXT Input Latch External Setup FO=32 FO=635 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO=32 FO=635 3.0 3.8 4.0 5.1 ns ns tP Minimum Period (1/fmax) FO=32 FO=635 5.8 6.8 7.7 9.1 ns ns fHMAX Maximum Datapath Frequency FO=32 FO=635 172 147 130 110 MHz MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.

A32200DX Timing Characteristics (continued) (Worst-Case Military Conditions, V CC = 4.5V, T J = 125°C) ‘–1’ Speed ‘Std’ Speed Parameter Description Min. Max. Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 5.1 6.8 ns tDHL Data to Pad Low 6.3 8.3 ns tENZH Enable Pad Z to High 6.6 8.8 ns tENZL Enable Pad Z to Low 7.1 9.5 ns tENHZ Enable Pad High to Z 11.5 15.3 ns tENLZ Enable Pad Low to Z 11.5 15.3 ns tGLH G to Pad High 11.5 15.3 ns tGHL G to Pad Low 12.3 16.5 ns tLSU I/O Latch Output Setup 0.4 0.5 ns tLH I/O Latch Output Hold 0.0 0.0 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 11.5 15.4 ns tACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 16.3 21.7 ns dTLH Capacitive Loading, Low to High 0.04 0.06 ns/pF dTHL Capacitive Loading, High to Low 0.06 0.08 ns/pF tWDO Hard-Wired Wide Decode Output 0.05 0.07 ns CMOS Output Module Timing1 tDLH Data to Pad High 5.1 6.8 ns tDHL Data to Pad Low 6.3 8.3 ns tENZH Enable Pad Z to High 6.6 8.8 ns tENZL Enable Pad Z to Low 7.1 9.5 ns tENHZ Enable Pad High to Z 11.5 15.3 ns tENLZ Enable Pad Low to Z 11.5 15.3 ns tGLH G to Pad High 11.5 15.3 ns tGHL G to Pad Low 12.3 16.5 ns tLSU I/O Latch Setup 0.4 0.5 ns tLH I/O Latch Hold 0.0 0.0 ns tLCO I/O Latch Clock-Out (Pad-to-Pad) 32 I/O 13.7 18.2 ns tACO Array Latch Clock-Out (Pad-to-Pad) 32 I/O 19.2 25.6 ns dTLH Capacitive Loading, Low to High 0.06 0.08 ns/pF dTHL Capacitive Loading, High to Low 0.05 0.07 ns/pF tWDO Hard-Wired Wide Decode Output 0.05 0.07 ns Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.

CLK Clock (Input) ACT 1 only. TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKA Clock A (Input) ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for global clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKB Clock B (Input) ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for global clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock (Input) ACT 3 only. TTL Clock input for sequential modules. This input is directly wired to each S-module and offers clock speeds independent of the number of S-modules being driven. This pin can also be used as an I/O. I/O Input/Output (Input, Output) I/O pin functions as an input, output, tristate, or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. In the ACT 3 and 3200DX families, unused I/Os are automatically tri-stated. With this configuration, the input buffer internal to the I/O module is disabled. In the ACT 1, ACT 2 and 1200XL families, unused I/Os are automatically configured as bi-directional buffers where each buffer is configured as a LOW driver. IOCLK Dedicated (Hard-wired) I/O Clock (Input) ACT 3 only. TTL Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds independent of the number of I/O modules being driven. This pin can also be used as an I/O. IOPCL Dedicated (Hard-wired) I/O Preset/Clear (Input) ACT 3 only. TTL input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O registers. This pin functions as an I/O when no I/O preset or clear macros are used. MODE Mode (Input) The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide debugging capability, the MODE pin should be terminated to GND through a 10 kΩ resistor so that the MODE pin can be pulled high when required. NC No Connection This pin is not connected to circuitry within the device. PRA, I/O Probe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB, I/O Probe B (Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. VCC 5.0V Supply Voltage HIGH supply voltage. QCLKA/B,C,D Quadrant Clock (Input/Output) 3200DX only. These four pins are the quadrant clock inputs. When not used as a register control signal, these pins can function as general purpose I/O. TCK Test Clock Clock signal to shift the JTAG data into the device. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available in the 3200DX device.

Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available in the 3200DX device. TDO Test Data Out Serial data output for JTAG instructions and test data. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available in the 3200DX device. TMS Test Mode Select Serial data input for JTAG test mode. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available in the 3200DX device.

84-Pin CPGA (Top View) Orientation Pin (C3) A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 84-Pin CPGA A B C D E F G H J K L

A1 I/O I/O F9 CLK, I/O CLK, I/O A2 I/O I/O F10 GND GND A3 I/O I/O F11 I/O I/O A4 I/O I/O G1 I/O I/O A5 I/O I/O G2 V CC VCC A6 I/O I/O G3 I/O I/O A7 I/O I/O G9 I/O I/O A8 I/O I/O G10 GND GND A9 I/O I/O G11 I/O I/O A10 I/O I/O H1 I/O I/O A11 PRA, I/O PRA, I/O H2 I/O I/O B1 NC I/O H10 I/O I/O B2 NC NC H11 I/O I/O B3 I/O I/O J1 I/O I/O B4 I/O I/O J2 NC I/O B5 V CC VCC J5 I/O I/O B6 I/O I/O J6 I/O I/O B7 GND GND J7 I/O I/O B8 I/O I/O J10 NC I/O B9 I/O I/O J11 I/O I/O B10 PRB, I/O PRB, I/O K1 NC I/O B11 SDI, I/O SDI, I/O K2 V CC VCC C1 NC I/O K3 I/O I/O C2 NC I/O K4 I/O I/O C5 I/O I/O K5 GND GND C6 I/O I/O K6 I/O I/O C7 I/O I/O K7 V CC VCC C10 DCLK, I/O DCLK, I/O K8 I/O I/O C11 NC I/O K9 I/O I/O D1 I/O I/O K10 NC I/O D2 I/O I/O K11 NC I/O D10 NC I/O L1 NC I/O D11 NC I/O L2 I/O I/O E1 I/O I/O L3 I/O I/O E2 GND GND L4 I/O I/O E3 GND GND L5 I/O I/O E9 V CC VCC L6 I/O I/O E10 V CC VCC L7 I/O I/O E11 MODE MODE L8 I/O I/O F1 V CC VCC L9 I/O I/O F2 I/O I/O L10 I/O I/O F3 I/O I/O L11 I/O I/O

Package Pin Assignments (continued) 132-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F G H J K L M N A B C D E F G H J K L M N Orientation Pin 132-Pin CPGA

B6 CLKB, I/O G1 I/O M1 I/O B7 CLKA, I/O G2 V CC M2 I/O B8 PRA, I/O G3 V CC M3 I/O B9 GND G4 V CC M4 I/O B10 I/O G10 V CC M5 I/O B11 I/O G11 V CC M6 I/O B12 SDI, I/O G12 V CC M7 I/O B13 I/O G13 V CC M8 I/O C1 I/O H1 I/O M9 GND C2 I/O H2 I/O M10 I/O C3 DCLK, I/O H3 I/O M11 I/O C4 I/O H4 I/O M12 I/O C5 GND H10 I/O M13 I/O C6 PRB, I/O H11 I/O N1 I/O C7 V CC H12 I/O N2 I/O C8 I/O H13 GND N3 I/O C9 GND J1 I/O N4 I/O C10 I/O J2 GND N5 I/O C11 I/O J3 GND N6 I/O C12 I/O J11 GND N7 I/O C13 I/O J12 I/O N8 I/O D1 I/O J13 I/O N9 I/O D2 I/O K1 I/O N10 I/O D3 I/O K2 I/O N11 I/O D6 I/O K3 I/O N12 I/O D7 V CC K6 I/O N13 I/O

Package Pin Assignments (continued) 133-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F G H J K L M N 133-Pin CPGA A B C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 12 13 Orientation Pin

A6 PRA, I/O E2 I/O L2 I/O A7 NC E3 MODE L3 GND A8 I/O E11 V CC L4 I/O A9 I/O E12 I/O L5 I/O A10 I/O E13 I/O L6 PRB, I/O A11 I/O F1 I/O L7 GND A12 I/O F2 I/O L8 I/O A13 NC F3 I/O L9 I/O B1 I/O F4 I/O L10 IOPCL, I/O B2 V CC F10 GND L11 GND B3 I/O F11 I/O L12 I/O B4 I/O F12 I/O L13 I/O B5 I/O F13 I/O M1 I/O B6 CLKB, I/O G1 NC M2 V CC B7 V CC G2 V CC M3 GND B8 I/O G3 GND M4 I/O B9 I/O G4 I/O M5 I/O B10 I/O G10 I/O M6 I/O B11 I/O G11 GND M7 V CC B12 V CC G12 V CC M8 I/O B13 I/O G13 NC M9 I/O C1 I/O H1 I/O M10 I/O C2 SDI, I/O H2 I/O M11 I/O C3 GND H3 I/O M12 V CC C4 I/O H4 I/O M13 I/O C5 I/O H10 I/O N1 NC C6 I/O H11 I/O N2 I/O C7 GND H12 I/O N3 I/O C8 I/O H13 I/O N4 I/O C9 I/O J1 I/O N5 I/O C10 IOCLK, I/O J2 V CC N6 I/O C11 GND J3 I/O N7 NC C12 GND J11 I/O N8 I/O C13 I/O J12 V CC N9 I/O D1 I/O J13 I/O N10 I/O D2 I/O K1 I/O N11 I/O D3 I/O K2 I/O N12 GND D4 DCLK, I/O K3 I/O N13 NC D6 CLKA, I/O K6 I/O D7 I/O K7 HCLKA, I/O

Package Pin Assignments (continued) 176-Pin CPGA (Top View) A 23456789 1 0 1 1 B C D E F G H J K L 176-Pin CPGA 123456789 1 0 1 1 M N P R A B C D E F G H J K L M N P R

A8 I/O I/O D7 PRB, I/O PRB, I/O A9 CLKA, I/O CLKA, I/O D8 V CC VCC A10 I/O I/O D9 I/O I/O A11 I/O I/O D10 GND GND A12 I/O I/O D11 V CC VCC A13 I/O I/O D12 GND GND A14 I/O I/O D13 I/O I/O A15 I/O I/O D14 I/O I/O B1 I/O I/O D15 I/O I/O B2 I/O I/O E1 I/O I/O B3 DCLK, I/O DCLK, I/O E2 I/O I/O B4 I/O I/O E3 I/O I/O B5 I/O I/O E4 GND GND B6 I/O I/O E12 GND GND B7 I/O I/O E13 I/O I/O B8 CLKB, I/O CLKB, I/O E14 I/O I/O B9 I/O I/O E15 I/O I/O B10 I/O I/O F1 I/O I/O B11 I/O I/O F2 I/O I/O B12 I/O I/O F3 I/O I/O B13 I/O I/O F4 V CC VCC B14 SDI, I/O SDI, I/O F12 GND GND B15 I/O I/O F13 I/O I/O C1 I/O I/O F14 I/O I/O C2 I/O I/O F15 I/O I/O C3 MODE MODE G1 I/O I/O C4 I/O I/O G2 I/O I/O C5 I/O I/O G3 I/O I/O C6 I/O I/O G4 GND GND C7 I/O I/O G12 V CC VCC C8 GND GND G13 I/O I/O C9 PRA, I/O PRA, I/O G14 I/O I/O C10 I/O I/O G15 I/O I/O C11 I/O I/O H1 I/O I/O C12 I/O I/O H2 V CC VCC C13 I/O I/O H3 V CC VCC C14 I/O I/O H4 GND GND

176-Pin CPGA (Continued) Pin Number A1280A Function A1280XL Function Pin Number A1280A Function A1280XL Function

Package Pin Assignments (continued) 207-Pin CPGA (Top View) A B C D E F G H J K L M N P R S T 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 A B C D E F G H J K L M N P R S T 207-Pin CPGA

A7 I/O C16 I/O H1 PRA, I/O A8 I/O C17 I/O H2 I/O A9 I/O D1 I/O H3 I/O A10 I/O D2 I/O H4 I/O A11 I/O D3 I/O H14 I/O A12 I/O D4 GND H15 I/O A13 I/O D5 GND H16 I/O A14 I/O D6 I/O H17 I/O A15 I/O D7 MODE J1 I/O A16 NC D8 I/O J2 V CC A17 NC D9 GND J3 CLKB, I/O B1 NC D10 I/O J4 GND B2 V CC D11 V CC J14 GND B3 I/O D12 I/O J15 HCLK, I/O B4 I/O D13 I/O J16 V CC B5 I/O D14 GND J17 I/O B6 I/O D15 I/O K1 CLKA, I/O B7 I/O D16 I/O K2 I/O B8 I/O D17 I/O K3 I/O B9 V CC E1 I/O K4 I/O B10 I/O E2 I/O K14 I/O B11 I/O E3 I/O . K15 I/O B12 I/O E4 DCLK, I/O K16 PRB, I/O B13 I/O E14 I/O K17 I/O B14 I/O E15 I/O L1 I/O B15 I/O E16 I/O L2 I/O B16 V CC E17 I/O L3 I/O B17 NC F1 I/O L4 I/O C1 NC F2 I/O L14 I/O C2 NC F3 I/O L15 I/O C3 SDI, I/O F4 I/O L16 I/O C4 I/O F14 I/O L17 I/O C5 I/O F15 I/O M1 I/O C6 I/O F16 I/O M2 I/O C7 I/O F17 I/O M3 I/O C8 I/O G1 I/O M4 I/O C9 I/O G2 I/O M14 I/O

N14 IOPCL, I/O R7 I/O S17 NC N15 I/O R8 I/O T1 NC N16 I/O R9 I/O T2 NC N17 I/O R10 I/O T3 I/O P1 I/O R11 I/O T4 I/O P2 I/O R12 I/O T5 V CC P3 GND R13 I/O T6 I/O P4 GND R14 I/O T7 I/O P5 IOCLK, I/O R15 GND T8 I/O P6 I/O R16 I/O T9 I/O P7 GND R17 I/O T10 I/O P8 I/O S1 NC T11 I/O P9 GND S2 V CC T12 I/O P10 I/O S3 NC T13 I/O P11 I/O S4 I/O T14 I/O P12 V CC S5 I/O T15 I/O P13 I/O S6 I/O T16 NC P14 GND S7 I/O T17 NC P15 I/O S8 I/O P16 I/O S9 V CC 207-Pin CPGA (Continued) Pin Number A1460A Function Pin Number A1460A Function Pin Number A1460A Function

Package Pin Assignments (continued) 257-Pin CPGA (Top View) A B C D E F G H J K L M N P R T V X Y A B C D E F G H J K L M N P R T V X Y 1 2 3 4 5 6 7 8 9 1 01 11 2 1 31 41 51 6 1 71 81 9 1 2 3 4 5 6 7 8 9 1 01 11 2 1 31 41 51 6 1 71 81 9 257-Pin CPGA

B4 SDI, I/O D10 GND H4 I/O B5 I/O D11 I/O H16 I/O B6 I/O D12 I/O H17 I/O B7 I/O D13 I/O H18 I/O B8 I/O D14 I/O H19 I/O B9 I/O D15 I/O J1 PRA, I/O B10 I/O D16 GND J2 I/O B11 I/O D17 I/O J3 I/O B12 I/O D18 I/O J4 I/O B13 I/O D19 I/O J5 GND B14 I/O E1 I/O J15 I/O B15 I/O E2 I/O J16 HCLK, I/O B16 GND E3 I/O J17 PRB, I/O B17 I/O E4 DCLK, I/O J18 I/O B18 I/O E5 NC J19 I/O B19 I/O E7 I/O K1 I/O C1 I/O E9 I/O K2 I/O C2 I/O E11 GND K3 V CC C3 V CC E13 I/O K4 GND C4 GND E16 I/O K16 GND C5 I/O E17 I/O K17 V CC C6 I/O E18 I/O K18 I/O

L3 I/O R16 IOPCL, I/O X1 I/O L4 CLKA, I/O R17 I/O X2 I/O L5 CLKB, I/O R18 I/O X3 I/O L15 GND R19 I/O X4 I/O L16 I/O T1 I/O X5 I/O L17 I/O T2 I/O X6 I/O L18 I/O T3 I/O X7 GND L19 I/O T4 GND X8 I/O M1 I/O T5 IOCLK, I/O X9 I/O M2 I/O T6 I/O X10 I/O M3 I/O T7 I/O X11 I/O M4 I/O T8 I/O X12 I/O M16 I/O T9 I/O X13 I/O M17 I/O T10 GND X14 V CC M18 I/O T11 I/O X15 I/O M19 I/O T12 I/O X16 I/O N1 I/O T13 I/O X17 I/O N2 I/O T14 I/O X18 I/O N3 I/O T15 I/O X19 I/O N4 I/O T16 GND Y1 I/O N5 I/O T17 GND Y2 I/O N15 I/O T18 I/O Y3 I/O N16 I/O T19 I/O Y4 I/O N17 I/O V1 I/O Y5 I/O N18 I/O V2 I/O Y6 I/O N19 I/O V3 V CC Y7 I/O P1 I/O V4 I/O Y8 I/O P2 I/O V5 I/O Y9 I/O P3 I/O V6 I/O Y10 I/O P4 I/O V7 V CC Y11 I/O P16 I/O V8 I/O Y12 I/O P17 I/O V9 I/O Y13 I/O P18 I/O V10 V CC Y14 I/O P19 I/O V11 I/O Y15 I/O R1 I/O V12 I/O Y16 I/O R2 I/O V13 I/O Y17 I/O R3 I/O V14 I/O Y18 I/O R4 GND V15 I/O Y19 I/O R7 I/O V16 I/O 257-Pin CPGA (Continued) Pin Number A14100A Function Pin Number A14100A Function Pin Number A14100A Function

Package Pin Assignments (continued) 84-Pin CQFP (Top View) Pin #1 Index 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 84-Pin CQFP

1 NC GND 43 I/O GND

2 I/O MODE 44 I/O I/O

3 I/O I/O 45 I/O I/O

4 I/O I/O 46 I/O I/O

5 I/O I/O 47 I/O I/O

6 I/O I/O 48 I/O I/O

8 GND I/O 50 GND GND

9 I/O I/O 51 I/O TCK, I/O

10 I/O GND 52 I/O GND

11 I/O V CC 53 CLKA, I/O V CC

12 I/O V CC 54 I/O V CC

13 I/O I/O 55 MODE V CC

14 V CC I/O 56 V CC VCC

15 V CC I/O 57 V CC I/O

16 I/O I/O 58 I/O I/O

17 I/O GND 59 I/O GND

18 I/O I/O 60 I/O I/O

19 I/O I/O 61 SDI, I/O I/O

20 I/O I/O 62 DCLK, I/O I/O

21 I/O I/O 63 PRA, I/O GND

22 V CC GND 64 PRB, I/O SDI, I/O

23 I/O I/O 65 I/O I/O (WD)

24 I/O I/O 66 I/O I/O (WD)

25 I/O I/O (WD) 67 I/O I/O (WD)

26 I/O I/O (WD) 68 I/O I/O (WD)

27 I/O I/O 69 I/O QCLKD, I/O

28 I/O QCLKA, I/O 70 I/O I/O (WD)

29 GND GND 71 GND I/O (WD)

30 I/O I/O (WD) 72 I/O PRA, I/O

31 I/O I/O 73 I/O CLKA, I/O

32 I/O GND 74 I/O V

33 I/O V CC 75 I/O GND

34 I/O I/O (WD) 76 I/O CLKB, I/O

35 V CC I/O (WD) 77 V CC PRB, I/O

36 I/O QCLKB, I/O 78 I/O I/O (WD)

37 I/O I/O (WD) 79 I/O I/O (WD)

38 I/O GND 80 I/O QCLKC, I/O

39 I/O I/O (WD) 81 I/O GND

40 I/O I/O (WD) 82 I/O I/O (WD)

41 I/O I/O (WD) 83 I/O I/O (WD)

42 I/O SDO, I/O 84 I/O DCLK, I/O

Package Pin Assignments (continued) 132-Pin CQFP (Top View) 132-Pin CQFP Pin #1 Index 132 131 130 129 128 127 126 125 124 107 106 105 104 103 102 101 100 34 35 36 37 38 39 40 41 42 59 60 61 62 63 64 65 66

1 NC 45 I/O 89 V CC

2 GND 46 I/O 90 GND

3 SDI, I/O 47 I/O 91 V CC

4 I/O 48 PRB, I/O 92 GND

5 I/O 49 I/O 93 I/O

6 I/O 50 HCLK, I/O 94 I/O

7 I/O 51 I/O 95 I/O

8 I/O 52 I/O 96 I/O

9 MODE 53 I/O 97 I/O

10 GND 54 I/O 98 IOCLK, I/O

12 I/O 56 I/O 100 NC

13 I/O 57 I/O 101 GND

14 I/O 58 GND 102 I/O

15 I/O 59 V

16 I/O 60 I/O 104 I/O

17 I/O 61 I/O 105 I/O

18 I/O 62 I/O 106 GND

19 I/O 63 I/O 107 V

20 I/O 64 IOPCL, I/O 108 I/O

21 I/O 65 GND 109 I/O

23 I/O 67 NC 111 I/O

24 I/O 68 I/O 112 I/O

25 I/O 69 I/O 113 I/O

26 GND 70 I/O 114 I/O

28 I/O 72 I/O 116 CLKA, I/O

29 I/O 73 I/O 117 CLKB, I/O

30 I/O 74 GND 118 PRA, I/O

31 I/O 75 V

32 I/O 76 I/O 120 I/O

33 I/O 77 I/O 121 I/O

34 NC 78 V

35 I/O 79 I/O 123 V CC

36 GND 80 I/O 124 I/O

37 I/O 81 I/O 125 I/O

38 I/O 82 I/O 126 I/O

39 I/O 83 I/O 127 I/O

40 I/O 84 I/O 128 I/O

41 I/O 85 I/O 129 I/O

42 GND 86 I/O 130 I/O

CC 87 I/O 131 DCLK, I/O

44 I/O 88 I/O 132 NC

Package Pin Assignments (continued) 172-Pin CQFP (Top View) 172-Pin CQFP Pin #1 Index 172 171 170 169 168 167 166 165 164 137 136 135 134 133 132 131 130 44 45 46 47 48 49 50 51 52 79 80 81 82 83 84 85 86 122 123 124 125 126 127 128 129

1 MODE MODE 45 I/O I/O

2 I/O I/O 46 I/O I/O

3 I/O I/O 47 I/O I/O

4 I/O I/O 48 I/O I/O

5 I/O I/O 49 I/O I/O

6 I/O I/O 50 V

7 GND GND 51 I/O I/O

8 I/O I/O 52 I/O I/O

9 I/O I/O 53 I/O I/O

10 I/O I/O 54 I/O I/O

11 I/O I/O 55 GND GND

12 V CC VCC 56 I/O I/O

13 I/O I/O 57 I/O I/O

14 I/O I/O 58 I/O I/O

15 I/O I/O 59 I/O I/O

16 I/O I/O 60 I/O I/O

17 GND GND 61 I/O I/O

18 I/O I/O 62 I/O I/O

19 I/O I/O 63 I/O I/O

20 I/O I/O 64 I/O I/O

21 I/O I/O 65 GND GND

22 GND GND 66 V

23 V CC VCC 67 I/O I/O

24 V CC VCC 68 I/O I/O

25 I/O I/O 69 I/O I/O

26 I/O I/O 70 I/O I/O

27 V CC VCC 71 I/O I/O

28 I/O I/O 72 I/O I/O

29 I/O I/O 73 I/O I/O

30 I/O I/O 74 I/O I/O

31 I/O I/O 75 GND GND

32 GND GND 76 I/O I/O

33 I/O I/O 77 I/O I/O

34 I/O I/O 78 I/O I/O

35 I/O I/O 79 I/O I/O

36 I/O I/O 80 V

37 GND GND 81 I/O I/O

38 I/O I/O 82 I/O I/O

39 I/O I/O 83 I/O I/O

40 I/O I/O 84 I/O I/O

41 I/O I/O 85 I/O I/O

42 I/O I/O 86 I/O I/O

43 I/O I/O 87 I/O I/O

44 I/O I/O 88 I/O I/O

89 I/O I/O 131 SDI, I/O SDI, I/O

90 I/O I/O 132 I/O I/O

91 I/O I/O 133 I/O I/O

92 I/O I/O 134 I/O I/O

93 I/O I/O 135 I/O I/O

94 I/O I/O 136 V

95 I/O I/O 137 I/O I/O

96 I/O I/O 138 I/O I/O

97 I/O I/O 139 I/O I/O

98 GND GND 140 I/O I/O

99 I/O I/O 141 GND GND

100 I/O I/O 142 I/O I/O

101 I/O I/O 143 I/O I/O

102 I/O I/O 144 I/O I/O

103 GND GND 145 I/O I/O

104 I/O I/O 146 I/O I/O

105 I/O I/O 147 I/O I/O

106 GND GND 148 PRA, I/O PRA, I/O

108 GND GND 150 CLKA, I/O CLKA, I/O

109 V CC VCC 151 V CC VCC

110 V CC VCC 152 GND GND

111 I/O I/O 153 I/O I/O

112 I/O I/O 154 CLKB, I/O CLKB, I/O

114 I/O I/O 156 PRB, I/O PRB, I/O

115 I/O I/O 157 I/O I/O

116 I/O I/O 158 I/O I/O

117 I/O I/O 159 I/O I/O

118 GND GND 160 I/O I/O

119 I/O I/O 161 GND GND

120 I/O I/O 162 I/O I/O

121 I/O I/O 163 I/O I/O

122 I/O I/O 164 I/O I/O

123 GND GND 165 I/O I/O

124 I/O I/O 166 V

125 I/O I/O 167 I/O I/O

126 I/O I/O 168 I/O I/O

127 I/O I/O 169 I/O I/O

128 I/O I/O 170 I/O I/O

129 I/O I/O 171 DCLK, I/O DCLK, I/O

130 I/O I/O 172 I/O I/O

172-Pin CQFP (Continued) Pin Number A1280A Function A1280XL Function Pin Number A1280A Function A1280XL Function

Package Pin Assignments (continued) 196-Pin CQFP (Top View) 196-Pin CQFP Pin #1 Index 196 195 194 193 192 191 190 189 188 155 154 153 152 151 150 149 148 50 51 52 53 54 55 56 57 58 91 92 93 94 95 96 97 98 100 101 102 103 104 105 106 107 140 141 142 143 144 145 146 147

1 GND 44 I/O 87 I/O

2 SDI, I/O 45 I/O 88 I/O

3 I/O 46 I/O 89 I/O

4 I/O 47 I/O 90 I/O

5 I/O 48 I/O 91 I/O

6 I/O 49 I/O 92 I/O

7 I/O 50 I/O 93 I/O

8 I/O 51 GND 94 V

9 I/O 52 GND 95 I/O

10 I/O 53 I/O 96 I/O

11 MODE 54 I/O 97 I/O

13 GND 56 I/O 99 I/O

14 I/O 57 I/O 100 IOPCL, I/O

15 I/O 58 I/O 101 GND

16 I/O 59 V

17 I/O 60 I/O 103 I/O

18 I/O 61 I/O 104 I/O

19 I/O 62 I/O 105 I/O

20 I/O 63 I/O 106 I/O

21 I/O 64 GND 107 I/O

22 I/O 65 I/O 108 I/O

23 I/O 66 I/O 109 I/O

24 I/O 67 I/O 110 V

25 I/O 68 I/O 111 V CC

26 I/O 69 I/O 112 GND

27 I/O 70 I/O 113 I/O

28 I/O 71 I/O 114 I/O

29 I/O 72 I/O 115 I/O

30 I/O 73 I/O 116 I/O

31 I/O 74 I/O 117 I/O

32 I/O 75 PRB, I/O 118 I/O

33 I/O 76 I/O 119 I/O

34 I/O 77 HCLK, I/O 120 I/O

35 I/O 78 I/O 121 I/O

36 I/O 79 I/O 122 I/O

37 GND 80 I/O 123 I/O

39 V CC 82 I/O 125 I/O

40 I/O 83 I/O 126 I/O

41 I/O 84 I/O 127 I/O

42 I/O 85 I/O 128 I/O

43 I/O 86 GND 129 I/O

130 I/O 153 I/O 176 I/O

131 I/O 154 I/O 177 I/O

132 I/O 155 V

133 I/O 156 I/O 179 I/O

134 I/O 157 I/O 180 I/O

135 I/O 158 I/O 181 I/O

136 I/O 159 I/O 182 I/O

138 GND 161 I/O 184 I/O

139 GND 162 GND 185 I/O

141 I/O 164 I/O 187 I/O

142 I/O 165 I/O 188 I/O

143 I/O 166 I/O 189 V

144 I/O 167 I/O 190 I/O

145 I/O 168 I/O 191 I/O

146 I/O 169 I/O 192 I/O

147 I/O 170 I/O 193 GND

148 IOCLK, I/O 171 I/O 194 I/O

149 GND 172 CLKA, I/O 195 I/O

150 I/O 173 CLKB, I/O 196 DCLK, I/O

151 I/O 174 PRA, I/O

152 I/O 175 I/O

196-Pin CQFP (Continued) Pin Number A1460A Function Pin Number A1460A Function Pin Number A1460A Function

Package Pin Assignments (continued) 208-Pin CQFP (Top View) 208-Pin CQFP Pin #1 Index 208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157 53 54 55 56 57 58 59 60 61 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 149 150 151 152 153 154 155 156

3 MODE 46 I/O 89 I/O

5 I/O 48 I/O 91 QCLKB, I/O

7 I/O 50 I/O 93 I/O (WD)

8 I/O 51 I/O 94 I/O (WD)

10 I/O 53 GND 96 I/O

11 I/O 54 TMS, I/O 97 I/O

12 I/O 55 TDI, I/O 98 V

13 I/O 56 I/O 99 I/O

14 I/O 57 I/O (WD) 100 I/O (WD)

15 I/O 58 I/O (WD) 101 I/O (WD)

16 I/O 59 I/O 102 I/O

CC 60 V CC 103 SDO, I/O

19 I/O 62 I/O 105 GND

20 I/O 63 I/O 106 V

21 I/O 64 I/O 107 I/O

22 GND 65 QCLKA, I/O 108 I/O

23 I/O 66 I/O (WD) 109 I/O

24 I/O 67 I/O (WD) 110 I/O

25 I/O 68 I/O 111 I/O

26 I/O 69 I/O 112 I/O

27 GND 70 I/O (WD) 113 I/O

CC 71 I/O (WD) 114 I/O

29 V CC 72 I/O 115 I/O

34 I/O 77 I/O 120 I/O

35 I/O 78 GND 121 I/O

36 I/O 79 V

37 I/O 80 V CC 123 I/O

38 I/O 81 I/O 124 I/O

39 I/O 82 I/O 125 I/O

40 I/O 83 I/O 126 GND

42 I/O 85 I/O (WD) 128 TCK, I/O

43 I/O 86 I/O (WD) 129 GND

130 V CC 157 GND 184 GND

131 GND 158 I/O 185 I/O

CC 159 SDI, I/O 186 CLKB, I/O

133 V CC 160 I/O 187 I/O

134 I/O 161 I/O (WD) 188 PRB, I/O

135 I/O 162 I/O (WD) 189 I/O

CC 163 I/O 190 I/O (WD)

137 I/O 164 V CC 191 I/O (WD)

138 I/O 165 I/O 192 I/O

139 I/O 166 I/O 193 I/O

140 I/O 167 I/O 194 I/O (WD)

141 I/O 168 I/O (WD) 195 I/O (WD)

142 I/O 169 I/O (WD) 196 QCLKC, I/O

143 I/O 170 I/O 197 I/O

144 I/O 171 QCLKD, I/O 198 I/O

145 I/O 172 I/O 199 I/O

146 I/O 173 I/O 200 I/O

147 I/O 174 I/O 201 I/O

148 I/O 175 I/O 202 V

149 I/O 176 I/O (WD) 203 I/O (WD)

150 GND 177 I/O (WD) 204 I/O (WD)

151 I/O 178 PRA, I/O 205 I/O

152 I/O 179 I/O 206 I/O

153 I/O 180 CLKA, I/O 207 DCLK, I/O

154 I/O 181 I/O 208 I/O

155 I/O 182 V

156 I/O 183 V CC

208-Pin CQFP (Continued) Pin Number A32100DX Function Pin Number A32100DX Function Pin Number A32100DX Function

Package Pin Assignments (continued) 256-Pin CQFP (Top View) 256-Pin CQFP Pin #1 Index 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 185 186 187 188 189 190 191 192

1 GND NC 45 I/O I/O 89 I/O I/O

2 SDI, I/O GND 46 V CC I/O 90 PRB, I/O I/O

3 I/O I/O 47 I/O I/O 91 GND I/O

4 I/O I/O 48 I/O GND 92 V

5 I/O I/O 49 I/O I/O 93 GND I/O

6 I/O I/O 50 I/O I/O 94 V CC I/O

7 I/O I/O 51 I/O I/O 95 I/O V CC

8 I/O I/O 52 I/O I/O 96 HCLK, I/O V CC

9 I/O I/O 53 I/O I/O 97 I/O GND

10 I/O GND 54 I/O I/O 98 I/O GND

11 MODE I/O 55 I/O I/O 99 I/O I/O

12 I/O I/O 56 I/O I/O 100 I/O I/O

13 I/O I/O 57 I/O I/O 101 I/O I/O

14 I/O I/O 58 I/O I/O 102 I/O I/O

15 I/O I/O 59 GND I/O 103 I/O I/O

16 I/O I/O 60 I/O V

17 I/O I/O 61 I/O GND 105 I/O I/O (WD)

18 I/O I/O 62 I/O GND 106 I/O I/O (WD)

19 I/O I/O 63 I/O NC 107 I/O I/O

20 I/O I/O 64 I/O NC 108 I/O I/O

21 I/O I/O 65 I/O NC 109 I/O I/O (WD)

22 I/O I/O 66 I/O I/O 110 GND I/O (WD)

23 I/O I/O 67 I/O SDO, I/O 111 I/O I/O

24 I/O I/O 68 I/O I/O 112 I/O QCLKA, I/O

25 I/O I/O 69 I/O I/O (WD) 113 I/O I/O

26 I/O V

CC 70 I/O I/O (WD) 114 I/O GND

27 I/O I/O 71 I/O I/O 115 I/O I/O

CC I/O 72 I/O V CC 116 I/O I/O

29 GND V CC 73 I/O I/O 117 I/O I/O

30 V CC VCC 74 I/O I/O 118 I/O I/O

31 GND GND 75 I/O I/O 119 I/O V CC

32 I/O V CC 76 I/O I/O (WD) 120 I/O I/O

33 I/O GND 77 I/O GND 121 I/O I/O (WD)

34 I/O TCK, I/O 78 I/O I/O (WD) 122 I/O I/O (WD)

35 I/O I/O 79 I/O I/O 123 I/O I/O

36 I/O GND 80 I/O QCLKB, I/O 124 I/O I/O

37 I/O I/O 81 I/O I/O 125 I/O TDI, I/O

38 I/O I/O 82 I/O I/O 126 I/O TMS, I/O

39 I/O I/O 83 I/O I/O 127 IOPCL, I/O GND

40 I/O I/O 84 I/O I/O 128 GND NC

41 I/O I/O 85 I/O I/O 129 I/O NC

42 I/O I/O 86 I/O I/O 130 I/O NC

43 I/O I/O 87 I/O I/O (WD) 131 I/O GND

44 I/O I/O 88 I/O I/O (WD) 132 I/O I/O

133 I/O I/O 175 GND I/O 217 I/O I/O

134 I/O I/O 176 GND I/O 218 I/O PRB, I/O

135 I/O I/O 177 I/O I/O 219 CLKA, I/O I/O

136 I/O I/O 178 I/O I/O 220 CLKB, I/O CLKB, I/O

137 I/O I/O 179 I/O I/O 221 V

138 I/O I/O 180 I/O GND 222 GND GND

139 I/O GND 181 I/O I/O 223 V

140 I/O I/O 182 I/O I/O 224 GND V CC

141 V CC I/O 183 I/O I/O 225 PRA, I/O V CC

142 I/O I/O 184 I/O I/O 226 I/O I/O

143 I/O I/O 185 I/O I/O 227 I/O CLKA, I/O

144 I/O I/O 186 I/O I/O 228 I/O I/O

145 I/O I/O 187 I/O I/O 229 I/O PRA, I/O

146 I/O I/O 188 IOCLK, I/O MODE 230 I/O I/O

147 I/O I/O 189 GND V

148 I/O I/O 190 I/O GND 232 I/O I/O (WD)

149 I/O I/O 191 I/O NC 233 I/O I/O (WD)

150 I/O I/O 192 I/O NC 234 I/O I/O

151 I/O I/O 193 I/O NC 235 I/O I/O

152 I/O I/O 194 I/O I/O 236 I/O I/O

153 I/O I/O 195 I/O DCLK, I/O 237 I/O I/O

154 I/O I/O 196 I/O I/O 238 I/O I/O

155 I/O V

CC 197 I/O I/O 239 I/O I/O

156 I/O I/O 198 I/O I/O 240 GND QCLKD, I/O

157 I/O I/O 199 I/O I/O (WD) 241 I/O I/O

158 GND V

CC 200 I/O I/O (WD) 242 I/O I/O (WD)

159 V CC VCC 201 I/O V CC 243 I/O GND

160 GND GND 202 I/O I/O 244 I/O I/O (WD)

161 V CC I/O 203 I/O I/O 245 I/O I/O

162 I/O I/O 204 I/O I/O 246 I/O I/O

163 I/O I/O 205 I/O I/O 247 I/O I/O

164 I/O I/O 206 I/O GND 248 I/O V

165 I/O GND 207 I/O I/O 249 I/O I/O

166 I/O I/O 208 I/O I/O 250 I/O I/O (WD)

167 I/O I/O 209 I/O QCLKC, I/O 251 I/O I/O (WD)

168 I/O I/O 210 I/O I/O 252 I/O I/O

169 I/O I/O 211 I/O I/O (WD) 253 I/O SDI, I/O

170 I/O V

CC 212 I/O I/O (WD) 254 I/O I/O

171 I/O I/O 213 I/O I/O 255 I/O GND

172 I/O I/O 214 I/O I/O 256 DCLK, I/O NC

173 I/O I/O 215 I/O I/O (WD)

CC I/O 216 I/O I/O (WD) 256-Pin CQFP (Continued) Pin Number A14100A Function A32200DX Function Pin Number A14100A Function A32200DX Function Pin Number A14100A Function A32200DX Function

Package Mechanical Drawings 84-Pin CPGA Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. Orientation Pin .110" .120" .140" .100" BSC 0.18" ± .002" .050" ± .010"

1.000 BSC

.045 .055 L K J H G F E D C B A 1110987654321 Pin #1 ID

Package Mechanical Drawings (continued) 132-Pin CPGA Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. Orientation Pin .140" .100" BSC 0.18" ± .002" .050" ± .010"

1.200 BSC

.085" .110"Pin #1 ID .045 .055 11 12 1310987654321 N M L K J H G F E D C B A

Package Mechanical Drawings (continued) 133-Pin CPGA Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. 1.360" ± 0.015" square 0.120" 0.140" 0.100" BSC 0.018" ± 0.002" 0.050" ± 0.010" Pin #1 1.200" BSC 0.100" 0.130" 0.045" 0.055" Orientation Pin 11 12 1310987654321 N M L K J H G F E D C B A Top View Bottom View Side View

Package Mechanical Drawings (continued) 176-Pin CPGA Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. INDEX MARK 0.018" ± .002" 0.102" 0.132" 0.050" ± .005"

1.400 BSC

0.100" BSC 1.570" ± .015" square 0.120" 0.140" 11 12 13 14 1510987654321 R P N M L K J H G F E D C B A

Package Mechanical Drawings (continued) 207-Pin CPGA Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. INDEX MARK 0.100" BSC 0.120" ± 0.015" 11 12 13 14 15 16 1710987654321 U T R P N M L K J H G F E D C B A 1.600" BSC 0.018" ± 0.002" 0.180" ± 0.010" 0.05" ± 0.005" 1.77" ± 0.010" square 0.05" ± 0.005" Top View Side View Bottom View

Package Mechanical Drawings (continued) 257-Pin CPGA Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. 0.105" ± 0.012" 0.05" ± 0.005" 0.100" BSC Y X V T R P N M L K J H G F E D C B A 1 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 0.018" ± 0.002" 0.180" ± 0.010" 0.05" ± 0.01" 1.970" ± 0.015" square 1.800" BSC Top View Side View Bottom View

Package Mechanical Drawings (continued) 84-Pin CQFP Notes: 1. Seal ring and lid are connected to Ground. 2. Lead material is Kovar with minimum 50 microinches gold plate over nickel. 3. Packages are shipped unformed with the ceramic tie bar in a test carrier. e A c H E2 E1 b F Lid Top View Side View

Package Mechanical Drawings (continued) 132-Pin, 172-Pin, 196-Pin, 208-Pin, and 256-Pin CQFP (Cavity Up) Notes: 1. Outside leadframe holes (from dimension H) are circular for the CQ208 and CQ256. 2. Seal ring and lid are connected to Ground. 3. Lead material is Kovar with minimum 50 microinches gold plate over nickel. 4. Packages are shipped unformed with the ceramic tie bar. 5. 32200DX – CQ208 has a heat sink on the back. A b H E2 E1 F L1 K Ceramic Tie Bar No. 1 e C Lead Kovar Lid Top View Side View

CQFP (Ceramic Quad Flat Pack) CQFP 84 CQFP 132 CQFP 172 CQFP 196 D2/E2 0.500 BSC 0.800 BSC 1.050 BSC 1.200 BSC e 0.025 BSC 0.025 BSC 0.025 BSC 0.025 BSC H 1.460 BSC 2.320 BSC 2.320 BSC 2.320 BSC K — 2.140 BSC 2.140 BSC 2.140 BSC Note: 1. All dimensions are in inches except CQ208 and CQ256, which are in millimeters. 2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. CQFP (Ceramic Quad Flat Pack) CQFP 208 CQFP 256 D2/E2 25.5 BSC 31.5 BSC e 0.50 BSC 0.50 BSC H 70.00 BSC 70.00 BSC K 65.90 BSC 65.90 BSC Note: 1. All dimensions are in inches except CQ208 and CQ256, which are in millimeters. 2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Actel Corporation

955 East Arques Avenue

Sunnyvale, California 94086 USA Tel:(408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan 5192641-2/1.00

Product Information

A1425 specifications and overview.

Summary

Highly Predictable Performance with 100% Automatic Placement and Routing

Description

Highly Predictable Performance with 100% Automatic Placement and Routing

Source title A1425 Datasheet(PDF) - Actel Corporation

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