A119X

A119X ALLEGRO | Alldatasheet

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Technical content

DESCRIPTION

The A119x and A119x-F comprise a family of two-wire, unipolar, Hall-effect switches, which can be trimmed by the user at end-of-line to optimize magnetic switchpoint accuracy in the application. The latter (-F option) are temperature- compensated for use with ferrite magnets. These devices are produced on the Allegro ™ advanced BiCMOS wafer fabrication process, which implements a patented high-frequency, 4-phase, chopper stabilization technique. This technique achieves magnetic stability over the full operating temperature range, and eliminates offsets inherent in devices with a single Hall element that are exposed to harsh application environments. The A119x and A119x-F family has a number of automotive applications. These include sensing seat track position, seat belt buckle presence, hood/trunk latching, and shift selector position. Two-wire unipolar switches are particularly advantageous in cost-sensitive applications because they require one less wire for operation versus the more traditional open-collector output switches. Additionally, the system designer inherently gains diagnostics because there is always output current flowing, which should be in either of two narrow ranges. Any current level not within these ranges indicates a fault condition. All family members are offered in three package styles. The LH is a SOT-23W style, miniature, low-profile package for surface- mount applications. The UA is a 3-pin, ultra-mini, single inline package (SIP) for through-hole mounting. The UB is a 2-pin single inline package (SIP) for through-hole mounting that integrates the power supply decoupling capacitor. All three packages are lead (Pb) free, with 100% matte-tin leadframe plating. A1190-DS, Rev. 7 FEATURES AND BENEFITS ▪ Choice of factory-set temperature coefficient (TC) for use with ferrite or rare-earth magnets ▪ Field programm able for optimi zed switchpoints AEC-Q100 automotive qualifi ed ▫ On-board volta ge regulator: 3 to 24 V operation High-speed, 4-phase chopper stabilization Low switchpoint drift througho ut temperature range Low sensitivity to thermal and mechanical stresses On-chip protec tion ▫ Supply transien t protection Reverse-battery protection Industry-leading ISO 7637-2 performance through use of proprietary, 40 V clamping structure Solid-state reli ability ▪ Robust EMC and ESD performance ▪ UB package w ith integrated 0. 1 µF bypass capacitor Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches Functional Block Diagram A119x and A119x-F Packages Not to scale 3-pin SOT23-W 2 mm × 3 mm × 1 mm (suffix LH) 3-pin ultramini SIP 1.5 mm × 4 mm × 3 mm (suffix UA) 2-pin ultramini SIP 1.5 mm × 4 mm × 4 mm (suffix UB) Amp Regula To all subcircuits tor Schmitt Trigger Polarity Low-Pass Filter GND VCC GND UA package only UB package only LH &U A package only 0 µF µF Clock/Logic Dynamic Offse t Cancellation Sample and Hold Program / Lock ICC Adjust Offset Adjust

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. SELECTION GUIDE Part Number Package Packing1 Temperature Coefficient Output (ICC) in South Polarity Field Supply Current at ICC(L) (mA) Magnetic Operate Point, BOP (G) A1190LLHLT-T2 LH (3-pin SOT23-W surface-mount) 7-in. reel, 3000 pieces/reel SmCo Low 2 to 5 10 to 200 A1190LLHLX-T LH (3-pin SOT23-W surface-mount) 13-in. reel, 10000 pieces/reel SmCo A1190LUA-T3 UA (3-pin SIP through-hole) Bulk, 500 pieces/bag SmCo A1190LUBTN-T UB (2-pin SIP through-hole) 13-in. reel, 4000 pieces/reel SmCo A1192LLHLT-T2 LH (3-pin SOT23-W surface-mount) 7-in. reel, 3000 pieces/reel SmCo 5 to 6.9 A1192LLHLT-F-T2 LH (3-pin SOT23-W surface-mount) 7-in. reel, 3000 pieces/reel Ferrite A1192LLHLX-T LH (3-pin SOT23-W surface-mount) 13-in. reel, 10000 pieces/reel SmCo A1192LLHLX-F-T LH (3-pin SOT23-W surface-mount) 13-in. reel, 10000 pieces/reel Ferrite A1192LUA-T3 UA (3-pin SIP through-hole) Bulk, 500 pieces/bag SmCo A1192LUA-F-T3 UA (3-pin SIP through-hole) Bulk, 500 pieces/bag Ferrite A1192LUBTN-T UB (2-pin SIP through-hole) 13-in. reel, 4000 pieces/reel SmCo A1192LUBTN-F-T UB (2-pin SIP through-hole) 13-in. reel, 4000 pieces/reel Ferrite A1193LLHLT-T2 LH (Surface mount) 7-in. reel, 3000 pieces/reel SmCo High A1193LLHLT-F-T2 LH (Surface mount) 7-in. reel, 3000 pieces/reel Ferrite A1193LLHLX-T LH (Surface mount) 13-in. reel, 10000 pieces/reel SmCo A1193LLHLX-F-T LH (Surface mount) 13-in. reel, 10000 pieces/reel Ferrite A1193LUA-T3 UA (3-pin SIP through-hole) Bulk, 500 pieces/bag SmCo A1193LUA-F-T3 UA (3-pin SIP through-hole) Bulk, 500 pieces/bag Ferrite A1193LUBTN-T UB (2-pin SIP through-hole) 13-in. reel, 4000 pieces/reel SmCo A1193LUBTN-F-T UB (2-pin SIP through-hole) 13-in. reel, 4000 pieces/reel Ferrite 1 Contact Allegro™ for additional packing options. 2 These variants available only through authorized distributors. 3 Contact factory for availability. RoHS COMPLIANT

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Notes Rating Unit Forward Supply Voltage VCC 28 V Reverse Supply Voltage VRCC –18 V Magnetic Flux Density B Unlimited G Operating Ambient Temperature TA Range L –40 to 150 ºC Maximum Junction Temperature TJ(max) 165 ºC Storage Temperature Tstg –65 to 170 ºC INTERNAL DISCRETE CAPACITOR RATINGS (UB PACKAGE ONLY) Characteristic Symbol Notes Rating Unit Rated Normal Capacitance CSUPPLY Connected between VCC and GND 0.1 µF Rated Voltage VCSUPPLY 50 V Rated Capacitor Tolerance ±10 % Temperature Designator X7R – SPECIFICATIONS

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. NC 1 2 1 32 Pinout Diagrams Terminal List Table Number Name Function LH package UA package UB package

1 VCC VCC VCC

Connects power supply to chip; used to apply programming signal

2 NC GND GND

LH package: no connection, it is highly recommended that this pin be tied to GND UA, UB package: ground terminal

3 GND GND – Ground terminal

Name Functional Description Quantity of Bits BOP Trim Fine trim of Programmable Magnetic Operating Point 6 Programming Lock Lock access to programming 1 1 2 PINOUT DIAGRAMS AND TERMINAL LIST TABLE

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS: Valid at TA = –40°C to 150°C, TJ < TJ(max), through operating supply voltage range, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit Supply Voltage1 VCC Operating, TJ ≤ 165 °C 3 – 24 V Supply Current ICC(L) A1190 B > BOP 2 – 5 mA A1192, A1192-F B > BOP 5 – 6.9 mA A1193, A1193-F B < BRP 5 – 6.9 mA ICC(H) A1190, A1192, A1192-F B < BRP 12 – 17 mA A1193, A1193-F B > BOP 12 – 17 mA Supply Zener Clamp Voltage V Z(sup) ICC = ICC(L)(max) + 3 mA, TA = 25°C 28 – – V Supply Zener Clamp Current I Z(sup) VZ(sup) = 28 V – – ICC(L)(max) + 3 mA mA Reverse Supply Current IRCC VRCC = –18 V – – –1.6 mA Output Slew Rate di/dt LH, UA package (no bypass capacitor2); capacitance of probe CS = 20 pF – 90 – mA / µs UB package (integrated capacitor3); capacitance of probe CS = 20 pF – 0.22 – mA/µs Chopping Frequency fC – 700 – kHz Power-Up Time4 ton LH, UA packages: A1190, A1192, A1192-F CBYP = 0.01 µF, B > BOP + 10 G – – 25 µs UB package3: A1190, A1192, A1192-F B > BOP + 10 G – – 25 µs LH, UA packages: A1193, A1193-F C BYP = 0.01 µF, B < BRP – 10 G – – 25 µs UB package3: A1193, A1193-F B < BRP – 10 G – – 25 µs Power-Up State5,6 POS t on < ton(max) , VCC slew rate > 25 mV / µs – I CC(H) – – 1 VCC represents the generated voltage between the VCC pin and the GND pin. 2 Measured without bypass capacitor between VCC pin and the GND pin. Use of a bypass capacitor results in slower current change. 3 Measured with internal bypass capacitor (0.1 µF) between VCC and GND. Additional bypass capacitance results in slower current change. 4 Guaranteed by characterization and design. 5 Power-Up State as defined is true only with a VCC slew rate of 25 mV / µs or greater. 6 For t > ton and BRP < B < BOP , Power-Up State is not defined. MAGNETIC CHARACTERISTICS1: Valid at TA = –40°C to 150°C, TJ ≤ TJ (max), unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit2 Initial Operate Point BOP(init) – –14 10 G Programmable Magnetic Operating Point B OP TA = 25°C 10 – 200 G Average Magnetic Step Size3 STEPBOP TA = 25°C, VCC = 5 V 3 4.8 7.5 G Switchpoint T emperature Drift ΔBOP A1190, A1192, A1193 – ±20 – G A1192-F, A1193-F 10 to 200 G – –0.25 – %/°C Hysteresis BHYS 5 – 30 G 1 Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present). 2 1 G (gauss) = 0.1 mT (millitesla). 3 STEPBOP is a calculated average from the cumulative programmed bits.

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. THERMAL CHARACTERISTICS: may require derating at maximum conditions; see application information Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance RθJA Package LH, on 1-layer PCB based on JEDEC standard 228 ºC/W Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side 110 ºC/W Package UA, on 1-layer PCB with copper limited to solder pads 165 ºC/W Package UB, on 1-layer PCB with copper limited to solder pads 213 ºC/W *Additional thermal information available on the Allegro website. 20 40 60 80 100 120 140 160 180 Temperature (ºC) Maximum Allowable VCC (V) (RθJA = 228ºC/W) 1-layer PCB, Package LH (RθJA = 110ºC/W) 2-layer PCB, Package LH (RθJA = 165ºC/W) 1-layer PCB, Package UA VCC(min) VCC(max) (RθJA = 213ºC/W) 1-layer PCB, Package UB 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 Temperature (°C) Power Dissipation, PD (mW) (RθJA = 228ºC/W) 1-layer PCB, Package LH (RθJA = 110ºC/W) 2-layer PCB, Package LH (RθJA = 165ºC/W) 1-layer PCB, Package UA (RθJA = 213ºC/W) 1-layer PCB, Package UB Power Derating Curve Power Dissipation vs. Ambient Temperature

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Characteristic Performance VCC = 3.0 V VCC = 24 V -60 -40 -20 0 20 40 60 80 100 140 120 160 Ambient Temperature, TA (°C) Supply Current, ICC(H) (mA) Average Supply Current (High) versus Temperature A1190, A1192, A1193 VCC = 3.0 V VCC = 24 V 7.0 6.5 6.0 5.5 5.0 -60 -40 -20 0 20 40 60 80 100 140 120 160 Ambient Temperature, TA (°C) Supply Current, ICC(L) (mA) VCC = 3.0 V VCC = 24 V 5.0 4.5 4.0 3.5 3.0 2.5 2.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 -60 -40 -20 0 20 40 60 80 100 140 120 160 Ambient Temperature, TA (°C) Supply Current, ICC(L) (mA) Average Supply Current (Low) versus Temperature A1192, A1193 Average Supply Current (Low) versus Temperature A1190 Supply Voltage, VCC (V) Supply Current, ICC(H) (mA) 2 6 10 14 18 22 26 T A = 150°C TA = –40°C TA = 25°C Average Supply Current (High) versus Supply Voltage A1190, A1192, A1193 TA = 150°C TA = –40°C TA = 25°C 7.0 6.5 6.0 5.5 5.0 2 6 10 14 18 22 26 Supply Voltage, VCC (V) Supply Current, ICC(L) (mA) TA = 150°C TA = –40°C TA = 25°C 2 6 10 14 18 22 26 Supply Voltage, VCC (V) Supply Current, ICC(L) (mA) Average Supply Current (Low) versus Supply Voltage A1192, A1193 Average Supply Current (Low) versus Supply Voltage A1190

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. VCC = 3.0 V VCC = 24 V Ambient Temperature, TA (°C) -60 -40 -20 0 20 40 60 80 100 140 120 160 Applied Flux Density at Switchpoint Hysteresis, BHYS (G) Ambient Temperature, TA (°C) -60 -40 -20 0 20 40 60 80 100 140 120 160 Bit #5 Bit #4 Bit #3 Bit #2 Bit #1 Bit #0 160 140 120 100 -20 Average Operate Point, BOP (G) Code 0 4 8 12 16 20 24 28 32 36 BOP(init) Average Switchpoint Hysteresis versus Temperature Average Operate Point versus Code A1190, A1192, A1193 A1190, A1192, A1193

Worcester, Massachusetts 01615-0036 U.S.A. Figure 1. Alternative switching behaviors are available in the A119x device family. On the horizontal axis, the B+ direction indicates case of increasing north polarity). at the Hall sensor IC exceeds the operate point threshold, BOP . RP, the device output goes low (panel B). external mechanical vibration and electrical noise.

Worcester, Massachusetts 01615-0036 U.S.A. Figure 2. Typical application circuits

Worcester, Massachusetts 01615-0036 U.S.A. Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation) induced signal in the frequency domain, through modulation. put voltages and precise recoverability after temperature cycling.

Worcester, Massachusetts 01615-0036 U.S.A. pulses serially through the VCC (supply) pin of the device. low (VPL) (see figure 1 and table 1).

• In Blow mode, the value of a programmable parameter may be permanently set by blowing solid-state fuses internal to the device. Device locking is also accomplished in this mode. The programming sequence is designed to help prevent the device from being programmed accidentally; for example, as a result of noise on the supply line. Although any programmable variable power supply can be used to generate the pulse wave- forms, Allegro highly recommends using the Allegro Sensor IC Evaluation Kit, available through your local Allegro sales repre- sentative. The manual for the kit provides additional information on programming these devices, and is available for download on the Allegro MicroSystems website. Definition of Terms Register. The section of the programming logic that controls the choice of programmable modes and parameters. Bit Field. The internal fuses unique to each register, represented as a binary number. Changing the bit field selection in a particu- lar register causes its programmable parameter to change, based on the internal programming logic. Key. A series of VPM voltage pulses used to select a register or mode.

Table 1. Programming Pulse Requirements, Protocol at TA = 25°C (refer also to figure 4) Figure 4. Programming pulse definition (see table 1)

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Table 2. Programming Logic Table [MSB → LSB] Decimal Equivalent Try Mode

0 B OP Trim Up Counting

Initial value (below minimum |BOP| ) (Try mode sequence starts with code 1); Code corresponds to bit field value (code 1 selects bit field value 000001) 111111 63 Maximum selectable value (above maximum |BOP| )

1 B OP Trim Down Counting

Initial value (above maximum |BOP| ) (Try mode sequence starts with code 1); Code is automatically inverted (code 1 selects bit field value 111110) 000000 63 Minimum selectable value (below minimum |B OP|)

7 Fuse Check

000111 7 Check integrity of all fuse bits versus low threshold 001111 15 Check integrity of all fuse bits versus high threshold Blow Mode

0 B OP Trim

000000 0 Initial value (below minimum |BOP| ); (Only allows selection of 1 bit per sequence) 111111 63 Maximum selectable value (above maximum |BOP| ); (Only allows selection of 1 bit per sequence)

7 Programming Lock 001000 8 Locks out access to all registers except Fuse Check

Code. The number used to identify the combination of fuses activated in a bit field, expressed as the decimal equivalent of the binary value. The LSB of a bit field is denoted as code 1, or bit 0. Addressing. Setting the bit field code in a selected register by serially applying a pulse train through the VCC pin of the device. Each parameter can be measured during the addressing process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent. Fuse Blowing. Applying a VPH pulse of sufficient duration to permanently set an addressed bit by blowing a fuse internal to the device. Once a bit (fuse) has been blown, it cannot be reset. Blow Pulse. A VPH pulse of sufficient duration to blow the addressed fuse. Cycling the Supply. Powering-down, and then powering-up the supply voltage. Cycling the supply is used to clear the program- ming settings in Try mode. Programming Procedure Programming involves selection of a register, a mode, and then setting values for parameters in the register for evaluation or for fuse blowing. Figure 10 provides an overview state diagram. Register Selection Each programmable parameter can be accessed through a specific register. To select a register, a sequence of voltage pulses consisting of a VPH pulse, a series of VPM pulses, and a VPH pulse (with no VCC supply interruptions) must be applied serially to the VCC pin. The quantity of VPM pulses is called the key, and uniquely identifies each register. The pulses for selection of register key 1, is shown in figure 5. No VPM pulse is sent for key 0. The register selections are shown in table 2. Mode Selection After register selection, the mode is selected, either Try or Blow mode. Try mode is selected by default. To select Blow mode, that mode selection key must be sent.

Worcester, Massachusetts 01615-0036 U.S.A. complete example is provided in figure 12. each bit in the bit field must be blown individually. state of decimal code 0 (binary 000000). Figure 6. Try mode bit field addressing pulses Figure 7. Example of code 5 broken into its binary components Figure 5. Register selection pulse sequence

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. To correctly address the fuses to be blown, the code represent- ing the required parameter value must be translated into a binary number. For example, as shown in figure 7, decimal code 5 is equivalent to the binary number 101. Therefore bit 2 must be addressed and blown, the device power supply cycled, and then bit 0 must be addressed and blown. The order of blowing bits, however, is not important. Blowing bit 0 first, and then bit 2 is acceptable. Note: After blowing, the programming is not reversible, even after cycling the supply power. Although a register bit field fuse cannot be reset after it is blown, additional bits within the same register can be blown at any time until the device is locked. For example, if bit 1 (binary 10) has been blown, it is still possible to blow bit 0. The end result would be binary 11 (decimal code 3). Locking the Device After the required code for each parameter is programmed, the device can be locked to prevent further programming of any parameters. To do so, perform the following steps: Ensure that the CBLOW capacitor is mounted. 2. Select the Programming Loc k register (key 7). 3. Select Blow mode (key 9). 4. Address bit 3 (001000) by sending four VPM pulses. 5. Send one Blow pulse, at I PP and SRBLOW, and sustain it for tBLOW. 6. Delay for a tLOW interval, then power-down. 7. Optionally check all fuses. Fuse Checking Incorporated in the A1 19x family is circuitry to simultaneously check the integrity of the fuse bits. The fuse checking feature is enabled by using the Fuse Check register (selection key 7), and while in T ry mode, applying the codes shown in table 2. The register is only valid in Try mode and is available before or after the Programming Lock bit is set. Setting the fuse threshold high checks that all blown fuses are properly blown. Setting fuse threshold low checks all un-blown fuses are properly intact. The supply current increases by 250 µA if a marginal fuse is detected. If all fuses are correctly blown or fully intact, there will be no change in supply current. Additional Guidelines The additional guidelines in this section should be followed to ensure the proper behavior of these devices:

• A 0.1 μF blowing capacitor , CBLOW, must be mounted between the VCC pin and the GND pin during programming, to ensure enough current is available to blow fuses.
• The power supply used for programming must be capable of delivering at least VPH and 175 mA.
• Be careful to observe the tLOW delay time before powering down the device after blowing each bit.
• Lock the device (only after all other parameters have been pro grammed and validated) to prevent any further programming of the device. B OP Selection Selecting BOP should be done in two stages. First, Try mode should be used to adjust BOP and monitor the output state. Then the optimum BOP is set permanently using Blow mode. Use the BOP Trim Up Counting register to increase the BOP selec- tion by one Magnetic Step Size, StepBOP , increment with each bit field pulse (see figure 8). Use the BOP Trim Down Counting register to decrease the BOP selection by one StepBOP with each bit field pulse (see figure 9). As an aid to programming, when using down-counting method, the A119x automatically inverts the bit field selection (code 0 in down-counting sets the bit field value 111111, and the actual bit field value decreases until code sets bit field value 000000). Note that the release point, BRP , is a value below BOP . The difference is specified by the Hysteresis, BHYS , which is not programmable.

Worcester, Massachusetts 01615-0036 U.S.A. Figure 8. BOP Selection Up-Counting Figure 9. BOP Selection Down-Counting

Worcester, Massachusetts 01615-0036 U.S.A. Figure 10. Programming state diagram Figure 11. Example of Try mode pulse sequence, Register Key = BOP selection down counting Figure 12. Example of Blow mode pulse sequence, Register Key = BOP selection bit field 2 (code 4)

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. The device must be operated below the maximum junction tem- perature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the appli- cation. This section presents a procedure for correlating factors affecting operating T J. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RθJA, is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Ef fective Thermal Conductivity , K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RθJC, is relatively small component of RθJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The ef fect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN (1) Δ T = PD × RθJA (2) TJ = TA + ΔT (3) For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 4 mA, and RθJA = 140 °C/W, then: PD = VCC × ICC = 12 V × 4 mA = 48 mW Δ T = PD × RθJA = 48 mW × 140 °C/W = 7°C TJ = TA + ΔT = 25°C + 7°C = 32°C A worst-case estimate, PD(max), represents the maximum allow- able power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RθJA and TA. Example: Reliability for VCC at TA = 150°C, package UA, using a low-K PCB. Observe the worst-case ratings for the device, specifically: RθJA = 165 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and ICC(max) = 17 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165 °C/W = 91 mW Finally , invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 17 mA = 5 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli- able operation between VCC(est) and VCC(max) requires enhanced RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions.

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A.

0.55 REF

0.25 BSC

0.95 BSC

0.95 1.00 0.70 2.40 A Active Area Depth, 0.28 mm REF B C C B Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Branding scale and appearance at supplier discretion A PCB Layout Reference View Standard Branding Reference View Branded Face N = Last two digits of device part number T = Temperature code NNT 2.90 +0.10 –0.20 4°±4° 8X 10° REF 0.180+0.020 –0.053 0.05 +0.10 –0.05

0.25 MIN

1.91 +0.19 –0.06 2.98 +0.12 –0.08 1.00 ±0.13 0.40 ±0.10 For reference only; not for tooling use (reference DWG-2840). Dimensions in millimeters. Dimensions exclusive of mold flash, gate burrs, and dambar protrusions. Exact case and lead configuration at supplier discretion within limits shown. D Hall element, not to scale D D D1.49 0.96

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package UA, 3-Pin SIP 2 31

1.27 NOM

1.02 MAX 45° 45° C 1.52 ±0.05 B Gate and tie bar burr area A B C Dambar removal protrusion (6X) A D E D E E

1.44 NOM

2.05 NOM

E Active Area Depth, 0.50 mm REF Branding scale and appearance at supplier discretion Hall element (not to scale) For reference only; not for tooling use (reference DWG-9065). Dimensions in millimeters. Dimensions exclusive of mold flash, gate burrs, and dambar protrusions. Exact case and lead configuration at supplier discretion within limits shown. Standard Branding Reference View NNN Mold Ejector Pin Indent = Supplier emblem N = Last three digits of device part number 0.41 +0.03 –0.06 0.43 +0.05 –0.07 14.99 ±0.25 4.09 +0.08 –0.05 3.02 +0.08 –0.05

0.79 REF

10° Branded Face

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package UB, 2-Pin SIP Mold Ejector Pin Indent

0.25 REF

0.30 REF

4 X 2.50 REF 4 X 7.37 REF 4 X 0.85 REF 4 X 0.85 REF

0.38 REF

45° 0.85 ±0.07 0.85 ±0.07 B

4 X 10°

A Branded Face 0.25 +0.07 –0.03 0.42 ±0.10 4.00 4.00 1.00 ±0.10 1.80 ±0.10

2.54 REF

12.20 ±0.10 1.50 ±0.05 1.50 ±0.05 A B C C DB randing scale and appearance at supplier discretion F F E E 1.75 2.00 E E Dambar removal protrusion (8X) Gate and tie bar burr area Active Area Depth, 0.38 mm REF Hall element; not to scale Thermoplastic Molded Lead Bar for alignment during shipment 4.00 +0.06 –0.05 +0.06 –0.07 1.80+0.06 –0.07 +0.06 –0.05 D = Supplier emblem = Last three digits of device part number = Last 2 digits of year of manufacture = Week of manufacture = Lot number N Y W L Standard Branding Reference View YYWW LLLL NNN For reference only; not for tooling use (reference DWG-9070). Dimensions in millimeters. Dimensions exclusive of mold flash, gate burrs, and dambar protrusions. Exact case and lead configuration at supplier discretion within limits shown.

Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches A119x and A119x-F Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. For the latest version of this document, visit our website: www.allegromicro.com

Revision History

Revision Revision Date Description of Revision

4 May 24, 2013 Update application information

5 September 21, 2015 Added AEC-Q100 qualification under Features

6 February 3, 2016 Added UB package option; added -F part option. 7 February 25, 2016 Removed A1190-F part option. Copyright ©2016, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.