A1174 ALLEGRO | Alldatasheet
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Technical content
Description
The A1174 is a micro-power, Hall-effect latch for use in portable devices that employ rotational detection systems, and have a power supply voltage between 1.65 and 3.5 V . The device has a single push-pull output structure and requires no external pull-up resistor for reliable operation. When a sufficient positive magnetic field is present on the device, the device output transitions to the low state and is latched in this state until a negative field of sufficient strength latches the device output into the high state. The latched output is ideal when using multiple sensors in rotational speed and direction sensing systems (for example, track ball and scroll bar systems in portable devices). The device includes an innovative clocking scheme that satisfies the micro-power needs of almost any application, including track balls for PDAs and cell phones. Using the EXTERNAL_CLK and DUAL_CLK pins as described in this datasheet, the device can be set into various working modes. In Dual Clock mode, the device switches between predefined slow and fast sampling rates. The average current consumption of the device is extremely low when rotation is not detected. In External Clock mode, the user sets the clock rate for the device to achieve the required on and off times for controlling average power. This user-determined clocking also helps to A1174-DS Features and Benefits ▪ Micro-power latch operation ▪ 1.65 to 3.5 V battery operation ▪ Push-pull output eliminates the need for an external pull- up resistor ▪ User configured, internally or externally controlled sample and sleep periods ▫ Floating the two clock pins results in the use of a fixed sampling clock internal to the sensor ▫ Toggling the clock pins allows the user to control the sampling and sleep times of the sensor for extreme low power operation ▪ External control of the clock pins allows the user to implement synchronous sampling of multiple sensors in direction detection systems ▪ Chopper stabilization ▫ Superior temperature stability ▫ Extremely low switchpoint drift ▫ Insensitive to physical stress ▪ Solid state reliability ▪ Small size Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications Continued on the next page… Package: 6-contact MLP/DFN (suffix EW) Not to scale A1174 1.5 mm × 2 mm × 0.40 mm Magnetic Flux Density A1174 Output On OffOffOn On BOP BOP BOP BRPBRPBRP Figure 1. Timing diagram for output switching
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications A1174 2Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A. Description (continued) VDD NC VOUT DUAL_CLK GND EXTERNAL_CLK PAD Pin-out Diagram Terminal List Number Name Function
1 VDD Supply Voltage
2 NC No connect
3 VOUT Output
4 EXTERNAL_CLK In combination with DUAL_CLK , allows external control of the device
sampling period and duty cycle
5 GND Ground
6 DUAL_CLK In combination with EXTERNAL_CLK , drives the part in Dual Clock mode
Part Number Packing* A1174EEWLT-T 3000 pieces per 7-inch reel *Contact Allegro® for additional packing options achieve synchronous clocking of multiple devices. This allows a defined phase relationship between the output transitions of each device in direction detection systems. Improved stability is made possible through dynamic offset cancellation using chopper stabilization, which reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. Solid state reliability is provided by integrating, on a single silicon chip, a Hall-voltage generator, a small-signal amplifier, chopper stabilization, a latch, and a MOSFET output. The device package is a 6-contact, 1.5 mm × 2 mm, 0.40 mm nominal overall height MLP/DFN, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Forward Supply Voltage V DD 5.0 V Reverse Supply Voltage V RDD –0.3 V Output Voltage V OUT 5.0 V Reverse Output Voltage V ROUT –0.3 V EXTERNAL_CLK and DUAL_CLK Pins Input Voltage VIN 5.0 V EXTERNAL_CLK and DUAL_CLK Pins Reverse Input Voltage VRIN –0.3 V Continuous Output Current IOUT(sink) –1 mA IOUT(source) 1m A Magnetic Flux Density* B Unlimited G Operating Ambient Temperature T A Range E –40 to 85 °C Maximum Junction Temperature T J(MAX) 165 °C Storage Temperature T stg –65 to 170 °C *1G = 0.1 mT (millitesla) (Top View)
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications A1174 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Functional Block Diagram VDD GND Amp VOUT Input Decoder Sample Control Block Internal Clock Latch EXTERNAL_CLK DUAL_CLK
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications A1174 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Operating Characteristics Valid over full operating voltage and ambient temperature ranges (unless otherwise specified) Characteristic Symbol Test Conditions Min. Typ. 1 Max. Unit
Electrical Characteristics
TA = 25°C 1.65 – 3.5 V Output On Voltage VOUT(SAT) NMOS on, IOUT = 1 mA – 100 300 mV VOUT(HIGH) PMOS on, IOUT = 1 mA V DD – 300 V DD – 100 – mV Supply Current IDD(EN) Chip in awake state (enabled) – – 2.0 mA IDD(DIS) Chip in sleep state (disabled) – – 8.0 μA IDD(AV) Normal Clock mode, VDD = 2.5 V – – 71 μA Normal Clock mode, VDD = 3.0 V – – 82 μA Internal Chopper Stabilization Clock Frequency f C – 200 – kHz EXTERNAL_CLK and DUAL_CLK Pins Input Current I IN VEXTERNAL_CLK = VDD, VDUAL_CLK = VDD – 0.5 – mA EXTERNAL_CLK and DUAL_CLK Pins Leakage Current I OFF VEXTERNAL_CLK = 0 V, VDUAL_CLK = 0 V – 0.02 – μA Supply Slew Rate3 SR t OFF = 100 ms 0.1 – – V/ms Normal Clock Mode Characteristics4 Normal Mode Awake Duration t awake_norm –2 5 3 8 m s Normal Mode Period t period_norm – 0.7 1.05 ms External Clock Mode Characteristics4 EXTERNAL_CLK and DUAL_CLK Pins Threshold Vth(HIGH) – – 0.75 × V DD V Vth(LOW) 0.25 × VDD –– V External Clock Mode Awake Duration t awake_ext VEXTERNAL_CLK > Vth(HIGH) 38 – – ms External Clock Mode Period t period_ext VEXTERNAL_CLK > Vth(HIGH) 80 – – ms State Transition Delay5 tdelay_ext –2 5 3 8 m s Dual Clock Mode Characteristics4 Dual Clock Mode Awake Duration t awake_dual –2 5 3 8 m s Dual Clock Mode Fast Sampling Period t period_fast – 8 × tawake_dual –m s Dual Clock Mode Slow Sampling Period t period_slow –2 8– m s Dual Clock Mode Timeout6 ttimeout – 100 × tperiod_slow –m s Magnetic Characteristics2 Operate Point B OP South pole to device branded side 5 36 55 G Release Point B RP North pole to device branded side –55 –36 –5 G Hysteresis B HYS BOP – BRP –7 2 1 1 0 G 1Typical values are at TA = 25°C and VDD = 2.75 V. Performance may vary for individual units, within the specified maximum and minimum limits. 2Magnetic operate and release points vary with supply voltage. 3If the device power supply is chopped, power-up slew rate dVDD / dt has to be adjusted to ensure correct functioning of the device. tOFF is the time of the power cycle when VDD < VDD(min). 4Defined in the Functional Description section of this datasheet. 5Time between external clock transition and resulting transition of the device between the awake and sleep states. See Functional Description section. 6If no output transition is detected during the timeout interval, the device goes back into slow sampling. See Functional Description section.
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications A1174 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Characteristic Performance Saturation Voltage versus Supply Voltage 100 150 200 250 300 VDD (V) VOUT(SAT) (mV) 1.0 2.0 3.0 4.0 1.0 2.0 3.0 4.0 Saturation Voltage versus Temperature 100 150 200 250 300 -60 -40 -20 0 20 40 60 80 100 TA (°C) VOUT(SAT) (mV) Average Supply Current versus Temperature 100 -60 -40 -20 0 20 40 60 80 100 T A (°C) IDD(AV) (μA) Average Supply Current versus Supply Voltage 100 1.5 2.5 3.5 V DD (V) IDD(AV) (μA) Normal Mode Period versus Temperature 100 200 300 400 500 600 700 800 900 1000 -60 -40 -20 0 20 40 60 80 100 TA (°C) tperiod (μs) Normal Mode Period versus Supply Voltage 100 200 300 400 500 600 700 800 900 1000 1.5 2.5 3.5 V DD (V) tperiod (μs) 1.65 1.8 2.5 2.75 3.0 3.5 1.65 1.8 2.5 3.0 3.5 VDD (V) IOUT = 1 mA VDD (V) TA (°C) 1.65 1.8 2.5 3.0 3.5 VDD (V) IOUT = 1 mA 85°C -40°C 25°C TA (°C) 85°C -40°C 25°C TA (°C) 85°C -40°C 25°C
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications A1174 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Dual Mode Fast Period versus Temperature 100 150 200 250 300 350 400 -60 -40 -20 0 20 40 60 80 100 TA (°C) tfast_period (μs) tfast_period (μs) Dual Mode Fast Period versus Supply Voltage 100 150 200 250 300 350 400 VDD (V) Dual Mode Slow Period versus Temperature -60 -40 -20 0 20 40 60 80 100 TA (°C) t slow_period (ms) t slow_period (ms) Dual Mode Slow Period versus Supply Voltage VDD (V) Operate Point versus Temperature -60 -40 -20 0 20 40 60 80 100 TA (°C) B OP (G) Operate Point versus Supply Voltage VCC (V) BOP (G) 1.65 1.8 2.5 3.0 3.5 3.5 1.65 1.8 2.5 3.0 3.5 VDD (V) VDD (V) TA (°C) 85°C -40°C 25°C TA (°C) 85°C -40°C 25°C TA (°C) 85°C -40°C 25°C 1.65 1.8 2.5 2.75 3.0 3.5 VDD (V)
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications A1174 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Release Point versus Temperature -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 BRP(G) Release Point versus Supply Voltage -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 BRP (G) Hysteresis versus Temperature 100 110 -60 -40 -20 0 20 40 60 80 100 T A (°C) -60 -40 -20 0 20 40 60 80 100 TA (°C) BHYS(G) Hysteresis versus Supply Voltage 100 110BHYS (G) VDD (V) VDD (V) 1.65 1.8 2.5 2.75 3.0 3.5 VDD (V) TA (°C) 1.65 1.8 2.5 2.75 3.0 3.5 VDD (V) 85°C -40°C 25°C TA (°C) 85°C -40°C 25°C
Worcester, Massachusetts 01615-0036 U.S.A. the presence of external mechanical vibration and electrical noise. (off) if the last crossed switchpoint is BRP . state is attained after the first excursion beyond BOP or BRP .
- powering all circuits in the chip and latching the device output state at the end of awake state periods, and
- turning off the bias current to most circuits in the chip and maintaining the device output state through sleep state periods. This is illustrated in figure 3. The awake state duration, tawake_x , is common in all defined modes of operation. The sleep state duration is set at a longer duration than the awake period in order to conserve power. During the sleep state, current consumption is insignificant (equal to I DD(DIS)), but the device output does not switch in response to changing incident magnetic fields. The device shows maximum current consumption, IDD(EN) , dur- ing the awake state and minimal current consumption, IDD(DIS) , during the sleep state. Average current, IDD(A V) , for micro-power operation is derived from following formula: IDD(AV) .IDD(EN) × tawake_x + IDD(DIS) × tsleep_x = tperiod_x Three micro-power control modes are available:
- Normal Clock mode
- External Clock mode
- Dual Clock mode Selection of clock mode is determined by the configuration of the EXTERNAL_CLK pin and the DUAL_CLK pin, and applied voltages as illustrated in figure 4 and table 1. Normal Clock Mode When both device clock pins are left floating or are grounded, the internal timing circuitry activates the sensor for t awake_norm and deactivates it for the remainder, tsleep , of the duty cycle period, tperiod_norm. The short awake time
Figure 2. Device output switching logic Figure 3. Micro-power behavior of the device
Worcester, Massachusetts 01615-0036 U.S.A. sleep , is latched in the last sampled state. output state determined during the prior awake state. order to update the device output state. Figure 5. External Clock mode clocking; tdelay_ext corresponding to the Table 1. Clock Mode Selection Options Figure 4. Clock mode selection algorithm; determined by clock pins
10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. sleep_fast , of 8 × tawake_dual. conserve battery life in handheld devices. rapidly changing magnetic field is shown in figure 8. Figure 6. Dual Clock mode operation algorithm
11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Figure 8. Device output response in Dual Clock mode with a rapid change of the Figure 7. Device output response in Dual Clock mode with no change of the
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications A1174 12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A.
Application Information
It is strongly recommended that an external bypass capacitor be connected (in close proximity to the Hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chopper stabilization technique (0.1 μF is a typical value). Additionally, it is recommended that, when possible, pins be tied to either the VDD pin or ground potential in order to improve the EMC performance of the device. However, it is feasible to float the EXTERNAL_CLK and DUAL_CLK pins in the application. In the case where these pins are floating, care should be taken to locate the device as far as possible from system antennas and transceivers. The schematics on this page represent typical application circuits. (A) Device is working in Normal Clock mode. Power consump- tion is determined by device internal clock. (B) Device is working in Dual Clock mode. Power consumption is determined by device internal clock; frequent usage of device in fast sampling state. (C) Device is working in External Clock mode; externally-con- trolled power consumption. (D) Device is working in External Clock mode; high power con- sumption. A1174DUAL_CLK VDD GND VOUT EXTERNAL_CLK Vbat Cbypass A1174DUAL_CLK VDD GND VOUT EXTERNAL_CLK Vbat Cbypass A1174 DUAL_CLK VDD GND VOUT EXTERNAL_CLK Vbat Cbypass A1174 DUAL_CLK VDD GND VOUT EXTERNAL_CLK Vbat Cbypass (A) (B) (C) (D)
Ultrasensitive Hall Effect Latch with Internally or Externally Controlled Sample and Sleep Periods for Track Ball and Scroll Wheel Applications A1174 13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. F F F SEATING PLANE 0.38 0.50 0.25 0.70 1.10 1.10 0.30 0.70 1.575 0.500.15 1.25 0.325 0.325 2.00 1.00 0.74 1.50 C0.08 7X C A A Terminal #1 mark area Active Area Depth B F Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) All dimensions nominal, not for tooling use (similar to JEDEC Type 1, MO-229”X2”BCD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C E Reference land pattern layout (reference IPC7351 SON50P200X200X80-7-M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) E Hall element (not to scale) B PCB Layout Reference ViewC D D Coplanarity includes exposed thermal pad and terminals Copyright ©2008, Allegro MicroSystems, Inc. The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Package EW 6-Contact MLP/DFN