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User's Guide SLAU145 December 2004 ADS78/8505EVM User's Guide

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Connector, Pinnout of the Digital Control Connector, Pinout of the Power Supply Connector, Factory Default Jumper Locations Bill of Materials EVM Compatible Device Data Sheets, Users Guides and Additional Resources The ADS7805 and ADS8505 are complete 16-bit analog-to-digital (A/D) using state-of-the-art CMOS structures. They contain a complete 16-bit, capacitor-based, successive approximation register (SAR) A/D with sample-and-hold, reference, internal conversion clock, and a parallel data interface with 3-state output drivers. The evaluation module (EVM) is available with either the ADS7805 or ADS8505 installed. The EVM can also accommodate the 12-bit ADS7804 simply removing and replacing the installed device. Samples of the ADS7804 can be obtained through the sample program at Texas Instruments. See the ADS7804 Product Folder for details. Full-Featured Evaluation Board for the ADS7804, ADS7805 or ADS8505, parallel Analog to Digital Converters Industry Standard V Analog Input Range Built in reference Parallel Interface with 3-state output drivers Compatible with the 5-6K Interface Board for use with a variety of DSP Starter Kits as well as the HPA449 from SoftBaugh, Inc. (www.softbaugh.com). Field Programmable Gate Array (FPGA) users can evaluate the ADS78/8505EVM by obtaining the Texas Instruments Analog Adapter Kit from Avnet Design Services (www.em.avnet.com). ADS78/8505EVM User's Guide SLAU145 December 2004

www.ti.com Analog Interface 2.1 Optional Amplifier Input Digital Interface Analog Interface For maximum flexibility, the ADS78/8505EVM is designed for easy interfacing to multiple analog sources. Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient ten-pin dual row header/socket combination at J1. This header/socket provides access to the analog input pins of the ADC. Please consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector options. Table shows the pin out of the analog input connector, J1. Table Pinout of the Analog Input Connector, Pin Number Signal

Description

J1.2 thru Analog To accommodate EVM Stacking using the SN74AHC138 address decoder, feeds jumper W1. Up to J1.16 (even) Input four converters can used at the same time. J1.20 REF(+)J External reference source input, accessible through W4. J1.15 REFOUT Optional connection via W4. Provides external AFE circuitry with REFOUT bias voltage. J1.1- J1.19 AGND Analog ground connections. Note J1.15 is used for REFOUT connections to external AFE circuitry. (odd) The analog front-end (AFE) circuitry found on the EVM consists of a simple RC filter. When used in combination with the 5-6K Interface Board, the circuits found on both DAP Signal Conditioning Boards (see SLAU105 provide the level shifting and amplifier configurations to realize single ended or bi-polar mode operation of the analog-to-digital converter installed on the EVM. Jumper provides access to an optional amplifier/buffer circuit on the front end of the data converter. Component can be installed at the user's option with any standard pin SOIC single amplifier component. The amplifier circuit is connected to the VA terminals for split supply operation. If single supply amplifiers are used, the VA (J3 pin can be tied to analog ground (J3 pin 6). The footprint for common 4mm trim pots (see component R7) is provided as an offset adjustment for precision amplifiers such as the OPA228. When used in conjunction with the 5-6K Interface Board, please be aware that the VA supply is common to all power connectors (JP1 through JP6). Shorting the VA supply to ground on the ADS78/8505EVM is possible only if it is not used elsewhere on the interface board. The active low CS pin is connected to W8. This pin can be controlled through the SN74AHC138 address decoder at U5. For standalone operation, a 10K resistor to ground on the CS pin is provided. Completely removing the shunt at ensures this pin is held low. The converted data output from the ADC is applied to U3, an SN74ALVCH16245. This 16-bit wide buffer can be configured for 3.3 or 5.0V systems by providing the device with the appropriate IO voltage via (see EVM silkscreen and schematic for details). The SN74ALVCH16245 inputs, making it an ideal level shifting buffer for processors. The entire bit data output is presented to pins 1-31 (odd). is a header/socket combination which acts as a pass through connector for easy data monitoring and/or board stacking when multiple devices share the data bus. The BUSY signal is fed through a single gate buffer, an SN74AHC1G125, which is also supplied by the IO voltage selected at W3. The BUSY signal can be used as an interrupt source to the host processor, indicating the converted data is ready to be accessed through the parallel data buffer. The remaining digital control lines are discussed in the following section. ADS78/8505EVM User's Guide SLAU145 December 2004

www.ti.com 3.1 Digital Control via J5, and 3.2 Additional Digital Control and Monitoring Digital Interface provides the parallel data bus control signals used on the various interface boards mentioned at the beginning of this document. Two single "OR" gates (U4 and SN74AHC1G32) are provided to allow several methods of accessing the converted analog signal. in conjunction with three pin jumper (shunt pins 1-2) allows the user to write a conversion command to the R/C pin of the data converter. When a valid chip select signal is applied to the ADC's CS pin, the host processors write strobe WR /(R/W)) can be used to initiate a conversion cycle. This function can be bypassed by placing a shunt jumper on pins 3-4. For stand alone operation, the CS pin can be held low by removing the shunt at and applying the R/C strobe to J5, pin 17. The shunt on needs to be moved to cover pins 2-3 in this case. The signal on pin connects to one of the timer outputs of the host DSP when this EVM is used with the 5-6K Interface Board. DSK users could set a periodic function in the DSP to initiate the conversion cycle if desired. in conjunction with (an SN74ALVCH16245) provides a means to isolate the ADC from the external data bus. When a valid chip select is applied to the ADC, the host processors read strobe RD enables the outputs of the data buffer. This function can be bypassed by placing a shunt jumper on pins 5-6. Table Pinnout of the Digital Control Connector, Pin Signal Function DC_CSx EVM Address Decoder Enable. Can be tied low by placing a shunt on pins 1-2. /WR(R/W) Host processor active low write strobe /RD Host processor active low read strobe EVM_A0 used in conjunction with EVM_A1 and EVM_A2 to determine the ADC address on the data bus. EVM_A1 used in conjunction with EVM_A0 and EVM_A2 to determine the ADC address on the data bus. EVM_A2 used in conjunction with EVM_A0 and EVM_A1 to determine the ADC address on the data bus. EVM_A3 connects to the enable of the address decoder U5. This pin must be high for address decoding operations. EVM_A4 can be used to control BYTE mode data access TOUT When is shunted pins 2-3, the signal applied to this pin can be used to initiate a conversion if the ADC has been properly chip selected. /INTB the buffered BUSY signal output of the ADC. Can provide the host processor with an interrupt source. 2-20 (even) Digital Ground Jumper is provided along with a k Ω resistor (R5) allowing the data converter installed at position to operate in BYTE mode. BYTE access requires two read accesses to the ADC in order to get the full 16-bit data output, once with BYTE high and again with BYTE low. When BYTE is low (default, installed) the data is presented with the LS Byte on pins 22-15 and the MS Byte on pins 13-6. When BYTE is high, the LS Byte and MS Byte swap. An eight bit processor can be configured to take LS or MS data first using either side of the chip, simplifying board layout. The digital control lines and parallel data bus can be monitored directly from and J4. Each of these connectors provides a complementary digital ground pin and can easily accomodata logic analysers or oscilloscopes. Test points through provide access to analog and digital ground as well as the applied power supply voltages. Test point can be used to monitor the reference voltage. ADS78/8505EVM User's Guide SLAU145 December 2004

www.ti.com Power Supplies 4.1 Reference Voltage control via Power Supplies The ADS78/8505EVM board requires +5V DC for both the analog and digital sections of the ADC. Power to the ADC is sourced from pin and pin (+5VA and +5VD see table below). The digital I/O voltage can be set for +3.3V or +5.0V depending on the needs of the host processor driving the ADC. Note: VDIG must be less than or equal to VANA. Table shows the pin out of J3: Table Pinout of the Power Supply Connector, Signal Pin Number Signal +VA -VA +5VA Unused DGND AGND Unused Unused +3.3VD +5VD The EVM is configured with two small LC filters that take the voltage applied to pin and splits it into +5VA and +5VD nodes. For stand alone operation, power sources can be applied via various test points located on the EVM (VANA to TP2 and VDIG to TP4) provided that inductor is removed. Refer to the schematic at the end of this document for details. The optional amplifier located at position (user supplied) can be powered through pins and See the earlier discussion about the power supply restrictions in section 1.2 of this manual. Note: While filters are provided for all power supply inputs, optimal performance of the EVM requires a clean, well-regulated power source. The ADS78/8505 is normally configured to use its internal reference. Jumper provides various options to allow the EVM user to send the reference voltage off board to external amplifier circuits (W4 pins 7-8, default state). An external reference source applied to pin can be sent to the ADC by moving the shunt at to pins 1-2. An on board trim pot is provided at R8, and can be used with a shunt jumper placed on pins 3-4. Finally, an on-board fixed 2.5V reference from (REF3125) can be applied to the ADC by moving the shunt at to cover pins 5-6. ADS78/8505EVM User's Guide SLAU145 December 2004

www.ti.com EVM Operation EVM Operation The maximum analog input swing is +/-10Vpp. Offset trim can be accomplished on board via R3. Single amplifier in an industry standard SOIC package can be installed to do on board signal conditioning if desired. Please refer to Section of Op Amps for Everyone (Doc. No. SLOD006) for information on various circuit applications. Once power is applied to the EVM, the analog input source can be connected directly to (top or bottom side) or through optional amplifier and signal conditioning modules using the 5-6K Interface Board or HPA449. Jumper allows the EVM user to choose which analog signal applied to is directed to the input of the ADC, providing the ability to stack up to four ADS78/8505EVM's using the address decoder found at U5. The digital control signals can be applied directly to (top or bottom side). The ADS78/8505EVM can also be connected directly to the 5-6K Interface Board for use with a variety of C5000 and C6000 series DSP Starter Kits (DSK). The analog and digital input connectors are designed to allow pattern generators and/or logic analyzers to be connected to the EVM using standard ribbon type cables on 0.1" centers. No specific evaluation software is provided with this EVM, however, code examples are available that show how to use this EVM with a variety of digital signal processors from Texas Instruments Incorporated. Check the product folders or send e-mail to dataconvapps@list.ti.com for a listing of available code examples. The EVM Gerber files are available on request. Table shows the factory default jumper locations for the ADS78/8505EVM. Table Factory Default Jumper Locations Jumper Function Default Condition Controls application of the applied analog signal to VIN Controls the state of BYTE Closed Controls application of the VIO (3.3 (default) or 5V) Controls the application of the reference voltage Controls the source of the conversion start signal applied to the ADC's R/C pin Controls the application of optional signal conditioning circuitry Controls the application of the voltage at the CAP pin or offest trim through to 33.2 k Ω resistor R4. Determines which decoded address the ADC will respond to. ADS78/8505EVM User's Guide SLAU145 December 2004

www.ti.com EVM Bill of Materials and Schematic EVM Bill of Materials and Schematic Table contains a complete Bill of Materials for the ADS78/8505EVM. The schematic diagram is also provided for reference. Table Bill of Materials Designators Mfg. Part Number C10 0.1uF Ceramic, 0805, X7R, 25V TDK C2012X7R1E104K C15 C19 C18 C27 C12 C20 C21 0.01uF Ceramic, 0805, X7R, 50V TDK C2012X7R1H103K C25 10uF Tantalum, A case, 10V Panasonic ECS-T1AY106R C16 2.2uF Ceramic, 0805, X5R, 10V TDK C2012X5R1A225K C11 C13 C22 10uF Ceramic, 0805, X5R, 10V Murata GRM21BR61A106KE19L C14 0.47uF Ceramic, 0805, X7R, 16V TDK C2012X7R1C474K C17 2.2nF Ceramic, 0805, X7R, 50V TDK C2012X7R1H223K C26 C28 100 pF Ceramic, C0G, 50V TDK C2012C0G1H101K (top side) pin, dual row, SMTheader (20 pos.) Samtec TSM-110-01-T-DV-P (bottom side) pin, dual row, SMT socket (20 pos.) Samtec SSW-110-22-F-D-VS-K (top side) pin, dual row, SMT header (10 Pos.) Samtec TSM-105-01-T-DV-P (bottom side) pin, dual row, SMT socket (10 Pos.) Samtec SSW-105-22-F-D-VS-K (top side) Pin, Dual Row, SMT Header (32 Samtec TSM-116-01-T-DV-P Pos.) (bottom side) Pin, Dual Row, SMT socket (32 Samtec SSW-116-22-F-D-VS-K Pos.) µ H inductor, SMT, 1608 series Inductors, Inc. CTDS1608C-153 k Ω 0805, Yageo America 9C08052A1002JLHFT Ω 0805, Yageo America 9C08052A33R0JLHFT k Ω SMT Trim Pot, mm Bourns 3214W-1-503E 33.2 k Ω 0805, Yageo America 9C08052A3322FKHFT 576 k Ω 0805, Yageo America 9C08052A5763FKHFT Ω 0805, Yageo America 9C08052A0R00JLHFT R10, R11 200 Ω 0805, Yageo America 9C08052A1002JLHFT TP2 TP4 TP5 Red test point loop Keystone 5000 TP1 TP3 Black test point loop Keystone 5001 ADS7805 or ADS8505 TI ADS7805U or ADS8505U REF3125 TI REF3125AIDBZT SN74ALVCH15245 TI SN74ALVCH15245DL SN74AHC1G32 TI SN74AHC1G32DBVT SN74AHC138 TI SN74AHC138D OPA353 TI OPA353NA Not Installed TI Single Op Amp SOIC pin dual row, mm header (16 pos) Samtec TMM-108-02-L-D pin 0.1" header Samtec TSW-102-07-L-S pin 0.1" header Samtec TSW-103-07-L-S Pin, dual row header pos) Samtec TSW-104-07-L-D pin, dual row, TH header pos.) Samtec TSW-103-07-L-D ADS78/8505EVM User's Guide SLAU145 December 2004

A B C DD C B A ti 12500 TI Blvd. Dallas, Texas 75243 Title: SHEET: OF:FILE: SIZE: DATE: REV:22-Nov-2004

Revision History

Drawn By: Engineer: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 +5VA EXT_REFIN TP2 TP3 TP1 5Vd AGNDDGND Tom Hendrick Tom Hendrick B ADS7805/8505 Evaluation Module Schematic A 11EDGE #6465116 A Initial Release TH 5Va REFOUT 10K 5Vd +5VA C18 0.1uF 5Va 5 2 OPA353N VIN1 GND3 OUT 2 REF3125 C14 0.47uF 5Va C22 10uF EVM_REFIN 0.1uF C16 2.2uF 0.01uF 5Va C12 0.01uF 0.1uF 5Vd 1 2 3 4 5 6 7 8 50KC13 10uF 5Va R8 10K ADJ_REFIN 50K C11 10uF 5Va 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EVM_IN_0 EVM_IN_1 EVM_IN_2 EVM_IN_3 EVM_IN_4 EVM_IN_5 EVM_IN_6 EVM_IN_7 EVM_IN_0 EVM_IN_1 EVM_IN_2 EVM_IN_3 EVM_IN_4 EVM_IN_5 EVM_IN_6 EVM_IN_7 ADC_ANALOG_IN 7 4 C17 2.2nF R10 200 ohm +VA -VA +VA -VA C20 10nF C21 10nF

0 Ohm

/BUSY 26 Vana27 BYTE 23 /CS 25 R/C 24 Vdig28 D10 D11 D12 D13 D14 D15 ADS8505 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D10 D11 D12 D13 D14 D15 D10 D11 D12 D13 D14 D15 A 1 B 2 C 3 G1 6 G2A 4 G2B 5 Y015 Y114 Y213 Y312 Y411 Y510 Y69 Y77 VCC16 GND 8 SN74AHC138 EVM_A0 EVM_A1 EVM_A2 EVM_A3 /WR(R/W) /RD A B C TOUT /INTB 10K /RD_ADC /CS /CS ADC_R/C /CS /RD_ADC 5VD 5 3 SN74AHC1G32 5VD 2.2uF 33.2K 5 3 SN74AHC1G32 EVM_A0 EVM_A1 EVM_A2 EVM_A3 DC_CSx DC_CSx EVM_A4 EVM_A4 5VD /CS /WR(R/W) TOUT ADC_R/C /RD VIO /INT EVM_A4 DIR11 1B12 1B23 1B35 1B46 1A5 41 1A6 40 1A7 38 1A8 37 1A1 47 1A2 46 1A3 44 1A4 43 1B58 1B69 1B711 1B812 VIO DGND /OE148 /OE225 DIR224 2A1 36 2A2 35 2A3 33 2A4 32 2A5 30 2A6 29 2A7 27 2A8 26 2B113 2B214 2B316 2B417 2B519 2B620 2B722 2B823 SN74ALVCH16245 C15 0.1uF 0.1uF 0.1uF C19 0.1uF C10 0.1uF 0.1uF + C6 + C4 C23 C24 VIO SN74AHC1G125 VIO /INT /INTB VIO + C25 TP4 C26 100pF C27 0.1uF +3.3VD +5.0VD C28 100pF R11 200 ohm TP5

www.ti.com Related Documentation from Texas Instruments Related Documentation from Texas Instruments Table EVM Compatible Device Data Sheets, Users Guides and Additional Resources Data Sheet Literature Number ADS7804 SBAS019 ADS7805 SBAS020 ADS8505 SLAS180 Users Guides Literatuare Number 5-6K Interface Board SLAU104 DAP Signal Conditioning Boards SLAU105 Additional Resources Literature Number Op Amps for Everyone SLOD006 Controlling the ADS7805 With TMS320 Series SLAA229 DSPs ADS78/8505EVM User's Guide SLAU145 December 2004

a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive. Should this evaluation kit not meet the specifications indicated in the EVM User's Guide, the kit may be returned within days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE Liable to the other FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive TI assumes no liability for

applications

assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the EVM User's Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact the TI application engineer. Persons handling the product must have electronics training and observe good laboratory practice standards. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of -10 V to +10 V and the output voltage range of V to Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than The EVM is designed to operate properly with certain components above C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated

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