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Data Sheet: Technical Data Document Number: MC9S08SE8 Rev. 4, 4/2015 © Freescale Semiconductor, Inc., 2008-2009, 2015. All rights reserved. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MC9S08SE8 Features:
- 8-Bit HCS08 Central Processor Unit (CPU) – 20 MHz HCS08 CPU (central processor unit) – 10 MHz internal bus frequency – HC08 instruction set with added BGND – Support for up to 32 interrupt/reset sources
- O n - C h i p M e m o r y – Up to 8 KB of on-chip in-circuit programmable flash memory with block protection and security options – Up to 512 bytes of on-chip RAM
- Power-Saving Modes – Wait plus two stops
- Clock Source Options – Oscillator (XOSC) — Loop- control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS ) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1 MHz to 10 MHz.
- System Protection – Optional computer operating properly (COP) reset with option to run from independent 1 kHz internal clock source or the bus clock – Low v oltage detection – Illegal opcode detection with reset – Illegal address detection with reset
- Development Support – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging
- Peripherals – SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge – ADC — 10-channel, 10-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; runs in stop3 – TPMx — One 2-channel (TPM1) and one 1-channel (TPM2) 16-bit timer/pulse-width modulator (TPM) modules; selectable input capture, output compare, and edge-aligned PWM capability on each channel; timer module may be configured for buffered, centered PWM (CPWM) on all channels – KBI — 8-pin keyboard interrupt module – RTC — Real-time counter with binary- or decimal-based prescaler
- Input/Output – Software selectable pullups on ports when used as inputs – Software selectable slew rate control on ports when used as outputs – Software selectable drive stre ngth on ports when used as outputs – Master reset pin and power-on reset (POR) – Internal pullup on RESET , IRQ, and BKGD/MS pins to reduce customer system cost
- Package Options – 28-pin PDIP – 28-pin SOIC – 16-pin TSSOP MC9S08SE8 Series Covers: MC9S08SE8 MC9S08SE4 28-Pin SOIC Case 751F 16-Pin TSSOP Case 948F-01 28-Pin PDIP Case 710-02 TBD
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor2 Table of Contents
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: freescale.com The following revision history table summarizes changes contained in this document. Revision Date Description of Changes 1 10/8/2008 Initial public released. 2 1/16/2009 In Table 8, added the Max. of S2IDD and S3IDD in 0–105 °C; changed the Max. of S2IDD and S3IDD in 0–85 °C; changed the typical of S2IDD and S3IDD; changed the S23IDDRTI to P . 3 4/7/2009 Added |I OZTOT| in the Table 7. Changed VDDAD to VDDA, VSSAD to VSSA. Updated Table 9, Table 10, Table 11, and Table 12. Updated Figure 13 and Figure 14. 4 4/10/2015 Updated Table 9. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08SE8RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
1 MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9S08SE8 series MCUs. Figure 1. MC9S08SE8 Series Block Diagram
20 MHz INTERNAL CLOCK
1 MHz to 16 MHz
When PTA4 is configured as BKGD, pin is bi-directional. For the 16-pin package: VSSA/VREFL and VDDA/VREFH are double bonded to VSS and VDD respectively.
2 Pin Assignments
This chapter shows the pin assignments in the packages available for the MC9S08SE8 series. Table 1. Pin Availability by Package Pin-Count
84 V SS
1 TPM1 pins can be remapped to PTA7, PTA6 and PTA1,PTA0
1 ADP1
MC9S08SE8 Series MCU Data Sheet, Rev. 4
Electrical Characteristics
3 Electrical Characteristics
This chapter contains electrical and timing specifications.
3.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate.
3.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. sample size across process variations. D Those parameters are derived mainly from simulations.
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 7
3.3 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 3. Absolute Maximum Ratings voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD.
3 Power supply must maintain regulation within operating VDD range during instantaneous and
Table 4. Thermal Characteristics
MC9S08SE8 Series MCU Data Sheet, Rev. 4 The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. 1 Where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user-determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273°C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3 Where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
3.4 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 5. ESD and Latch-up Test Conditions
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 9
3.5 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics. Latch-up Minimum input voltage limit — –2.5 V Maximum input voltage limit — 7.5 V Table 6. ESD and Latch-up Protection Characteristics
1 Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
1 Human body model (HBM) V HBM ±2000 — V
2 Machine model (MM) V MM ±200 — V
3 Charge device model (CDM) V CDM ±500 — V
4 Latch-up current at T A = 125 °CI LAT ±100 — mA
Table 7. DC Characteristics
5 V, ILoad = –2 mA
5 V, I
3 V, ILoad = –3 mA
5 V, ILoad = 10 mA
3 V, ILoad = 3 mA
5 V, ILoad = 2 mA
Table 5. ESD and Latch-up Test Conditions (continued)
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Output low current — Max total I OL for all ports 5 V 3 V IOLT — 100 mA 6 P Input high voltage; all digital inputs V IH 0.65 × VDD —— V P Input low voltage; all digital inputs V IL — — 0.35 × VDD7 P Input hysteresis; all digital inputs V hys 0.06 × VDD —— m V8 9 C Input leakage current; input only pins 2 |IIn|— 0 . 1 1 μA 10 P High impedance (off-state) leakage current 2 |IOZ|— 0 . 1 1 μA
11 C Total leakage combined for all inputs and Hi-Z pins
— All input only and I/O 2 |IOZTOT|— — 2 μA
12 P Internal pullup resistors 3 RPU 20 45 65 k Ω
13 P Internal pulldown resistors 4 RPD 20 45 65 k Ω
DC injection current 5, 6, 7 VIN < VSS, VIN > VDD Single pin limit Total MCU limit, includes sum of all stressed pins IIC –0.2 0.2 mA
15 C Input capacitance; all non-supply pins C In —— 8 p F
16 C RAM retention voltage V RAM 0.6 1.0 — V 17 P POR re-arm voltage 8 VPOR 0.9 1.4 2.0 V
18 D POR re-arm time t POR 10 — — μs
Low-voltage detection threshold — high range VDD falling VDD rising VLVD1 3.9 4.0 4.0 4.1 4.1 4.2 V P Low-voltage detection threshold — low range VDD falling VDD rising VLVD0 2.48 2.54 2.56 2.62 2.64 2.70 V20 C Low-voltage warning threshold — high range 1 VDD falling VDD rising VLVW3 4.5 4.6 4.6 4.7 4.7 4.8 V21 P Low-voltage warning threshold — high range 0 VDD falling VDD rising VLVW2 4.2 4.3 4.3 4.4 4.4 4.5 V22 P Low-voltage warning threshold low range 1 VDD falling VDD rising VLVW1 2.84 2.90 2.92 2.98 3.00 3.06 V23 C Low-voltage warning threshold — low range 0 VDD falling VDD rising VLVW0 2.66 2.72 2.74 2.80 2.82 2.88 V24 Table 7. DC Characteristics (continued)
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 11 25 T Low-voltage inhibit reset/recover hysteresis 5 V 3 V Vhys — 100 mV 26 P Bandgap voltage reference 9 VBG 1.18 1.20 1.21 V 1 Typical values are measured at 25 °C. Characterized, not tested. 2 Measured with VIn = VDD or VSS. 3 Measured with VIn = VSS. 4 Measured with VIn = VDD. 5 All functional non-supply pins are internally clamped to VSS and VDD. 6 Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 8 Maximum is highest voltage that POR is guaranteed. 9 Factory trimmed at VDD = 5.0 V, Temp = 25 °C.
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 15 Figure 10. Typical VOH vs. IOH for Low Drive Enabled Pad (VDD = 5 V) Figure 11. Typical VOH vs. IOH for Low Drive Enabled Pad (VDD = 3 V)
3.6 Supply Current Characteristics
This section includes information about power supply current in various operating modes.
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Table 8. Supply Current Characteristics curves across voltage/temperature. 2 All modules except ADC active, ICS configured for FBE, and does not include any dc loads on port pins.
4 P Stop2 mode supply current S2I DD
5 P Stop3 mode supply current S3I
6 P RTC adder to stop2 or stop3 3
mode. Wait mode typical is 220 μA at 5 V with fBus = 1 MHz.
7 C LVD adder to stop3 (LVDE = LVDSE = 1) S3I DDLVD
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Figure 14. Typical Stop3 IDD Curves
3.7 External Oscillator (XOSC) Characteristics
Table 9. Oscillator electrical specifications (Temperature Range = –40 to 125°C Ambient)
4 MHz
1 MHz
MC9S08SE8 Series MCU Data Sheet, Rev. 4
3.8 Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) 1 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value. 2 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This parameter is characterized and not tested on each device.
10 C FLL acquisition time4
as the reference, this specification assumes it is already running.
11 C Long term jitter of DCO output clock (averaged over 2-ms
5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 21 Figure 17. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.9 ADC Characteristics
Table 11. 10-Bit ADC Operating Conditions
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Figure 18. ADC Input Impedance Equivalency Diagram reference only and are not tested in production. Table 12. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 23 ADC Asynchronous Clock Source High Speed (ADLPC = 0) Df ADACK 23 . 35 MHz tADACK = 1/fADACKLow Power (ADLPC = 1) 1.25 2 3.3 Conversion Time (Including sample time) Short Sample (ADLSMP = 0) Dt ADC —2 0— ADCK cycles See SE8 reference manual for conversion time variances Long Sample (ADLSMP = 1) — 40 — Sample Time Short Sample (ADLSMP = 0) Dt ADS —3 . 5— ADCK cycles Long Sample (ADLSMP = 1) — 23.5 — Temp Sensor Slope –40°C– 25°C Dm —3 . 2 6 6— mV/°C Temp Sensor Voltage 25°CD V TEMP25 —1 . 3 9 6— m V Characteristics for 28-pin packages only Total Unadjusted Error 10-bit mode P ETUE — ±1 ±2.5 LSB3 Includes quantization8-bit mode P — ±0.5 ±1.0 Differential Non-Linearity 10-bit mode2 P DNL — ±0.5 ±1.0 LSB3 8-bit mode3 P— ±0.3 ±0.5 Integral Non-Linearity 10-bit mode T INL — ±0.5 ±1.0 LSB3 8-bit mode T — ±0.3 ±0.5 Zero-Scale Error 10-bit mode P EZS — ±0.5 ±1.5 LSB3 VADIN = VSSA 8-bit mode P — ±0.5 ±0.5 Full-Scale Error 10-bit mode T EFS — ±0.5 ±1 LSB3 VADIN = VDDA 8-bit mode T — ±0.5 ±0.5 Quantization Error 10-bit mode DE Q —— ±0.5 LSB3 8-bit mode — — ±0.5 Input Leakage Error 10-bit mode DE IL — ±0.2 ±2.5 LSB3 Pad leakage4 * RAS8-bit mode — ±0.1 ±1 Characteristics for 16-pin package only Total Unadjusted Error 10-bit mode P ETUE — ±1.5 ±3.5 LSB3 Includes quantization8-bit mode P — ±0.7 ±1.5 Table 12. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
MC9S08SE8 Series MCU Data Sheet, Rev. 4 — ±0.5 ±1.0 LSB3 8-bit mode3 P— ±0.3 ±0.5 Integral Non-Linearity 10-bit mode T INL — ±0.5 ±1.0 LSB3 8-bit mode T — ±0.3 ±0.5 Zero-Scale Error 10-bit mode P EZS — ±1.5 ±2.1 LSB3 VADIN = VSSA 8-bit mode P — ±0.5 ±0.7 Full-Scale Error 10-bit mode T EFS — ±1 ±1.5 LSB3 VADIN = VDDA 8-bit mode T — ±0.5 ±0.5 Quantization Error 10-bit mode DE Q —— ±0.5 LSB3 8-bit mode — — ±0.5 Input Leakage Error 10-bit mode DE IL — ±0.2 ±2.5 LSB3 Pad leakage4 * RAS8-bit mode — ±0.1 ±1 1 Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production.
2 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
3 1 LSB =(VREFH – VREFL)/2N 4 Based on input pad leakage current. Refer to pad electricals.
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 25
3.10 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.10.1 Control Timing
Figure 19. Reset Timing Table 13. Control Timing 1 Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
1 D Bus frequency (t cyc = 1/fBus)f Bus DC — 10 MHz
2 D Internal low power oscillator period t LPO 700 — 1300 μs
3 D External reset pulse width 2
override reset requests from internal sources.
4 D Reset low drive 3
3 When any reset is initiated, internal circuitry drives the reset pin (if enabled, RSTPE = 1) low for about 34 cycles of tcyc. may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 6 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 125 °C.
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Figure 20. IRQ/Pin Interrupt Timing
3.10.2 TPM/MTIM Module Timing
Figure 21. Timer External Clock Figure 22. Timer Input Capture Pulse Table 14. TPM Input Timing
1 D External clock frequency f TPMext DC f Bus/4 MHz
2 D External clock period t TPMext 4— t cyc
Ordering Information
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 27
3.11 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section in the reference manual.
4 Ordering Information
This chapter contains ordering information for the device numbering system. Example of the device numbering system: Table 15. Flash Characteristics
3 D Internal FCLK frequency 1
1 The frequency of this clock is controlled by a software setting.
5 P Byte program time (random location) 2
calculating approximate time to program and erase.
6 P Byte program time (burst mode) 2 tBurst 4t Fcyc
7 P Page erase time 2 tPage 4000 t Fcyc
8 P Mass erase time 2 tMass 20,000 t Fcyc
10 C Data retention 4
to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
MC9S08SE8 Series MCU Data Sheet, Rev. 4
4.1 Package Information
4.2 Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 16. Table 16. Package Descriptions Pin Count Package Type Abbreviation Designator Case No. Document No.
28 Plastic Dual In-line Pin PDIP RL 710 98ASB42390B
28 Small Outline Integrated Circuit SOIC WL 751F 98ASB42345B
16 Thin Shrink Small Outline Package TSSOP TG 948F 98ASH70247A
MC9S08SE8 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 29
MC9S08SE8 Series MCU Data Sheet, Rev. 4
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MC9S08SE8 Series MCU Data Sheet, Rev. 4
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MC9S08SE8 Series MCU Data Sheet, Rev. 4
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