MC9S08PA16 NXP | Alldatasheet
Document overview
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Technical content
Supports: MC9S08PA16(A) and MC9S08PA8(A) Key features
- 8-Bit S08 central processor unit (CPU) – Up to 20 MHz bus at 2.7 V to 5.5 V across operating temperature range of -40 °C to 105 °C for V part and -40 °C to 125 °C for M part. – Supporting up to 40 interrupt/reset sources – Supporting up to four-level nested interrupt – On-chip memory – Up to 16 KB flash read/program/erase over full operating voltage and temperature – Up to 256 byte EEPROM; 2-byte erase sector; program and erase while executing flash – Up to 2048 byte random-access memory (RAM) – Flash and RAM access protection
- Power-saving modes – One low-power stop mode; reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode
- Clocks – Oscillator (XOSC) - loop-controlled Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz – Internal clock source (ICS) - containing a frequency- locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allowing 1% deviation across temperature range of 0 °C to 70 °C and 2% deviation across the whole operating temperature; up to 20 MHz
- System protection – Watchdog with independent clock source – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset
- Development support – Single-wire background debug interface – Breakpoint capability to allow three breakpoints setting during in-circuit debugging – On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes
- Peripherals – ACMP - one analog comparator with both positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering – ADC - 12-channel, 12-bit resolution; 2.5 µs conversion time; data buffers with optional watermark; automatic compare function; internal bandgap reference channel; operation in stop mode; optional hardware trigger – CRC - programmable cyclic redundancy check module – FTM - two flex timer modulators modules including one 6-channel and one 2-channel ones; 16-bit counter; each channel can be configured for input capture, output compare, edge- or center-aligned PWM mode – IIC - One inter-integrated circuit module; up to 400 kbps; multi-master operation; programmable slave address; supporting broadcast mode and 10-bit addressing; supporting SMBUS and PMBUS – MTIM - One modulo timer with 8-bit prescaler and overflow interrupt – RTC - 16-bit real timer counter (RTC) – SCI - two serial communication interface (SCI/ UART) modules optional 13-bit break; full duplex non-return to zero (NRZ); LIN extension support – SPI - one 8-bit serial peripheral interface (SPI) modules; full-duplex or single-wire bidirectional; master or slave mode NXP Semiconductors Document Number MC9S08PA16 Data Sheet: Technical Data Rev. 4, 03/2020 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. MC9S08PA16A and MC9S08PA8A are recommended for new design
- Input/Output – Up to 37 GPIOs including one output-only pin – One 8-bit keyboard interrupt module (KBI) – Two true open-drain output pins – Four, ultra-high current sink pins supporting 20 mA source/sink current
- Package options – 44-pin LQFP – 32-pin LQFP – 20-pin SOIC; 20-pin TSSOP – 16-pin TSSOP MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020
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MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 3
1 MCU block diagram
The block diagram below shows the structure of the MCUs.
- PTD0, PTD1, PTB4 and PTB5 can provide high sink/source current drive.
20 MHz INTERNAL CLOCK
- The secondary power pair of V DD and V SS (pin 11, 27 and 28 in 44-pin package) are not bonded in 32-pin, 20-pin or 16-pin packages.
- PTA2 and PTA3 operate as true-open drain when working as output.
- PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin.
Figure 1. MCU block diagram
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2 Orderable part numbers
Table 1. Ordering information
3.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
3.2 Format
Part numbers for this device have the following format: MC 9 S08 PA AA (V) B CC
3.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values MC Qualification status • MC = fully qualified, general market flow
9 Memory • 9 = flash based
S08 Core • S08 = 8-bit CPU PA Device family • PA AA Approximate flash size in KB • 16 = 16 KB
- 8 = 8 KB (V) Mask set version • (blank) = Any version
- A = Rev. 2 or later version, this is recommended for new design B Operating temperature range (°C) • M = –40 to 125
- V = –40 to 105
- LC = 32-LQFP
- TJ = 20-TSSOP
- WJ = 20-SOIC
- TG = 16-TSSOP
3.4 Example
This is an example part number: Part identification MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020
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4 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. parameter tables where appropriate.
5.1 Thermal handling ratings
- Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.2 Moisture handling ratings
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -6000 +6000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105 °C for V part and 125 °C for M part -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
5.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in below table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Symbol Description Min. Max. Unit VDD Supply voltage –0.3 6.0 V IDD Maximum current into VDD — 120 mA VDIO Digital input voltage (except RESET, EXTAL, XTAL, or true open drain pin PTA2 and PTA3) –0.3 VDD + 0.3 V Digital input voltage (true open drain pin PTA2 and PTA3) -0.3 6 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V ID Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V 1. All digital I/O pins, except open-drain pin PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 is only clamped to VSS. Ratings MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020
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6.1.1 DC characteristics
Table 3. DC characteristics
5 V, Iload =
5 V — — -100 mA
3 V — — -50
5 V, Iload = 5
5 V, Iload
5 V — — 100 mA
3 V — — 50
Table continues on the next page...
Table 3. DC characteristics (continued)
- Typical values are measured at 25 °C. Characterized, not tested.
- Only PTB4, PTB5, PTD0, PTD1 support ultra high current output.
- The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
- All functional non-supply pins, except for , are internally clamped to VSS and VDD.
- Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the large one.
- Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
very low (which would reduce overall power consumption). Table 4. LVD and POR Specification Table continues on the next page...
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Table 4. LVD and POR Specification (continued)
- Maximum is highest voltage that POR is guaranteed.
- POR ramp time must be longer than 20us/V to get a stable startup.
- Rising thresholds are falling threshold + hysteresis.
- Voltage factory trimmed at VDD = 5.0 V, Temp = 25 °C
Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V)
Figure 3. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V) Figure 4. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V)
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Figure 7. Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V) Figure 8. Typical IOL Vs. VOL (high drive strength) (VDD = 5 V)
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Figure 9. Typical IOL Vs. VOL (high drive strength) (VDD = 3 V)
6.1.2 Supply current characteristics
Table 5. Supply current characteristics
1 C Run supply current FEI mode,
2 C Run supply current FEI mode,
3 P Run supply current FBE
Table continues on the next page...
Table 5. Supply current characteristics (continued)
4 P Run supply current FBE
5 P Wait mode current FEI mode,
6 C Stop3 mode supply current
7 C ADC adder to stop3
8 C LVD adder to stop34 — — 5 128 — µA
- Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
- RTC adder cause <1 µA IDD increase typically, RTC clock source is 1kHz LPO clock.
- ACMP adder cause <10 µA IDD increase typically.
- LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms.
6.1.3 EMC performance
AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
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6.1.3.1 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors for 44-pin LQFP package
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
measured orientations in each frequency range.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
6.2.1 Control timing
Table 7. Control timing
1 P Bus frequency (tcyc = 1/fBus) fBus DC — 20 MHz
4 D Reset low drive trstdrv 34 × tcyc — — ns
5 D BKGD/MS setup time after issuing background
6 D BKGD/MS hold time after issuing background
7 D IRQ pulse width Asynchronous
8 D Keyboard interrupt pulse
Table continues on the next page...
Table 7. Control timing (continued)
9 C Port rise and fall time -
- Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
- This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
- To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after
- This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
- Timing is shown with respect to 20% VDD and 80% VDD levels, across operating temperature range.
Figure 10. Reset timing Figure 11. IRQ/KBIPx timing
6.2.2 Debug trace timing specifications
Table 8. Debug trace operating behaviors
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Figure 12. TRACE_CLKOUT specifications Figure 13. Trace data specifications
6.2.3 FTM module timing
synchronizers operate from the current bus rate clock. Table 9. FTM input timing
1 D External clock
2 D External clock
3 D External clock
4 D External clock
5 D Input capture
Figure 14. Timer external clock
Figure 15. Timer input capture pulse
6.3.1 Thermal characteristics
Table 10. Thermal characteristics
- -40 to 125 for M part
- -40 to 105 for V part Junction temperature range TJ • -40 to 135 for M part
- -40 to 125 for V part Thermal resistance single-layer board 44-pin LQFP RθJA 76 °C/W 32-pin LQFP RθJA 88 °C/W 20-pin SOIC RθJA 82 °C/W 20-pin TSSOP RθJA 116 °C/W 16-pin TSSOP RθJA 130 °C/W Thermal resistance four-layer board 44-pin LQFP RθJA 54 °C/W 32-pin LQFP RθJA 59 °C/W 20-pin SOIC RθJA 54 °C/W 20-pin TSSOP RθJA 76 °C/W 16-pin TSSOP RθJA 87 °C/W 6.3 Thermal specifications MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020
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- Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA x chip power dissipation.
7 Peripheral operating requirements and behaviors
7.1 External oscillator (XOSC) and ICS characteristics
Table 11. XOSC and ICS specifications (temperature range = -40 to 105 °C for V part and -40
1 C Oscillator
2 D Load capacitors C1, C2 See Note3
3 D Feedback
4 D Series resistor -
5 D Series resistor -
4 MHz — 0 — kΩ
6 C Crystal start-up
7 T Internal reference start-up time tIRST — 20 50 µs
Table continues on the next page...
8 D Square wave
9 P Average internal reference frequency -
10 P DCO output frequency range - trimmed fdco_t 16 — 20 MHz
11 P Total deviation
12 C FLL acquisition time5, 7 tAcquire — — 2 ms
13 C Long term jitter of DCO output clock
- Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
- When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25
- See crystal or resonator manufacturer's recommendation.
- Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
- This parameter is characterized and not tested on each device.
- Proper PC board layout procedures must be followed to achieve specifications.
- This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or
the reference, this specification assumes it is already running.
- Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Figure 16. Typical crystal or resonator circuit
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7.2 NVM specifications
the flash and EEPROM memories. Table 12. Flash clock characteristics and erase times are also a function of the NVM operating frequency, fNVMOP. Table 13. Flash timing characteristics Table continues on the next page...
Table 13. Flash timing characteristics (continued)
7.3 Analog
7.3.1 ADC characteristics
Table 14. 5 V 12-bit ADC operating conditions
- f ADCK > 4 MHz
- f ADCK < 4 MHz RAS — kΩ External to MCU 10-bit mode
- f ADCK > 4 MHz
- f ADCK < 4 MHz 8-bit mode (all valid fADCK) — — 10 ADC conversion clock frequency High speed (ADLPC=0) fADCK 0.4 — 8.0 MHz — Low power (ADLPC=1) 0.4 — 4.0 Peripheral operating requirements and behaviors MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020
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- Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production. Figure 17. ADC input impedance equivalency diagram Table 15. 12-bit ADC Characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page...
Table 15. 12-bit ADC Characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- 1 LSB = (VREFH - VREFL)/2N
- Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
- IIn = leakage current (refer to DC characteristics)
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7.3.2 Analog comparator (ACMP) electricals
Table 16. Comparator electrical specifications
7.4 Communication interfaces
7.4.1 SPI switching specifications
high drive strength is enabled for SPI output pins. Table 17. SPI master mode timing Table continues on the next page...
Table 17. SPI master mode timing (continued)
- If configured as an output.
Figure 18. SPI master mode timing (CPHA=0)
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Figure 19. SPI master mode timing (CPHA=1) Table 18. SPI slave mode timing
Figure 20. SPI slave mode timing (CPHA = 0) Figure 21. SPI slave mode timing (CPHA=1)
8.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
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9.1 Signal multiplexing and pin assignments
for selecting which ALT functionality is available on each pin. Table 19. Pin availability by package pin-count Table continues on the next page...
Table 19. Pin availability by package pin-count (continued)
- This is a high current drive pin when operated as output.
- This is a true open-drain pin when operated as output.
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9.2 Device pin assignment
Pins in bold are not available on less pin-count packages.
- High source/sink current pins
Figure 22. MC9S08PA16 44-pin LQFP package
- High source/sink current pins
Pins in are not available on less pin-count packages. Figure 23. MC9S08PA16 32-pin LQFP package bold are not available on less pin-count packages.
- High source/sink current pins
Figure 24. MC9S08PA16 20-pin SOIC and TSSOP package
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PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Pins in PTA5/IRQ/TCLK0/RESET PTB5/FTM2CH5/SS0 Figure 25. MC9S08PA16 16-pin TSSOP package The following table provides a revision history for this document. Table 20. Revision history
- Updated footnote on the S3I DD in Supply current characteristics
- Added EMC radiated emissions operating behaviors
- Updated the typical of f int_t to 31.25 kHz and updated footnote to tAcquire in External oscillator (XOSC) and ICS characteristics
- Updated the assumption for all the timing values in SPI switching specifications
- Updated the rating descriptions for t Rise and tFall in Control timing
- Updated the part number format to add new field for new part numbers in Fields 3 06/2015 • Corrected the Min. of the t extrst in Control timing
- Updated Thermal characteristics to add footnote to the TA and removed redundant information.Updated the symbol of θJA to RθJA. 4 03/2020 • Added MCU block diagram.
- Added new parts of MC9S08PA16AMTJ, MC9S08PA16AMTG and MC9S08PA8AMTG and updated related information in the whole book.
- Added new section of Orderable part numbers
- Updated T j in the Thermal characteristics.
- Updated flash characteristics in the NVM specifications
- Updated S3I DD values in the Supply current characteristics
Revision history
MC9S08PA16 Series Data Sheet, Rev. 4, 03/2020 NXP Semiconductors 35
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