MCF51JG256DS NXP | Alldatasheet
Document overview
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Technical content
© Freescale Semiconductor, Inc., 2013. All rights reserved. Freescale Semiconductor MCF51JG256DS Rev.1.1, 07/2013 This is the MCF51JG256 Data Sheet set consisting of the following files:
- MCF51JG256 Data Sheet Addendum, Rev 1
- MCF51JG256 Data Sheet, Rev 1 MCF51JG256 Data Sheet
© Freescale Semiconductor, Inc., 2013. All rights reserved. Freescale Semiconductor Data Sheet Addendum MCF51JG256DSAD Rev.1, 07/2013 Table of ContentsThis errata document describes corrections to the MCF51JG256 Microcontroller Data Sheet, order number MCF51JG256DS. For convenience, the addenda items are grouped by revision. Please check our website at http://www.freescale.com for the latest updates. The current version available of the MCF51JG256 Microcontroller Data Sheet is Revision 1.0. MCF51JG256 Data Sheet Addendum
2 Revision history
Table 2 provides a revision history for this addendum. Table 1. MCF51JG256DS Rev 1.0 addendum Updated the numbers in “Power Mode Transition Operating Behaviors” table. Table 2. Revision history table temperature range of the chip.
1.85 V/(VDD slew
1 Normal boot (FTFL_FOPT[LPBOOT] is 1).
2 The wake-up time includes the execution time for small amount of firmware used to produce
falling-edge of GPIO clear performed by software.
Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Document Number: MCF51JG256DSAD Rev.1
MCF51JG256 Microcontroller
Features
- Operating characteristics – Voltage range 1.85 V to 3.6 V – Flash write voltage 1.85 V to 3.6 V – Temperature range (ambient) -40 °C to 85 °C
- Core features – Up to 50 MHz Version 1 (V1) ColdFire CPU – Provides 1.10 DMIPS(2.1) per MHz performance when running from internal RAM, 0.99 DMIPS per MHz when running from flash – Enhanced Multiply-Accumulate Unit (EMAC) – Hardware divide
- Clocks – 1 MHz to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator(MCG)
- System debug, protection, and power management – Various stop, wait, and run modes to provide low power based on application needs – Illegal opcode and illegal address detection with programmable reset or processor exception response – Hardware CRC module to support fast cyclic redundancy checks – Cryptographic Acceleration Unit (CAU) – Random Number Generator Accelerator (RNGA)
- Debug – Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM connection – EzPort support flash In-System Programming
- DMA controller – Four independently programmable DMA controller channels for directly transferring data between system memory and I/O peripherals
- Timers – Motor control/general purpose timer (FTM) – 16-bit modulo timer (MTIM) – Low-power timer/pulse counter (LPTMR0)
- Communications – Universal asynchronous receivers/transmitters (UART)/Serial communications interface (SCI) with Smart Card support and FIFO – Serial peripheral interface (SPI) with FIFO – Inter-Integrated Circuit (I2C) – USB Full Speed/Low Speed OTG/Host/Device – Serial Audio Interface (SAI), to support Full Duplex Serial Interfaces with Frame Sync I2S, TDM, AC97, and CODEC, on MCF51Jx families only
- Input/output – All pins with interrupt with selectable polarity – Up to 14 pins with programmable glitch filter – Up to 14 rapid general purpose I/O (RGPIO) pins
- On-Chip Memory – Flash FlexMemory for additional program space or EEPROM – Flash security features and block protection
- System RAM – Protected from single-bit errors by nibble parity checking – Ability for software to insert single-bit errors to "check the checkers" Freescale Semiconductor Document Number: MCF51JG256 Data Sheet: Technical Data Rev. 1, 01/2013 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2013 Freescale Semiconductor, Inc.
2.6 Relationship between ratings and operating
4.2.5.1 Diagram: Typical IDD_RUN operating
4.2.6.1 Designing with radiated emissions in
5.3.1.1 Flash timing specifications —
5.3.1.2 Flash timing specifications —
5.3.1.5 Write endurance to FlexRAM for
5.4.2.1 Oscillator DC electrical specifications. 27 5.4.3.1 32 kHz oscillator DC electrical 5.4.3.2 32 kHz oscillator frequency MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 2 Freescale Semiconductor, Inc.
1.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
1.2 Format
Part numbers for this device have the following format: Q CCCC DD MMM T PP
1.2.1 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • P = Prequalification
- M = Fully qualified, general market flow CCCC Core code CF51 = ColdFire V1 DD Device number JG MMM Memory size 256 = 256K Flash T Temperature range (°C) C = –40 to 85 free)
1.2.2 Example
MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. Freescale Semiconductor, Inc. 3
Terminology and guidelines
2.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
2.1.1 Example
This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V
2.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
2.2.1 Example
This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
2.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. Terminology and guidelines MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 4 Freescale Semiconductor, Inc.
2.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF
2.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered.
2.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V
2.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. Freescale Semiconductor, Inc. 5
2.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
2.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
2.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 6 Freescale Semiconductor, Inc.
2.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
2.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
2.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. Freescale Semiconductor, Inc. 7
3.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
3.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
3.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 500 V 2 VMM Electrostatic discharge voltage, machine model -200 200 V 3 ILAT Latch-up Current at ambient temperature of 85 °C -100 100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD22-A115, Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM). Ratings MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 8 Freescale Semiconductor, Inc.
3.4 Voltage and current operating ratings
Table 1. Voltage and current operating ratings
4.1 AC electrical characteristics
Figure 1. Input signal measurement reference MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
4.2.1 Voltage and current operating requirements
Table 2. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.85 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.85 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V IIC DC injection current — single pin
- V IN > VDD
- V IN < VSS –0.2 mA mA DC injection current — total MCU limit, includes sum of all stressed pins
- V IN > VDD
- V IN < VSS mA mA VRAM VDD voltage required to retain RAM 1.2 -- V 1. The device always interprets an input as a 1 when the input is greater than or equal to VIH (min.) and less than or equal to VIH (max.), regardless of whether input hysteresis is turned on. 2. The device always interprets an input as a 0 when the input is less than or equal to VIL (max.) and greater than or equal to VIL (min.), regardless of whether input hysteresis is turned on. 3. All functional non-supply pins (except RESET) are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIN > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption).
4.2.2 LVD and POR operating requirements
Table 3. LVD and POR operating requirements Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 10 Freescale Semiconductor, Inc.
Table 3. LVD and POR operating requirements (continued)
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 2.6 2.7 2.8 2.9 2.70 2.80 2.90 3.00 2.8 2.9 3.0 3.1 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — +/-80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 1.7 1.8 1.9 2.0 1.80 1.90 2.00 2.10 1.9 2.0 2.1 2.2 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — +/-60 — mV tLPO Internal low power oscillator period factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage
4.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -9 mA
- 1.85 V ≤ V DD ≤ 2.7 V, IOH = -3 mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2 mA
- 1.85 V ≤ V DD ≤ 2.7 V, IOH = -0.6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA Table continues on the next page... Nonswitching electrical specifications MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. Freescale Semiconductor, Inc. 11
Table 4. Voltage and current operating behaviors (continued)
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 9 mA
- 1.85 V ≤ V DD ≤ 2.7 V, IOL = 3 mA 0.5 0.5 V V Output low voltage — low drive strength
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2 mA
- 1.85 V ≤ V DD ≤ 2.7 V, IOL = 0.6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin)
- @ full temperature range
- @ 25 °C 1.0 0.1 μA μA IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 2 RPD Internal pulldown resistors 20 50 kΩ 3 1. Tested by ganged leakage method 2. Measured at Vinput = VSS 3. Measured at Vinput = VDD
4.2.4 Power mode transition operating behaviors
- CPU and system clocks = 50 MHz
- Bus clock (and flash and FlexBus clocks) = 25 MHz
Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.
- RUN → VLLS1
- VLLS1 → RUN 4.4 124 μs μs RUN → VLLS2 → RUN
- RUN → VLLS2
- VLLS2 → RUN 4.6 83.6 μs μs Table continues on the next page... Nonswitching electrical specifications MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 12 Freescale Semiconductor, Inc.
Table 5. Power mode transition operating behaviors (continued)
- RUN → VLLS3
- VLLS3 → RUN 4.4 83.6 μs μs RUN → VLPS → RUN
- RUN → VLPS
- VLPS → RUN 4.4 4.6 μs μs RUN → STOP → RUN
- RUN → STOP
- STOP → RUN 4.4 4.6 μs μs 1. Normal boot (FTFL_FOPT[LPBOOT] is 1)
4.2.5 Current consumption operating behaviors
Table 6. Current consumption operating behaviors
- @ 1.85 V
- @ 3.0 V mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
- @ 1.85 V
- @ 3.0 V 19.5 25.5 mA mA IDD_WAIT Wait mode current at VDD = 3.0 V — 13 19 mA 3 IDD_STOP Stop mode current at VDD = 3.0 V — 0.4 1.8 mA -- IDD_VLPR Very-low-power run mode current at VDD = 3.0 V. All peripheral clocks disabled. — 1.8 3.6 mA 4 IDD_VLPR Very-low-power run mode current at VDD = 3.0 V. All peripheral clocks enabled. — 1.8 3.6 mA 5 IDD_VLPW Very-low-power wait mode current at VDD = 3 V — 0.3 1.7 mA 6 IDD_VLPS Very-low-power stop mode current at VDD = 3.0 V — 50 900 μA 7 IDD_VLLS3 Very low-leakage stop mode 3 current at VDD = 3.0 V — 3.5 200 μA 7 IDD_VLLS2 Very low-leakage stop mode 2 current at VDD = 3.0 V — 2.8 110 μA 7 IDD_VLLS1 Very low-leakage stop mode 1 current at VDD = 3.0 V — 2.3 63 μA 7 Nonswitching electrical specifications MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. Freescale Semiconductor, Inc. 13
- 50 MHz CPU clock not including peripherals or external loads. 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled. 2. 50 MHz CPU clock not including peripherals or external loads. 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled. 3. 50 MHz CPU clock. 25 MHz bus clock. MCG configured for FEI mode. 4. 2 MHz CPU clock and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. Code executing from flash. 5. 2 MHz CPU clock and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled, but peripherals are not in active operation. Code executing from flash. 6. 2 MHz CPU clock and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. 7. OSC clocks disabled.
4.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
- MCG in FBE mode, except for 50 MHz core (FEI mode)
- For the All Peripheral Clocks Disabled curve, all peripheral clocks are disabled except flash
- For the All Peripheral Clocks Enabled curve, all peripheral clocks are enabled but peripherals are not in active operation
- No GPIOs toggled
- Code execution from flash memory Nonswitching electrical specifications MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 14 Freescale Semiconductor, Inc.
Figure 2. Run mode supply current vs. core frequency
4.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
measured orientations in each frequency range.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
4.2.6.1 Designing with radiated emissions in mind
- Perform a keyword search for “EMC design.”
4.2.7 Capacitance attributes
Table 8. Capacitance attributes
4.3 Switching electrical specifications
Table 9. Device clock specifications MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 16 Freescale Semiconductor, Inc.
4.3.1 General Switching Specifications
filter, digital or analog, unless otherwise specified. Table 10. General control timing
- The greater synchronous or asynchronous timing must be met.
- This is the shortest pulse that is guaranteed to be recognized.
Figure 3. GPIO timing diagram MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
filter, digital or analog, unless otherwise specified. Table 11. RGPIO/SCI general control timing
- The greater synchronous or asynchronous timing must be met.
4.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
4.4.2 Thermal attributes
Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 18 Freescale Semiconductor, Inc.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
Environmental Conditions—Forced Convection (Moving Air).
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
- Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
the top of the package and the cold plate.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
5.1.1 Debug specifications
Table 13. Background debug mode (BDM) timing
- To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after
5.2.1 EzPort switching specifications
Table 14. EzPort signal timing Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
Table 14. EzPort signal timing (continued) Input slew rate of 2 ns and output load of 35 pF. Figure 4. EzPort timing diagram
5.3.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module. MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 20 Freescale Semiconductor, Inc.
5.3.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 15. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
5.3.1.2 Flash timing specifications — commands
Table 16. Flash command timing specifications
- 32 KB data flash
- 128 KB program flash 0.5 1.7 ms ms trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs tersblk32k tersblk128k Erase Flash Block execution time
- 32 KB data flash
- 128 KB program flash 220 465 1850 ms ms tersscr Erase Flash Sector execution time — 14 114 ms 2 tpgmsec512 tpgmsec1k Program Section execution time
- 512 bytes flash
- 1 KB flash 4.7 9.3 ms ms trd1all Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs tersall Erase All Blocks execution time — 490 4200 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 Table continues on the next page... Memories and memory interfaces MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. Freescale Semiconductor, Inc. 21
Table 16. Flash command timing specifications (continued)
- control code 0x01
- control code 0x02
- control code 0x04
- control code 0x08 200 150 150 μs μs μs μs tpgmpart32k Program Partition for EEPROM execution time
- 32 KB FlexNVM ms tsetramff tsetram8k tsetram32k Set FlexRAM Function execution time:
- Control Code 0xFF
- 8 KB EEPROM backup
- 32 KB EEPROM backup 0.3 0.7 0.5 1.0 μs ms ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time — 175 260 μs 3 teewr8b8k teewr8b16k teewr8b32k Byte-write to FlexRAM execution time:
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 340 385 475 1700 1800 2000 μs μs μs Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 175 260 μs teewr16b8k teewr16b16k teewr16b32k Word-write to FlexRAM execution time:
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 340 385 475 1700 1800 2000 μs μs μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 360 540 μs teewr32b8k teewr32b16k teewr32b32k Longword-write to FlexRAM execution time:
- 8 KB EEPROM backup
- 16 KB EEPROM backup
- 32 KB EEPROM backup 545 630 810 1950 2050 2250 μs μs μs 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. Memories and memory interfaces MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 22 Freescale Semiconductor, Inc.
5.3.1.3 Flash high voltage current behaviors
Table 17. Flash high voltage current behaviors
5.3.1.4 Reliability specifications
Table 18. NVM reliability specifications
- EEPROM backup to FlexRAM ratio = 16
- EEPROM backup to FlexRAM ratio = 128
- EEPROM backup to FlexRAM ratio = 512
- EEPROM backup to FlexRAM ratio = 4096
- EEPROM backup to FlexRAM ratio = 8192 35 K 315 K 1.27 M 10 M 20 M 175 K 1.6 M 6.4 M 50 M 100 M writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 105°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 105°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum and typical values assume all byte-writes to FlexRAM.
5.3.1.5 Write endurance to FlexRAM for EEPROM
can be set to any of several non-zero values. MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_FlexRAM = × Write_efficiency × nEEPROM – 2 × EEESIZEEEESIZE nvmcycd where
- Writes_FlexRAM — minimum number of writes to each FlexRAM location
- EEPROM — allocated FlexNVM based on DEPART; entered with the Program Partition command
- EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command
- Write_efficiency —
- 0.25 for 8-bit writes to FlexRAM
- 0.50 for 16-bit or 32-bit writes to FlexRAM
- n nvmcycd — data flash cycling endurance (the following graph assumes 10,000 cycles) Memories and memory interfaces MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 24 Freescale Semiconductor, Inc.
Figure 5. EEPROM backup writes to FlexRAM
5.4.1 MCG specifications
Table 19. MCG specifications Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
Table 19. MCG specifications (continued)
- PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
- PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 26 Freescale Semiconductor, Inc.
- f vco = 48 MHz
- f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
- f vco = 48 MHz
- f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 11 1. Typ. value indicates typical deviation at 25 °C. Max. value indicates maximum deviation from 25 °C to the temperature extreme. 2. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 3. Subject to change after process characterization. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
5.4.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
5.4.2.1 Oscillator DC electrical specifications
Table 20. Oscillator DC electrical specifications Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
Table 20. Oscillator DC electrical specifications (continued)
- 32 kHz
- 1 MHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 500 200 200 300 950 1.2 1.5 nA μA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
- 32 kHz
- 1 MHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 300 400 500 2.5 μA μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Table continues on the next page... Clock modules MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 28 Freescale Semiconductor, Inc.
- 1 MHz resonator
- 2 MHz resonator
- 4 MHz resonator
- 8 MHz resonator
- 16 MHz resonator
- 20 MHz resonator
- 32 MHz resonator 6.6 3.3 kΩ kΩ kΩ kΩ kΩ kΩ kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using either the integrated capacitors or by using external components. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.
5.4.2.2 Oscillator frequency specifications
Table 21. Oscillator frequency specifications Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
Table 21. Oscillator frequency specifications (continued)
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
This section describes the module electrical characteristics. Table 22. 32kHz oscillator DC electrical specifications
- When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices. Table 23. 32 kHz oscillator frequency specifications
- Proper PC board layout procedures must be followed to achieve specifications.
MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 30 Freescale Semiconductor, Inc.
- This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
- The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
5.5.1 SPI switching specifications
VDD and 70% VDD, unless noted, input slew rate of 2 ns and 35 pF load on all SPI pins. rate configuration) and high drive strength is enabled for SPI output pins. Table 24. SPI master mode timing MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
Table 25. SPI slave mode timing (continued) Figure 8. SPI slave mode timing (CPHA=0) MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
Figure 9. SPI slave mode timing (CPHA=1)
5.5.2 USB electrical specifications
5.5.3 USB DCD electrical specifications
Table 26. USB DCD electrical specifications
5.5.4 VREG electrical specifications
Table 27. VREG electrical specifications Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 34 Freescale Semiconductor, Inc.
Table 27. VREG electrical specifications (continued)
- VREGIN = 5.0 V and temperature=25 °C
- Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
- Run mode
- Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
5.5.5 I2S/SAI Switching Specifications
frame sync (FS) signal shown in the following figures. Table 28. I2S/SAI master mode timing Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
Table 28. I2S/SAI master mode timing (continued)
- This parameter is limited in VLPx modes.
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 10. I2S/SAI timing — master modes Table 29. I2S/SAI slave mode timing Table continues on the next page... MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 36 Freescale Semiconductor, Inc.
Table 29. I2S/SAI slave mode timing (continued)
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 11. I2S/SAI timing — slave modes
6.1 Obtaining package dimensions
Package dimensions are provided in package drawing. MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013.
7.1 Pinout Diagram
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin.
25 PTB6/SPI2_CLK/RGPIO14
27 PTC0/SPI2_SS/USBCLKIN
29 PTC2/SCI1_RX/SPI1_MISO
31 IRQ1/PTC4/SCI1_RTS_b
32 IRQ2/PTC5/SCI1_CTS_b/TMR_CLKIN0
33 VDD
34 VSS
36 RESET_B
38 XTAL
40 PTD0/SPI0_SS/SAI0_TX_FS
42 PTD2/SCI0_RX/SPI0_MISO/SAI0_TX_BCLK
44 VSS
Figure 12. MCF51JG256 44-pin MAPLGA Pinout Diagram MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 38 Freescale Semiconductor, Inc.
PTD4 is adjacent to EXTAL32 and may inject coupling noise on EXTAL32 when both PTD4 as well as EXTAL32 is being used. So it is highly recommended that PTD4 be only used for the cases where EXTAL32 is not used at all and system relies on internal RC clock or external EXTAL clock.
7.2 Signal Multiplexing and Pin Assignments
Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 EZPORT
1 VDD VDD VDD
2 VREGIN VREGIN VREGIN
3 VOUT33 VOUT33 VOUT33
4 USB_DM USB_DM USB_DM
5 USB_DP USB_DP USB_DP
6 BKGD/
7 EXTAL32 EXTAL32 EXTAL32
8 XTAL32 XTAL32 XTAL32
9 PTA1/
FTM1_CH0/ IIC1_SCL/ RGPIO1 Disabled Disabled PTA1 FTM1_CH0 IIC1_SCL RGPIO1
10 PTA2/
FTM1_CH1/ IIC1_SDA/ RGPIO2 Disabled Disabled PTA2 FTM1_CH1 IIC1_SDA RGPIO2
11 VDD VDD VDD
12 VSS VSS VSS
13 PTA3/
FTM1_CH2/ CLKOUT/ SAI0_RX_BCLK/ RGPIO3 Disabled Disabled PTA3 FTM1_CH2 CLKOUT SAI0_RX_BCLKRGPIO3
14 PTA5/
SCI2_CTS_b/ FTM1_CH4/ SAI0_RXD/ RGPIO5 Disabled Disabled PTA5 SCI2_CTS_bFTM1_CH4 SAI0_RXD RGPIO5
15 PTA6/
SAI0_RX_FS/ RGPIO6/ EZP_DO Disabled Disabled PTA6 SAI0_RX_FSRGPIO6 EZP_DO
16 PTA7/
LPT_ALT0/ Disabled Disabled PTA7 LPT_ALT0 RGPIO7 EZP_DI Pinout MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. Freescale Semiconductor, Inc. 39
Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 EZPORT RGPIO7/ EZP_DI
17 PTB0/
EZP_CLK Disabled Disabled PTB0 RGPIO8 EZP_CLK
18 IRQ0/
EZP_MS_b/ RGPIO9/ EZP_CS_b IRQ0 IRQ0 PTB1 EZP_MS_b RGPIO9 EZP_CS_b
19 PTB2/
SCI0_RTS_b/ FTM0_CH1/ IIC0_SCL/ RGPIO10 Disabled Disabled PTB2 SCI0_RTS_bFTM0_CH1 IIC0_SCL RGPIO10
20 PTB3/
SCI0_CTS_b/ FTM0_CH0/ IIC0_SDA/ RGPIO11 Disabled Disabled PTB3 SCI0_CTS_bFTM0_CH0 IIC0_SDA RGPIO11
21 PTB4/
SCI2_TX/ SPI2_MOSI/ RGPIO12 Disabled Disabled PTB4 SCI2_TX SPI2_MOSI RGPIO12
22 VSS VSS VSS
23 VDD VDD VDD
24 PTB5/
SCI2_RX/ SPI2_MISO/ RGPIO13 Disabled Disabled PTB5 SCI2_RX SPI2_MISO RGPIO13
25 PTB6/
SPI2_CLK/ RGPIO14 Disabled Disabled PTB6 SPI2_CLK RGPIO14
26 PTB7/
SCI1_TX/ SPI1_MOSI/ RGPIO15 Disabled Disabled PTB7 SCI1_TX SPI1_MOSI RGPIO15
27 PTC0/
SPI2_SS/ USBCLKIN Disabled Disabled PTC0 SPI2_SS USBCLKIN
28 IRQ3/
FTM1_CH5/ CLKOUT IRQ3 IRQ3 PTC1 FTM1_CH5 CLKOUT
29 PTC2/
SCI1_RX/ SPI1_MISO Disabled Disabled PTC2 SCI1_RX SPI1_MISO
30 PTC3/
SPI1_CLK/ Disabled Disabled PTC3 SPI1_CLK Pinout MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. 40 Freescale Semiconductor, Inc.
Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 EZPORT
31 IRQ1/
SCI1_RTS_b IRQ1 IRQ1 PTC4 SCI1_RTS_b
32 IRQ2/
SCI1_CTS_b/ TMR_CLKIN0 IRQ2 IRQ2 PTC5 SCI1_CTS_bTMR_CLKIN0
33 VDD VDD VDD
34 VSS VSS VSS
35 ENABLE_USB_
ENABLE_USB_ REG ENABLE_USB_ REG
36 RESET_B RESET_B RESET_B
37 EXTAL EXTAL EXTAL
38 XTAL XTAL XTAL
39 PTC7/
SPI1_SS Disabled Disabled PTC7 SPI1_SS
40 PTD0/
SPI0_SS/ SAI0_TX_FS Disabled Disabled PTD0 SPI0_SS SAI0_TX_FS
41 PTD1/
SCI0_TX/ SPI0_MOSI/ SAI0_TXD Disabled Disabled PTD1 SCI0_TX SPI0_MOSI SAI0_TXD
42 PTD2/
SCI0_RX/ SPI0_MISO/ SAI0_TX_BCLK Disabled Disabled PTD2 SCI0_RX SPI0_MISO SAI0_TX_BCLK
43 PTD3/
SPI0_CLK/ SAI0_MCLK/ SAI0_CLKIN Disabled Disabled PTD3 SPI0_CLK SAI0_MCLK/ SAI0_CLKIN
44 VSS VSS VSS
MCF51JG256 Microcontroller Data Sheet, Rev. 1, 01/2013. Freescale Semiconductor, Inc. 41
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