98ARB18753C

MC74HC1G00_V01 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• High Speed: tPD = 7 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 1 /C0109A (Max) at TA = 25°C
• High Noise Immunity
• Balanced Propagation Delays (tpLH = tpHL)
• Symmetrical Output Impedance (IOH = IOL = 2 mA)
• Chip Complexity: < 100 FETs
• NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

Figure 1. Pinout Figure 2. Logic Symbol

3 GND

ORDERING INFORMATION

XXX = Device Code M = Date Code* A = Assembly Location Y = Year W = Work Week /C0071= Pb−Free Package SC−88A DF SUFFIX CASE 419A TSOP−5 DT SUFFIX CASE 483 XX M/C0071 /C0071 M (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. XXX M/C0071 /C0071SC−74A DBV SUFFIX CASE 318BQ XXX = Specific Device Code M = Date Code /C0071 = Pb−Free Package (Note: Microdot may be in either location) XXXAYW/C0071 /C0071 XX M/C0071 /C0071 Commercial NLV Prefix

www.onsemi.com MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage SC −88A (NLV), TSOP−5 SC−88A, SC−74A −0.5 to +7.0 −0.5 to +6.5 V VIN DC Input Voltage −0.5 to VCC +0.5 V VOUT DC Output Voltage −0.5 to VCC +0.5 V IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±20 mA IOUT DC Output Source/Sink Current ±12.5 mA ICC or IGND DC Supply Current per Supply Pin or Ground Pin ±25 mA TSTG Storage Temperature Range −65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction Temperature Under Bias +150 °C /C0113JA Thermal Resistance (Note 1) SC −88A SC−74A 377 320 °C/W PD Power Dissipation in Still Air at 85°CS C −88A SC−74A 332 390 mW MSL Moisture Sensitivity Level 1 FR Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in VESD ESD Withstand Voltage (Note 2) Human Body Model Charged Device Model 2000 1000 V ILATCHUP Latchup Performance (Note 3) SC −88A (NLV), TSOP−5 SC−88A, SC−74A ±500 ±100 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm −by−1 inch, 20 ounce copper trace with no air flow per JESD51−7. 2. HBM tested to ANSI/ESDA/JEDEC JS −001−2017. CDM tested to JESD22 −C101−F. JEDEC recommends that ESD qualification to EIA/JESD22−A115A (Machine Model) be discontinued per JEDEC/JEP172A. 3. Tested to EIA/JESD78 Class II.

www.onsemi.com RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage 2.0 6.0 V VIN DC Input Voltage 0.0 VCC V VOUT DC Output Voltage 0.0 VCC V TA Operating Temperature Range −55 +125 °C tr , tf Input Rise and Fall Time SC −88A (NLV), TSOP−5 VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V 1000 600 500 400 ns Input Rise and Fall Time SC −88A, SC−74A VCC = 2,0 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 6.0 V ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS VCC TA = 25/C0053C −40°C ≤ TA ≤ 85°C −55°C ≤ TA ≤ 125°C Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit VIH High−Level Input Voltage 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.20 1.5 2.1 3.15 4.20 1.5 2.1 3.15 4.20 V VIL Low−Level Input Voltage 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 V VOH High−Level Output Voltage VIN = VIH or VIL IOH = −20 /C0109A 2.0 3.0 4.5 6.0 1.9 2.9 4.4 5.9 2.0 3.0 4.5 6.0 1.9 2.9 4.4 5.9 1.9 2.9 4.4 5.9 V VIN = VIH or VIL IOH = −2 mA IOH = −2.6 mA 4.5 6.0 4.18 5.68 4.31 5.80 4.13 5.63 4.08 5.58 VOL Low−Level Output Voltage VIN = VIH or VIL IOL = 20 /C0109A 2.0 3.0 4.5 6.0 0.0 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN = VIH or VIL IOL = 2 mA IOL = 2.6 mA 4.5 6.0 0.17 0.18 0.26 0.26 0.33 0.33 0.40 0.40 IIN Input Leakage Current VIN = 6.0 V or GND 6.0 − − /C00360.1 − /C00361.0 − /C00361.0 /C0109A ICC Quiescent Supply Current VIN = VCC or GND 6.0 − − 1.0 − 10 − 40 /C0109A

www.onsemi.com AC ELECTRICAL CHARACTERISTICS TA = 25/C0053C −40°C ≤ TA ≤ 85°C −55°C ≤ TA ≤ 125°C Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Unit tPLH, tPHL Propagation Delay, (A or B) to Y VCC = 5.0 V C L = 15 pF − 3.5 15 − 20 − 25 ns VCC = 2.0 V C L = 50 pF VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V 100 125 155 tTLH, tTHL Output Transition Time VCC = 5.0 V C L = 15 pF − 3 10 − 15 − 20 ns VCC = 2.0 V C L = 50 pF VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V 125 155 200 CIN Input Capacitance − 5 10 − 10 − 10 pF Typical @ 25/C0053C, VCC = 5.0 V CPD Power Dissipation Capacitance (Note 4) 10 pF 4. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD /C0015 VCC /C0015 fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD /C0015 VCC2 /C0015 fin + ICC /C0015 VCC.

www.onsemi.com Device Packages Specific Device Code Pin 1 Orientation (See below) Shipping† MC74HC1G00DFT1G SC−88A H1 Q2 3000 / Tape & Reel NLV74HC1G00DFT1G* SC−88A H1 Q2 3000 / Tape & Reel MC74HC1G00DFT2G SC−88A H1 Q4 3000 / Tape & Reel MC74HC1G00DFT2G−L22038** SC−88A H1 Q4 3000 / Tape & Reel NLVHC1G00DFT2G* SC−88A H1 Q4 3000 / Tape & Reel MC74HC1G00DTT1G** TSOP−5 H1 Q4 3000 / Tape & Reel NLV74HC1G00DTT1G* TSOP−5 H1 Q4 3000 / Tape & Reel MC74HC1G00DBVT1G SC−74A H1 Q4 3000 / Tape & Reel †For complete information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. **Please refer to NLV specifications for this device. Pin 1 Orientation in Tape and Reel

SC−74A CASE 318BQ ISSUE B DATE 18 JAN 2018SCALE 2:1 GENERIC MARKING DIAGRAM* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. Some products may not follow the Generic Marking. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIM MIN MAX MILLIMETERS D A 0.90 1.10 b 0.25 0.50 e 0.95 BSC A1 0.01 0.10 c 0.10 0.26 L 0.20 0.60 M 0 10 E 2.50 3.00 123 E D b A c /C0095/C0095 0.20 C AB C SEATING PLANE L M DETAIL A TOP VIEW SIDE VIEW A B END VIEW 1.35 1.65 2.85 3.15 2.40 0.70 DIMENSIONS: MILLIMETERS RECOMMENDED 0.95 PITCH 1.00 e A10.05 DETAIL A XXX M/C0071 /C0071 XXX = Specific Device Code M = Date Code /C0071 = Pb−Free Package (Note: Microdot may be in either location) MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON66279GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1SC−74A © Semiconductor Components Industries, LLC, 2018 www.onsemi.com

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A −01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. DIM A MIN MAX MIN MAX MILLIMETERS 1.80 2.200.071 0.087 INCHES B 1.15 1.350.045 0.053 C 0.80 1.100.031 0.043 D 0.10 0.300.004 0.012 G 0.65 BSC0.026 BSC J 0.10 0.250.004 0.010 K 0.10 0.300.004 0.012 N 0.20 REF0.008 REF S 2.00 2.200.079 0.087 STYLE 1: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 2: PIN 1. ANODE 2. EMITTER 3. BASE 4. COLLECTOR 5. CATHODE B0.2 (0.008) MM 12 3 A G S D 5 PL H C N J K −B− STYLE 3: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. CATHODE 1 STYLE 4: PIN 1. SOURCE 1 2. DRAIN 1/2 3. SOURCE 1 4. GATE 1 5. GATE 2 STYLE 5: PIN 1. CATHODE 2. COMMON ANODE 3. CATHODE 2 4. CATHODE 3 5. CATHODE 4 STYLE 7: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 6: PIN 1. EMITTER 2 2. BASE 2 3. EMITTER 1 4. COLLECTOR 5. COLLECTOR 2/BASE 1 XXXM/C0071 /C0071 XXX = Specific Device Code M = Date Code /C0071= Pb−Free Package GENERIC MARKING DIAGRAM* STYLE 8: PIN 1. CATHODE 2. COLLECTOR 3. N/C 4. BASE 5. EMITTER STYLE 9: PIN 1. ANODE 2. CATHODE 3. ANODE 4. ANODE 5. ANODE Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE L DATE 17 JAN 2013SCALE 2:1 (Note: Microdot may be in either location) /C0466mm inches/C0467SCALE 20:1 0.65 0.025 0.65 0.025 0.50 0.0197 0.40 0.0157 1.9 0.0748 SOLDER FOOTPRINT *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “/C0071”, may or may not be present. Some products may not follow the Generic Marking. MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98ASB42984BDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1SC−88A (SC−70−5/SOT−353) © Semiconductor Components Industries, LLC, 2018 www.onsemi.com

TSOP−5 CASE 483 ISSUE N DATE 12 AUG 2020 SCALE 2:1 XXX M/C0071 /C0071 GENERIC MARKING DIAGRAM* 0.7 0.028 1.0 0.039 /C0466mm inches/C0467SCALE 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week /C0071= Pb−Free Package XXXAYW/C0071 /C0071 Discrete/LogicAnalog (Note: Microdot may be in either location) XXX = Specific Device Code M = Date Code /C0071= Pb−Free Package NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY . DIM MIN MAX MILLIMETERS A B C 0.90 1.10 D 0.25 0.50 G 0.95 BSC H 0.01 0.10 J 0.10 0.26 K 0.20 0.60 M 0 10 S 2.50 3.00 12 3 S A G B D H C J /C0095/C0095 0.20 C ABT0.102X 2X T0.20 NOTE 5 C SEATING PLANE 0.05 K M DETAIL Z DETAIL Z TOP VIEW SIDE VIEW A B END VIEW 1.35 1.65 2.85 3.15 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98ARB18753CDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1TSOP−5 © Semiconductor Components Industries, LLC, 2018 www.onsemi.com

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