97U877AHLF

97U877AHLF IDT | Alldatasheet

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Technical content

Systems, Inc. ICS97U877 0792A—04/15/04 Block Diagram 1.8V Wide Range Frequency Clock Driver Pin Configuration 40-Pin MLF Recommended Application:  DDR2 Memory Modules / Zero Delay Board Fan Out  Provides complete DDR DIMM logic solution with ICSSSTU32864 Product Description/Features:  Low skew, low jitter PLL clock driver  1 to 10 differential clock distribution (SSTL_18)  Feedback pins for input to output synchronization  Spread Spectrum tolerant inputs  Auto PD when input signal is at a certain logic state Switching Characteristics:  Period jitter: 40ps  Half-period jitter: 60ps  CYCLE - CYCLE jitter 40ps  OUTPUT - OUTPUT skew: 40ps A B 123456 C D E F G H J K VDDQ CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND CLKC7 CLKT7 VDDQ FB_INT FB_INC FB_OUTC FB_OUTT VDDQ OE OS CLKT3 CLKC3 CLKC4 CLKT4 VDDQ CLKT9 CLKC9 CLKC8 CLKT8 VDDQ CLKC1 CLKT1 CLKT0 CLKC0 VDDQ CLKC5 CLKT5 CLKT6 CLKC6 VDDQ 11 20 ICS97U877 52-Ball BGA Top View CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 FB_OUTT FB_OUTC AV DD FB_INT CLK_INT CLK_INC FB_INC PLL Powerdown Control and Test Logic OE LD* or OE PLL bypassLD* LD*, OS or OEOS GND 10K-100k * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. 12345 6 A CLKT1 CLKT0 CLKC0 CLKC5 CLKT5 CLKT6 B CLKC1 GND GND GND GND CLKC6 C CLKC2 GND NB NB GND CLKC7 D CLKT2 VDDQ VDDQ VDDQ OS CLKT7 E CLK_INT VDDQ NB NB VDDQ FB_INT F CLK_INC VDDQ NB NB OE FB_INC G AGND VDDQ VDDQ VDDQ VDDQ FB_OUTC H AVDD GND NB NB GND FB_OUTT J CLKT3 GND GND GND GND CLKT8 K CLKC3 CLKC4 CLKT4 CLKT9 CLKC9 CLKC8

0792A—04/15/04 Pin Descriptions lanimreT emaN noitpircseD lacirtcelE scitsiretcarahC DNGAd nuorGgolanA dnuorG VA DD rewopgolanA lanimonV8.1 TNI_KLCr otsisernwodllup)mhOK001-K01(ahtiwtupnikcolC tupnilaitnereffiD CNI_KLC rotsisernwodllup)mhOK001-K01(ahtiwtupnikcolcyratnelpmoC tupnilaitnereffiD TNI_BFt upnikcolckcabdeeF tupnilaitnereffiD CNI_BFt upnikcolckcabdeefyratnemelpmoC tupnilaitnereffiD TTUO_BFt uptuokcolckcabdeeF tuptuolaitnereffiD CTUO_BFt uptuokcolckcabdeefyratnemelpmoC tuptuolaitnereffiD EO) suonorhcnysA(elbanEtuptuO tupniSOMCVL SOV roDNGotdeit(tceleStuptuO QDD )t upniSOMCVL DNGd nuorG dnuorG V QDD rewoptuptuodnacigoL lanimonV8.1 ]9:0[TKLCs tuptuokcolC stuptuolaitnereffiD ]9:0[CKLCs tuptuokcolcyratnemelpmoC stuptuolaitnereffiD BNl laboN The PLL clock buffer, ICS97U877 , is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF . ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/ FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or V DDQ . When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF . When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time t STAB . The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97U877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97U877 is characterized for operation from 0°C to 70°C.

0792A—04/15/04 Function Table stupnIs tuptuO LLP DDVAE OS OT NI_KLCT NI_KLCT KLCC KLCT TUO_BFC TUO_BF DNGH X L H L H L H f fO/dessapyB DNGH X H L H L H L f fO/dessapyB DNGL H L H ) Z(L*) Z(L*L H f fO/dessapyB DNGL L H L ,)Z(L* 7TKLC evitca ,)Z(L* 7CKLC evitca H Lf fO/dessapyB )mon(V8.1L H L H ) Z(L*) Z(L*L H n O )mon(V8.1L L H L ,)Z(L* 7TKLC evitca ,)Z(L* 7CKLC evitca HL n O )mon(V8.1H X L H L H LH n O )mon(V8.1H X H L H L HL n O )mon(V8.1X X L L ) Z(L*) Z(L*) Z(L*) Z(L*f fO )mon(V8.1X X H H d evreseR *L(Z) means the outputs are disabled to a low stated meeting the IODL limit.

0792A—04/15/04 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Current (CLK_INT, CLK_INC) IIH VI = VDDQ or GND ±250 µA Input Low Current (OE, OS, FB_INT, FB_INC) IIL VI = VDDQ or GND ±10 µA Output Disabled Low Current IODL OE = L, VODL = 100mV 100 µA IDD1.8 C L = 0pf @ 270MHz 300 mA IDDLD C L = 0pf 500 µA Input Clamp Voltage VIK VDDQ = 1.7V Iin = -18mA -1.2 V IOH = -100 µA VDDQ - 0.2 V IOH = -9 mA 1.1 1.45 V IOL =100 µA 0.25 0.10 V IOL =9 mA 0.6 V Input Capacitance1 C IN VI = GND or VDDQ 23 p F Output Capacitance1 C OUT VOUT = GND or VDDQ 23 p F 1Guaranteed by design, not 100% tested in production. Operating Supply Current High-level output voltageVOH Low-level output voltageVOL

0792A—04/15/04 Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of V DDQ and is the voltage at which the differential signal must be crossing. Recommended Operating Condition (see note1) TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDDQ , AVDD 1.7 1.8 1.9 V CLK_INT, CLK_INC, FB_INC, FB_INT 0.35 x VDDQ V OE, OS 0.35 x VDDQ V CLK_INT, CLK_INC, FB_INC, FB_INT 0.65 x VDDQ V OE, OS 0.65 x VDDQ V DC input signal voltage (note 2) VIN -0.3 VDDQ + 0.3 V DC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.3 VDDQ + 0.4 V AC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.6 VDDQ + 0.4 V Output differential cross- voltage (note 4) VOX VDDQ /2 - 0.10 V DDQ /2 + 0.10 V Input differential cross- voltage (note 4) VIX VDDQ /2 - 0.15 VDD /2 V DDQ 2 + 0.15 V High level output current IOH -9 mA Low level output current IOL 9m A Operating free-air temperature TA 07 0 ° C Differential input signal voltage (note 3) VID Low level input voltage VIL High level input voltage VIH

0792A—04/15/04 Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design. Timing Requirements TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Max clock frequency freqop 1.8V+0.1V @ 25°C 95 370 MHz Application Frequency Range freqApp 1.8V+0.1V @ 25°C 160 350 MHz Input clock duty cycle dtin 40 60 % CLK stabilization TSTAB 15 µs Switching Characteristics1 TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Output enable time ten OE to any output 4.73 8 ns Output disable time tdis OE to any output 5.82 8 ns Period jitter tjit (per) -30 30 ps Half-period jitter tjit(hper) -60 60 ps Input Clock 1 2.5 4 v/ns Output Enable (OE ), (OS ) 0.5 v/ns Output clock slew rate SLr1(o) 1.5 2.5 3 v/ns tjit(cc+) 04 0 p s tjit(cc-) 0 -40 ps Dynamic Phase Offset t( )dyn -20 20 ps Static Phase Offset tSPO 2 -50 0 50 ps Output to Output Skew tskew 40 ps SSC modulation frequency 30.00 33 kHz SSC clock input frequency deviation 0.00 -0.50 % PLL Loop bandwidth (-3 dB from unity gain) 2.0 MHz Cycle-to-cycle period jitter Input slew rate SLr1(i)

Figure 11. AVDD Filtering

• Place the 2200pF capacitor close to the PLL.

GND via (farthest from PLL).

• Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).

0792A—04/15/04

Ordering Information

• e -TYP b REF b REF Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) Numeric Designations for Horizontal Grid Numeric Designations for Horizontal Grid h TYP h TYP c REF c REF A B C D TOP VIEW 3 2 14 Seating Plane Seating Plane C T 0.12 C d TYP E D D1D1D1 D1 D1 - e - - e -- e - TYP TYP D E T e HORIZ VERT TOTAL d h D1 E1 b c Min/Max Min/Max Min/Max * Source Ref.: JEDEC Publication 95, 10-0055 ALL DIMENSIONS IN MILLIMETERS REF. DIMENSIONS ----- BALL GRID ----- Max. Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. MO-205*, MO-225** Example: Designation for tape and reel packaging Lead Free (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type XXXX y H LF- T

0792A—04/15/04 Example: Designation for tape and reel packaging Lead Free (Optional) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type XXXX y K LF- T Top View IndexArea E D Sawn Singulation Anvil Singulation or A 0.08 C C Seating Plane E2 E2 L (N -1)x e (Ref.) D (Ref.) N& N Even D E N e D E (Ref.) N& N Odd e (Typ.) If N & N areEven (N -1)x e (Ref.) E ED b Thermal Base N ALL DIMENSIONS IN MILLIMETERS N SYMBOL MIN. MAX. N D A 0.80 1.00 N E A1 0 0.05 D x E BASIC A3 D2 MIN. / MAX. b 0.18 0.30 E2 MIN. / MAX. e L MIN. / MAX. SPECIAL NON-JEDEC ALL DIM. SAME EXCEPT AS BELOW: 4.35 / 4.65 5.05 / 5.35 10-0053 Source Reference: MLF2™ SER THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE 0.30 / 0.50 D2 MIN. / MAX. E2 MIN. / MAX.

0.25 Reference

0.50 BASIC

6.00 x 6.00 2.75 / 3.05 2.75 / 3.05