97CFDC

97CFDC SMSC | Alldatasheet

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Technical content

SMSC DS – USB97CFDC Rev. 12/15/2000 USB97CFDC USB Floppy Disk Controller

FEATURES

/elevenoclock 3.3 Volt, Low Power Operation /elevenoclock Complete USB Specification 1.1 Compatibility - Includes USB Transceiver - Based on an Enhanced Version of SMSC’s Industry Proven USB97C100 USB Controller /elevenoclock Complete System Solution Including USB Mass Storage Class Compliant Win98/2000 Driver and Firmware - Supports 640K, 720K, 1.44M, 1.2M Windows 98 J, and 1.2M NEC DOS 6.x Formats - Supports Both the UFI and SFF8070i Command Sets - Supports USB Mass Storage Compliant Bootable Floppy BIOS - 4ms Seek Times - USB 1.1 Compliance, Including Low Power Device Class SUSPEND Mode Operation and Power Control of Disk Drive - Disk Drive Feedback of Readiness Upon Power Re-Application Option - Option for Ultra High Performance Using Additional Caching SRAM - Support for Floppy Drive Power Control /elevenoclock Contains SMSC’s Industry Proven Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Supports Single Normal or Three Mode Floppy Drives - Supports Vertical Recording Format and High Capacity Drives in User Written Firmware

Applications

• Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption /elevenoclock Enhanced Digital Data Separator - 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes /elevenoclock Intelligent Auto Power Management - <300µA SUSPEND Current - <75mA Operating Current /elevenoclock External Program Memory Interface - 32K Byte Code Space (Supplied Firmware Requires 16KB Memory) - Flash, SRAM, or EPROM Memory /elevenoclock 4KB Internal Buffer SRAM for High Performance Operation /elevenoclock Optional External Cache Memory - Up to 16K x 8 External SRAM may be Used for Custom Tape/ Drive Applications /elevenoclock Integrated 14.318 MHz Crystal Driver Circuit /elevenoclock 100 pin TQFP package (12.0 x 12.0 mm footprint) - 25% smaller body size than other 100 pin TQFP packages

ORDERING INFORMATION

Order Number: USB97CFDC-MN

100 Pin TQFP Package

SMSC DS – USB97CFDC Page 2 Rev. 12/15/2000 © STANDARD MICROSYSTEMS CORPORATION (SMSC) 2000

80 Arkay Drive

Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Micro systems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain t he latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devi ces described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and cond itions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published speci fications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life suppo rt or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

SMSC DS – USB97CFDC Page 3 Rev. 12/15/2000 GENERAL DESCRIPTION The USB97CFDC is an integration of the USB97C102 Enhanced Multi-Endpoint USB Peripheral Controller, without its integrated hub functions, and the SMSC Floppy Disk Controller used in many of its Super IO products, such as the FDC37C869. Special care in the interconnection of the two devices has been taken to assure the lowest possible system current draw (<300µA) during SUSPEND mode operation. Provisions for external Flash Memory up to 32K bytes for program storage is provided. Although not required for standard floppy operation, provisions for 16K bytes of external buffer SRAM, in addition to that included in the USB97C102 core, is also provided for extended applications, such as tape drives and for other special applications. Several pins are provided for controlling external power control elements and sensing specialized drive functions. Note: SMSC has developed and supplies firmware and drivers for this device to implement a standard three mode or dual mode Floppy Disk Drive system with drive power control. If the customer desires to develop his own firmware and/or drivers for this system, he may contact SMSC to obtain a complete engineering specification which details all the internal block functions and register maps of the USB97CFDC to allow custom programs to be written for this device.

SMSC DS – USB97CFDC Page 4 Rev. 12/15/2000 TABLE OF CONTENTS

SMSC DS – USB97CFDC Page 5 Rev. 12/15/2000 DESCRIPTION OF PIN FUNCTIONS FLOPPY DISK INTERFACE (14 Pins) nTRK0 nINDEX nWRTPRT nDSKCHG nRDATA DRVDEN0 DRVDEN1 nSTEP nWDATA nWGATE nHDSEL nDIR nDSO nMTR0 USB INTERFACE (4 Pins) USB+ USB- AVDD AGND FLASH ROM INTERFACE (26 Pins) FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FA0 FA1 FA2 FA3 FA4 FA5 FA6 FA7 FA8 FA9 FA10 FA11 FA12 FA13 FA14 FA15 nFRD nFCE SRAM/IO INTERFACE (24 Pins) SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 nMEMR nMEMW MISC (10 Pins) nMEMEN OPTEN nDRVRDY nFDPWR XTAL1/CLKIN XTAL2 nRESET nTEST TST_OUT nTESTEN POWER, GROUNDS, and NO CONNECTS (22 Pins)

SMSC DS – USB97CFDC Page 6 Rev. 12/15/2000 PIN CONFIGURATION SA10 SA9 SA8 SA7 SA6 SA5 SA4 GND SA3 SA2 SA1 SA0 SA13 VDD nTEST nTESTEN XTAL1/CLKIN XTAL2 GND N.C. nRESET TSTOUT nMEMEN OPTEN nDRVRDY USB97CFDC 1 25 5175 nRDATA nWRTPRT nTRK0 nINDEX nHDSEL nWGATE nWDATA nSTEP nDIR GND nDS0 nMTR0 DRVDEN0 AGND USB+ VDD USB- AVDD FA11 FA9 FA8 FA13 FA14 GND N.C. nDSKCHG DRVDEN1 N.C. GND N.C. GND VDD N.C. SD7 SD6 SD5 SD4 GND SD3 SD2 SD1 SD0 VDD N.C. N.C. N.C. nMEMR nMEMW SA12 SA11 FA15 FA12 FA7 FA6 FA5 FA4 FA3 GND FA2 FA1 FA0 VDD FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 nFCE FA10 nFRD GND nFDPWR

SMSC DS – USB97CFDC Page 7 Rev. 12/15/2000 BLOCK DIAGRAM Pin Descriptions PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION FLOPPY DISK INTERFACE

75 Read Disk

nRDATA IS Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data.

69 Write

nWDATA OD12 This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media.

71 Head

nHDSEL OD12 This high current output selects the floppy disk side for reading or writing. A logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed.

67 Direction

nDIR OD12 This high current low active output determines the direction of the head movement. A logic "1" on this pin means outward motion, while a logic "0" means inward motion.

68 Step Pulse nSTEP OD12 This active low high current driver issues a low

pulse for each track-to-track movement of the head.

76 Disk Change nDSKCHG IS This input senses that the drive door is open or

that the diskette has possibly been changed since the last drive selection.

8051 CPU

ControlSerial Interface Engine GPIO nMEMEN FD[7:0] nFRD nFCE Option Select/ Drive Control Flash/ SRAM Interface IRQ0 SD[7:0] SA[13:0] nIOW nIOR nMEMW nMEMR High Speed USB XCVR To USB Bus FA[15:0] FLOPPY DISK CONTROLLER DRQ2 TC nDAK2 ADDRESS DECODE nCE AEN SRAM Interface nTRK0, nINDEX, nWRTPRT, nDSKCHG nRDATA, DRVDEN0, DRVDEN1, nWDATA, nWGATE, nHDSEL, nDIR, nMTR0, nDS0, nSTEP DRIVE INTERFACE CLOCK CONTROL nOPTEN nDRVRDY nFDPWR

SMSC DS – USB97CFDC Page 8 Rev. 12/15/2000 PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION

63 DRVDEN 0 DRVDEN 0 OD12 An active low on this pin indicates a disk drive

spindle speed change from 300 RPM to 360 RPM or 1.2M format disks in three mode drives. This pin should be tied to the disk drives spindle speed control input pin. 77 DRVDEN 1 DRVDEN1 OD12 Reserved for future use.

70 Write Gate nWGATE OD12 This active low high current driver allows current to

flow through the write head. It becomes active just prior to writing to the diskette.

73 Track 0 nTRK0 IS This active low Schmitt Trigger input senses from

the disk drive that the head is positioned over the outermost track.

72 Index nINDEX IS This active low Schmitt Trigger input senses from

the disk drive that the head is positioned over the beginning of a track, as marked by an index hole.

74 Write Protect nWRTPRT IS This active low Schmitt Trigger input senses from

the disk drive that a disk is write protected. Any write command is ignored.

64 Motor On 0 nMTR0 OD12 This active low open drain output selects motor

drive 0. 65 Drive Select 0 nDS0 OD12 This active low open drain output selects drive 0. USB INTERFACE USB Bus Data USB- USB+ IO-U These pins connect to the USB data signals through 33 ohm series resistors. The USB+ line should be pulled up with a 5%, 1.5K ohm resistor to indicate that this is a high speed USB device.

58 USB

AVDD This is the 3.3V supply to the internal USB transceiver.

62 USB

AGND This is the supply ground for the internal USB transceiver. FLASH INTERFACE 31-38 Flash Memory Data Bus FD[7:0] IO8 These signals are used to transfer data between the internal 8051 and the external FLASH program memory. 50, 53, 54, 49, 57, 29, 56, 55, 48- 44, 42-40, Flash Memory Address Bus FA[15:0] O8 These signals address memory locations within the FLASH memory.

28 Flash Memory

nFRD O8 Flash ROM Read; active low

30 Flash Memory

nFCE O8 Flash ROM Chip Select; active low SRAM/IO INTERFACE 1-7, 9-13, 99,100 SRAM Memory Bus SA[13:0] O8 These signals provide the memory address to an external SRAM buffer. 84-87, 89-92 SRAM Memory Data Bus SD[7:0] I/O8 These signals are used to transfer data to/from the SRAM Memory.

97 SRAM

nMEMR O8 Memory read; active low This active low signal indicates that data is to be driven onto the data bus by the SRAM. Data will be latched internal to the chip on the rising edge of this signal

98 SRAM

nMEMW O8 Memory write; active low This active low signal indicates to the SRAM to load data from the data bus on its rising edge.

SMSC DS – USB97CFDC Page 9 Rev. 12/15/2000 PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION MISCELLANEOUS

17 Crystal

ICLKx 14.318Mhz Crystal or clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 14.318Mhz clock when a crystal is not used.

18 Crystal

XTAL2 OCLKx 14.318Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit.

23 SRAM Enable nMEMEN O24 An active low signal is output on this pin to enable

the optional external SRAM for extended FDC write and read caching for ultra high performance applications.

24 Option Enable OPTEN I Current firmware utilizes this input pin for

detecting the media density switch of the drive. Various firmware options are available for different polarities of this signal. Contact factory for available firmware options. If this pin is not driven by the drive, it should be tied low.

25 Drive Ready nDRVRDY I An active low signal on this pin from the floppy

disk drive, after DS0 goes active, indicates that the system may activate MTR0. If the drive does not supply this signal, this pin should be tied low.

26 Drive Power nFDPWR OD24 This active low signal is intended to activate an

external power switch, either in the drive or on the system board, to supply power to the floppy disk drive. It is active whenever the USB97CFDC is not in SUSPEND mode.

21 RESET input nRESET IS This active low signal is used by the system to

reset the chip. The active low pulse should be at least 100ns wide.

22 Test output TSTOUT O8 This signal is used for testing the chip via an

internal XNOR chain. User should normally leave it unconnected. 15 Test input nTEST I This signal is a manufacturing test pin. It should be tied to VDD for normal operation.

16 Test Enable nTESTEN I This active low signal places the device into board

test mode using the XNOR chain. For normal operation this pin should be tied high. See Board Test Mode Operation on page 10 POWER, GROUND, AND NO CONNECTS 14, 39, 60, 82, 93 VDD +3.3V power 8, 19, 27, 43, 52, 66, 79, 81, 88 GND Ground Reference 20, 51, 78, 80, 83, 94-96 NC No Connect. These pins should not be connected externally.

SMSC DS – USB97CFDC Page 10 Rev. 12/15/2000 BUFFER TYPE DESCRIPTIONS Table 1 - USB97CFDC Buffer Type Descriptions BUFFER DESCRIPTION I Input IS Input with Schmitt trigger O8 Output with 8mA drive I/O8 Input/output with 8mA drive OD12 Open drain….12mA sink O24 Output with 24mA drive OD24 Open drain….24mA sink ICLKx XTAL clock input OCLKx XTAL clock output I/O-U See Table 6. BOARD TEST MODE OPERATION By driving the nTESTEN pin low, the device will be placed into a special test mode to allow verification of attachment of the device to the circuit board. Every pin except the TSTOUT, XTAL2, and the power and ground pins become an input to an XNOR chain, as shown below, to allow continuity to be tested on the board. This test should individually toggle the state of the trace connected to the pin being examined for continuity, and the TSTOUT pin monitored for toggle of state. If no toggle occurs, either the pin under test is discontinuous, or the TSTOUT pin is not connected on the board Pin1 Pin2 Pin3 Pin100 TSTOUT

SMSC DS – USB97CFDC Page 11 Rev. 12/15/2000 DC PARAMETERS MAXIMUM GUARANTEED RATINGS Note 1: Maximum voltage on all I type Inputs and the IS inputs, OD12 and OD24 outputs for floppy disk drive interface is 5.25V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 2: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (T PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS I Type Input Buffer Low Input Level High Input Level V ILI VIHI 2.0 0.8 V V TTL Levels ICLK Input Buffer Low Input Level High Input Level V ILCK VIHCK 2.2 0.4 V V Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage I IL IIH -10 -10 +10 +10 uA uA VIN = 0 VIN = VCC O8 Type Buffer Low Output Level High Output Level Output Leakage V OL VOH IOL 2.4 -10 0.4 +10 V V UA IOL = 8 mA IOH = -4 mA VIN = 0 to VCC (Note 1) I/O8 Type Buffer Low Output Level High Output Level Output Leakage V OL VOH IOL 2.4 -10 0.4 +10 V V µA IOL = 8mA IOH = -4mA VIN = 0 to Vcc (Note 1) OD12 Type Buffer Low Output Level Output Leakage V OL IOL -10 0.4 +10 V µA IOL = 12mA VIN = 0 to Vcc (Note 1)

SMSC DS – USB97CFDC Page 12 Rev. 12/15/2000 PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS O24 Type Buffer Low Output Level High Output Level Output Leakage V OL VOH IOL 2.4 -10 0.4 +10 V V µA IOL = 24mA IOH = -12mA VIN = 0 to Vcc (Note 1) OD24 Type Buffer Low Output Level Output Leakage V OL IOL -10 0.4 +10 V µA IOL = 24mA VIN = 0 to Vcc (Note 1) IO-U Note 2 Supply Current Active Supply Current Standby I CC ICSBU 120 300 MA µA All outputs open. Note 1: Output leakage is measured with the current pins in high impedance. Note 2: See Appendix A for USB DC electrical characteristics. CAPACITANCE TA = 25°C; fc = 1MHz; VCC = 3.3V LIMITS PARAMETER SYMBOL MIN TYP MAX UNIT TEST CONDITION Clock Input Capacitance C IN 20 pF Input Capacitance C IN 10 pF Output Capacitance C OUT 20 pF All pins except USB pins (and pins under test tied to AC ground) AC PARAMETERS CLOCKI FIGURE 1 - INPUT CLOCK TIMING Table 2 – Input Clock Timing Parameters NAME DESCRIPTION MIN TYP MAX UNITS t1 Clock Cycle Time for 14.318MHz 69.84 ns t2 Clock High Time/Low Time for 24MHz 41.9/ 27.9 27.9/ 41.9 ns tr, tf Clock Rise Time/Fall Time (not shown) 5 ns

SMSC DS – USB97CFDC Page 15 Rev. 12/15/2000 USB PARAMETERS The following tables and diagrams were obtained from the USB specification USB DC PARAMETERS 0.0 0.2 0.4 0.6 0.8 1.0 Common Mode Input Voltage (volts) Minimum Differential Sensitivity (volts) FIGURE 6 - DIFFERENTIAL INPUT SENSITIVITY OVER ENTIRE COMMON MODE RANGE Table 6 - DC Electrical Characteristics PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) MIN TYP MAX UNIT Supply Voltage Powered (Host or Hub) Port VBUS 4.4 5.25 V Supply Current Function ICC Note 4 100 mA Un-configured Function (in) ICCINIT Note 5 100 uA Suspend Device ICCS 100 uA Leakage Current Hi-Z State Data Line Leakage ILO 0 V < VIN < 3.3 V -10 10 uA Input Levels Differential Input Sensitivity VDI |(D+) - (D-)|, and FIGURE 6 0.2 V Differential Common Mode Range VCM Includes VDI range 0.8 2.5 V Single Ended Receiver Threshold VSE 0.8 2.0 V Output Levels Static Output Low VOL RL of 1.5 KΩ to 3.6 V 0.3 (3) V Static Output High VOH RL of 15 KΩ to GND 2.8 3.6 (3) V Capacitance Transceiver Capacitance CIN Pin to GND 20 pF Terminals Bus Pull-up Resistor on Root Port Bus Pull-down Resistor on Downstream Port RPD (15 KΩ +/- 5%) 14.25 15.75 kΩ Note 1: All voltages are measured from the local ground potential, unless otherwise specified. Note 2: All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified. Note 3: This is relative to VUSBIN. Note 4: This is dependent on block configuration set by software. Note 5: When the internal ring oscillator and waiting for first setup packet.

SMSC DS – USB97CFDC Page 18 Rev. 12/15/2000 MECHANICAL OUTLINE FIGURE 11 - 100 PIN TQFP PACKAGE MIN NOMINAL MAX REMARK A ~ ~ 1.60 Overall Package Height A1 0.05 ~ 0.15 Standoff A2 1.35 1.40 1.45 Body Thickness D 13.80 14.00 14.20 X Span D/2 6.90 7.00 7.10 1/2 X Span Measure from Centerline D1 11.80 12.00 12.20 X body Size E 13.80 14.00 14.20 Y Span E/2 6.90 7.00 7.10 1/2 Y Span Measure from Centerline E1 11.80 12.00 12.20 Y body Size H 0.09 ~ 0.20 Lead Frame Thickness L 0.45 0.60 0.75 Lead Foot Length from Centerline L1 ~ 1.00 ~ Lead Length e 0.40 Basic Lead Pitch 0 o 3.5o 7o Lead Foot Angle W 0.13 0.16 0.23 Lead Width R1 0.08 ~ ~ Lead Shoulder Radius R2 0.08 ~ 0.20 Lead Foot Radius ccc ~ ~ 0.08 Coplanarity Note 1: Controlling Unit: millimeter Note 2: Minimum space between protrusion and an adjacent lead is .007 mm. Note 3:Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated.

SMSC DS – USB97CFDC Page 19 Rev. 12/15/2000 APPENDIX A: USB97CFDC TYPICAL APPLICATION G USB97CFDC Typical Application B 11Wednesday, December 13, 2000 Title Size Document Number Rev Date: Sheet of VCC VCC FVDD VCC FVDD VDD VCC FVDD FVDD nDRVRDY HDO VDD nFDPWR VDD HDO nDRVRDY VDD VDD nFDPWR TP2 C12 .1uF TP3 15K 1.5K 1µf RN1 1K x 5 28F256 A10 A11 A12 A13 A14 CE OE WE VPP NC NC NC .1uF .1uF C10 .1uF VR1 3.3V Regulator 3 2 GND VIN VOUT 39pf 15pf #1.2M #HHDOUT #DSKSTAT #MTR0 #DS1 #DS0 #MTR1 #DIR #INDEX #WDATA #WGATE #TRK0 #WP #RDATA #HDSEL #DSKCHG #STEP JP1 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 USB97CFDC 100 SA10 SA9 SA8 SA7 SA6 SA5 SA4 GND SA3 SA2 SA1 SA0 SA13 VDD nTEST VDD XTAL1/CLKIN XTAL2 GND N.C. nRESET TSTOUT nMEMEN OPTEN nDRVRDY FA12 FA7 FA6 FA5 FA4 FA3 GND FA2 FA1 FA0 VDD FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 nFCE FA10 nFRD GND nFDPWR nRDATA nWRTPRT nTRK0 nINDEX nHDSEL nWGATE nWDATA nSTEP nDIR GND nDS0 nMTR0 DRVDEN0 AGND USB+ VDD USB- AVDD FA11 FA9 FA8 FA13 FA14 GND N.C.nDSKCHG DRVDEN1 N.C. GND N.C. GND VDD N.C. SD7 SD6 SD5 SD4 GND SD3 SD2 SD1 SD0 VDD N.C. N.C. N.C. nMEMR nMEMW SA12 SA11 FA15 MOSFET P RN2 10K x 8 USB TYPE B VCC GND + C6 10uF C13 .1uF 10K 1/10W 180K TP1 C11 .1uF C14 .1uF .1uF + C5 10uF .1uF 14.318Mhz R1 10ohm R2 10ohm FLOPPY Note: IF DRIVE DOES NOT SUPPLY nDRVRDY OR HDO SIGNAL, THEY SHOULD BE TIED LOW AT Note: If SD pins not used, tie to ground to prevent pins from floating during suspend mode.

SMSC DS – USB97CFDC Page 20 Rev. 12/15/2000 SMSC PROVIDED SOFTWARE FOR USB97CFDC SMSC provides the following for the USB97CFDC: I. Program firmware with the following features: (b) Supports USB Mass Storage Class compliant drivers from Apple and Microsoft as well as SMSC’s Windows 98 driver. (c) Supports USB Mass Storage compliant bootable floppy BIOS. (d) 4ms Seek times. (e) USB 1.1 compliance, including low power device class SUSPEND mode operation and power control of disk drive. (f) Disk drive feedback of readiness upon power re-application (optional). (g) Option for using drive media density sense output (HDO#) pin to prevent attempts to format 2DD disks as 2HD. II. USB Mass Storage Class compliant driver for Windows 98. USB97CFDC REVISIONS PAGE(S) SECTION/FIGURE/ENTRY CORRECTION DATE REVISED

19 USB97CFDC TYPICAL

Updated schematic 12/15/00 Updated schematic 11/01/00