CSD97374Q4M_15 TI1 | Alldatasheet
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Output Current (A) Efficiency (%) Power Loss (W) VGS = 5V VIN = 12V VOUT = 1.8V LOUT = .29µH fS W = 500kHz TA = 25ºC G001 CSD97374Q4M www.ti.com SLPS382C –JANUARY 2013–REVISED JULY 2013 Synchronous Buck NexFET™ Power Stage 1FEATURES APPLICATIONS 23• Over 92% System Efficiency at 15A • Ultrabook/Notebook DC/DC Converters
- Max Rated Continuous Current 25A, Peak 60A • Multiphase Vcore and DDR Solutions
- High Frequency Operation (up to 2 MHz) • Point-of-Load Synchronous Buck in Networking, Telecom, and Computing Systems• High Density - SON 3.5x4.5-mm Footprint
- Ultra Low Inductance Package ORDERING INFORMATION
- System Optimized PCB Footprint Device Package Media Qty Ship
- Ultra Low Quiescent (ULQ) Current Mode SON 3.5 × 4.5-mm 13-Inch Tape andCSD97374Q4M 2500Plastic Package Reel Reel
- 3.3V and 5V PWM Signal Compatible
- Diode Emulation Mode with FCCM
- Input Voltages up to 24V
- Three-State PWM Input
- Integrated Bootsrap Diode
- Shoot Through Protection
- RoHS Compliant – Lead Free Terminal Plating
- Halogen Free
DESCRIPTION
The CSD97374Q4M NexFET™ Power Stage is a highly optimized design for use in a high power, high density Synchronous Buck converter. This product integrates the driver IC and NexFET technology to complete the power stage switching function. The driver IC has a built-in selectable diode emulation function that enables DCM operation to improve light load efficiency. In addition, the driver IC supports ULQ mode that enables Connected Standby for Windows™ 8 . With the PWM input in tri-state, quiescent current is reduced to 130 µA, with immediate response. When SKIP# is held at tri-state, the current is reduced to 8 µA (typically 20 µs is required to resume switching). This combination produces a high current, high efficiency, and high speed switching device in a small 3.5 × 4.5-mm outline package. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design. Figure 1. Application Diagram Figure 2. Efficiency and Power Loss Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2NexFET is a trademark of Texas Instruments. 3All other trademarks are the property of their respective owners. necessarily include testing of all parameters.
SLPS382C –JANUARY 2013–REVISED JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) TA = 25°C (unless otherwise noted) VALUE UNIT MIN MAX VIN to PGND -0.3 30 V VSW to PGND , VIN to VSW -0.3 30 V VSW to PGND , VIN to VSW (<10ns) -7 33 V VDD to PGND –0.3 6 V PWM, SKIP# to PGND –0.3 6 V BOOT to PGND –0.3 35 V BOOT to PGND (<10ns) -2 38 V BOOT to BOOT_R –0.3 6 V Human Body Model (HBM) 2000 V ESD Rating Charged Device Model (CDM) 500 V Power Dissipation, PD 8 W Operating Temperature Range, TJ -40 150 °C Storage Temperature Range, TSTG –55 150 °C (1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS TA = 25° (unless otherwise noted) Parameter Conditions MIN MAX UNIT Gate Drive Voltage, VDD 4.5 5.5 V Input Supply Voltage, VIN 24 V Continuous Output Current, IOUT VIN = 12V, VDD = 5V, VOUT = 1.8V, 25 A fSW = 500kHz, LOUT = 0.29µH(1) Peak Output Current, IOUT-PK (2) 60 A Switching Frequency, fSW C BST = 0.1µF (min) 2000 kHz On Time Duty Cycle 85 % Minimum PWM On Time 40 ns Operating Temperature –40 125 °C (1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins. (2) System conditions as defined in Note 1. Peak Output Current is applied for tp = 10ms, duty cycle≤ 1% THERMAL INFORMATION TA = 25°C (unless otherwise noted) PARAMETER MIN TYP MAX UNIT R θJC Thermal Resistance, Junction-to-Case (Top of package)(1) 22.8 °C/W R θJB Thermal Resistance, Junction-to-Board(2) 2.5 °C/W (1.52-mm) thick FR4 board. (2) R θJB value based on hottest board temperature within 1mm of the package.
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Not Recommended For New Designs
www.ti.com SLPS382C –JANUARY 2013–REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = POR to 5.5V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT PLOSS VIN = 12V, VDD = 5V, VOUT = 1.8V, IOUT = 15A,Power Loss(1) 2.3 WfSW = 500kHz, LOUT = 0.29µH , TJ = 25°C VIN = 19V, VDD = 5V, VOUT = 1.8V, IOUT = 15A,Power Loss(2) 2.5 WfSW = 500kHz, LOUT = 0.29µH , TJ = 25°C VIN = 19V, VDD = 5V, VOUT = 1.8V, IOUT = 15A,Power Loss(2) 2.8 WfSW = 500kHz, LOUT = 0.29µH , TJ = 125°C VIN VIN Quiescent Current, IQ PWM=Floating, VDD = 5V, VIN= 24V 1 µA VDD PWM = Float, SKIP# = VDD or 0V 130 µA Standby Supply Current, IDD SKIP# = Float 8 µA Operating Supply Current, IDD PWM = 50% Duty cycle, fSW = 500kHz 8.2 mA POWER-ON RESET AND UNDER VOLTAGE LOCKOUT Power-On Reset, VDD Rising 4.15 V UVLO, VDD Falling 3.7 V Hysteresis 0.2 mV PWM and SKIP# I/O Specifications Pull Up to VDD 1700 Input Impedance, RI kΩ Pull Down (to GND) 800 Logic Level High, VIH 2.65 Logic Level Low, VIL 0.6 V Hysteresis, VIH 0.2 Tri-State Voltage, VTS 1.3 2 Tri-state Activation Time (falling) PWM, 60tTHOLD(off1) ns Tri-state Activation Time (rising) PWM, 60tTHOLD(off2) Tri-state Activation Time (falling) SKIP#, 1tTSKF µs Tri-state Activation Time (rising) SKIP#, 1tTSKR Tri-state Exit Time PWM, t3RD(PWM) (2) 100 ns Tri-state Exit Time SKIP#, t3RD(SKIP#) (2) 50 µs BOOTSTRAP SWITCH Forward Voltage, VFBST IF = 10mA 120 240 mV Reverse Leakage, IRLEAK (2) VBST – VDD = 25V 2 µA (1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins. (2) Specified by design Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Not Recommended For New Designs
TJ = 125°C, unless stated otherwise. Figure 3. Power Loss vs Output Current Figure 4. Power Loss vs Temperature Figure 5. Safe Operating Area – PCB Horizontal Mount(1) Figure 6. Typical Safe Operating Area(1) Figure 7. Normalized Power Loss vs Frequency Figure 8. Normalized Power Loss vs Input Voltage
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SKIP# VSW VDD PGND BOOT BOOT_R CSD97374Q4M SLPS382C –JANUARY 2013–REVISED JULY 2013 www.ti.com PIN CONFIGURATION Figure 13. Top View NO. NAME 1 SKIP# This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the Sync FET. When SKIP# is High, the CSD97374Q4M operates in Forced Continuous Conduction Mode. A tri-state voltage on SKIP# puts the driver into a very low power state. 2 V DD Supply Voltage to Gate Drivers and internal circuitry.
3 P GND Power Ground, Needs to be connected to Pin 9 and PCB
4 V SW Voltage Switching Node – pin connection to the output inductor. 5 V IN Input Voltage Pin. Connect input capacitors close to this pin. 6 BOOT_R Bootstrap capacitor connection. Connect a minimum 0.1µF 16V X5R, ceramic cap from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.7 BOOT 8 PWM Pulse Width modulated 3-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if greater than the 3-State Shutdown Hold-off Time (t3HT )
9 P GND Power Ground
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Not Recommended For New Designs
incorporates a weak pull-up to maintain the voltage within the tri-state window during low-power modes. Operation into and out of tri-state mode follows the timing diagram outlined inFigure 16. (typical) and 5 V (typical) PWM drive signals. pin. Normal operation requires this time period in order for the auto-zero comparator to resume. Figure 16. PWM Tri-State Timing Diagram current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs. Table 1shows the logic functions of UVLO, PWM, SKIP#, the Control FET Gate and the Sync FET Gate. Table 1. Logic Functions of the Driver IC (1) Until zero crossing protection occurs.
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www.ti.com SLPS382C –JANUARY 2013–REVISED JULY 2013 Zero Crossing (ZX) Operation The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy load condition, the inductor current also reduces and eventually arrives at avalley, where it touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the rectifying MOSFET. Integrated Boost-Switch To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL signal. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Not Recommended For New Designs
SLPS382C –JANUARY 2013–REVISED JULY 2013 www.ti.com
APPLICATION INFORMATION
The Power Stage CSD97374Q4M is a highly optimized design for synchronous buck applications using NexFET devices with a 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance in the actual application. Power Loss Curves MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves.Figure 3plots the power loss of the CSD97374Q4M as a function of load current. This curve is measured by configuring and running the CSD97374Q4M as it would be in the final application (seeFigure 17). The measured power loss is the CSD97374Q4M device power loss which consists of both input conversion loss and gate drive loss.Equation 1is used to generate the power loss curve. Power Loss = (VIN x IIN) + (VDD x IDD ) – (VSW_AVG x IOUT ) (1) The power loss curve inFigure 3is measured at the maximum recommended junction temperature of TJ = 125°C under isothermal test conditions. Safe Operating Curves (SOA) The SOA curves in the CSD97374Q4M datasheet give engineers guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss.Figure 5and Figure 6 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with Normalized Curves The normalized curves in the CSD97374Q4M data sheet give engineers guidance on the Power Loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve. Figure 17. Power Loss Test Circuit
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The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).
- Typical Power Loss at 15A = 2.8W (Figure 3)
- Normalized Power Loss for switching frequency≈ 1.02 (Figure 7)
- Normalized Power Loss for input voltage≈ 1.07 (Figure 8)
- Normalized Power Loss for output voltage≈ 0.94(Figure 9)
- Normalized Power Loss for output inductor≈ 1.08 (Figure 10) Calculating SOA Adjustments
- SOA adjustment for switching frequency≈ 0.3°C (Figure 7)
- SOA adjustment for input voltage≈ 1.2°C (Figure 8)
- SOA adjustment for output voltage≈ –1.1°C (Figure 9)
- SOA adjustment for output inductor≈ 1.4°C (Figure 10)
Figure 18. Power Stage CSD97374Q4M SOA graphically shows how the SOA curve would be adjusted accordingly.
- Start by drawing a horizontal line from the application current to the SOA curve.
- Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
- Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
would yield an increase in allowable board/ambient temperature.
is a brief description on how to address each parameter. taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.
- The placement of the input capacitors relative to VIN and PGND pins of CSD97374Q4M device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (seeFigure 19). The example inFigure 19uses 1 x 1nF 0402 25V and 3 x 10µF 1206 25V ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Stage C5, C8 and C6, C19 should follow in order.
- The bootstrap cap CBOOT 0.1µF 0603 16V ceramic capacitor should be closely connected between BOOT and BOOT_R pins
- The switching node of the output inductor should be placed relatively close to the Power Stage CSD97374Q4M V SW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level.(2) Thermal Performance The CSD97374Q4M has the ability to use the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:
- Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
- Use the smallest drill size allowed in your design. The example inFigure 19uses vias with a 10 mil drill hole and a 16 mil capture pad.
- Tent the opposite side of the via with solder-mask. In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.
Figure 19. Recommended PCB Layout (Top Down View)
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0.300 (x4 5°) CSD97374Q4M www.ti.com SLPS382C –JANUARY 2013–REVISED JULY 2013 MECHANICAL DATA MILLIMETERS INCHES DIM Min Nom Max Min Nom Max e 0.400 TYP 0.016 TYP K 0.300 TYP 0.012 TYP Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Not Recommended For New Designs
0.600 (x 2) .024) 0.225 ( x 2) 2.200 (0.087) .009) 0.850 (x8) 0.300 0.200 0.200 0.390 0.350 0.225 2.200 0.115 (0.029) (0.015) (0.012) (0.014) (0.009) (0.087) (0.004) 0.400 .016) 0.200 .008) 0.300 .012) (0.033) 0.200 .008) 0.440 (0.017) R0.100 R0.100 0.250 (x18) .010) 0.150 .006) 0.600 (x 2) .024) 0.200 (x2 2.250 0.225 ( x 2) 4.050 2.200 0.300 .008) (0.087) (0.012) (0.088) (0.009) (0.159) 0.150 .006) 0.400 .016) 0.440 (0.017) R0.100R0.100 RECOMMENDED PCB PATTERN CSD97374Q4M SLPS382C –JANUARY 2013–REVISED JULY 2013 www.ti.com Recommended PCB Land Pattern Recommended Stencil Opening NOTE: Dimensions are in mm (inches).
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Not Recommended For New Designs
www.ti.com SLPS382C –JANUARY 2013–REVISED JULY 2013
REVISION HISTORY
Changes from Original (January 2013) to Revision A Page
- Changed the ROC table, From: VSW to PGND , VIN to VSW (<20ns) MIN = -5 To: VSW to PGND , VIN to VSW (<10ns) MIN Changes from Revision A (March 2013) to Revision B Page Changes from Revision B (May 2013) to Revision C Page Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 15 Not Recommended For New Designs
www.ti.com 2-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CSD97374Q4M NRND VSON-CLIP DPC 8 2500 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 150 97374M FX021 NRND VSON-CLIP DPC 8 2500 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 150 97374M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 2-Apr-2015 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant CSD97374Q4M VSON- CLIP PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD97374Q4M VSON-CLIP DPC 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2014 Pack Materials-Page 2
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