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Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 24

Technical content

Features

  • Wide input voltage range from 4.5V to 16V
  • Adjustable output voltages wi th continuous output current up to 4A
  • 1% accuracy over temperature and V CC range
  • Built-in low-power LDO for external µC
  • B u i l t - i n c o m p e n s a t i o n
  • Internally set SS and OCP
  • Independent enable, power-good and standby control inputs for each output
  • Innovative R4™ Modulator
  • Boot undervoltage detection

Applications

  • General purpose, point-of-load DC/DC power conversion
  • Notebook, netbook and tablet
  • Embedded computing system Related Literature
  • See AN1743 “Wide VIN Dual Integrated Buck Regulator With 4A/4A Continuous Output Current and LDOs”

FIGURE 1. EFFICIENCY vs LOAD, V IN = 12V, TA = +25°C FIGURE 2. R3™ vs R4™ IDEALIZED TRANSIENT RESPONSE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil (and design) and R3 and R4 technologies are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 FN7893.1 January 22, 2015 Submit Document Feedback Table of Contents

3 FN7893.1 January 22, 2015 Submit Document Feedback Pin Configuration ISL95901 (46 LD QFN) TOP VIEW PHASE1 BOOT1 LDO3P3 MODE VSIN2 VCC EN2 45 44 43 42 14 15 16 17 PAD1 BYP3P3 VSIN1 GND VIN1 PHASE1 PHASE2 VIN1 PHASE1 EN1 BOOT2 PHASE2 VIN2 FB2 STB2 41 40 VIN FB1 FS PG1 LDO5 BYP5 VIN1 GND PGND1 PGND1 10 PHASE1 VIN2 VIN2 PHASE2 PHASE229

27 PGND2

24 PGND2

PIN NUMBER SYMBOL PIN DESCRIPTION 1 FS Buck switching frequency selection. Tie to high for 1MHz, float for 500kHz, tie to GND for 300kHz. 2 VSIN1 Sensing for output of Switching Mode Power Supply 1 -SMPS1. Must be connected to channel 1 output side of inductor. 3 FB1 SMPS1 feedback input. Connect FB1 to a resistive volt age divider from SVIN1 to GND1 to adjust the output from 0.8V to 5.5V. 4, 33, PAD1 GND Analog ground for buck controllers and LDOs. Ke lvin connect GND to the negative terminal of SMPS1/2. For optimal thermal performance, place as many vias as possible under PAD1 and connecting to GND plane. 5 EN1 SMPS1 controller enable input. PWM controller is held off when pin is pulled to ground. When voltage on this pin rises above 1.4V, PWM controller is enabled. 6 BOOT1 Floating bootstrap supply pin for power MOSFET gate driver. Bootstrap capacitor provides necessary charge to turn on high-side internal N-channel MOSFET of channel 1. Connect an external capacitor from this pin to PHASE1. 7, 8, 14, 18, PAD2 PHASE1 Switch node output of channel 1. Connects source of internal power MOSFETs with external output inductor. Connect exposed PAD2 as close to inductor of SMPS1 as possible. 9, 10, 11, 12, 13 PGND1 Power ground of SMPS1.

4 FN7893.1 January 22, 2015 Submit Document Feedback 15, 16, 17 VIN1 Input supply for power stage of SMPS1 regula tor and source for internal linear regulator, LDO. For decoupling, place a minimum of 10µF ceramic capacitance from VIN1 to PGND1 and close to IC. 19, 23, 29, 30, PAD3 PHASE2 Switch node output of channel 2. Connects source of internal power MOSFETs with external output inductor. Connect exposed PAD3 as close to inductor of SMPS2 as possible. 20, 21, 22 VIN2 Input supply for power stage of SMPS2 regu lator. For decoupling, place a minimum of 10µF ceramic capacitance from VIN2 to PGND2 and close to the IC. 24, 25, 26, 27, PGND2 Power ground of SMPS2. 31 BOOT2 Floating bootstrap supply pin for power MOSFET gate driver. Bootstrap capacitor provides necessary charge to turn on high-side internal N-channel MOSFET of channel 2. Connect an external capacitor from this pin to PHASE2. 32 EN2 SMPS2 controller enable input. PWM controller is he ld off when pin is pulled to ground. When voltage on this pin rises above 1.4V, PWM controller is enabled. 34 FB2 SMPS2 feedback Input. Connect FB2 to a resistive voltage divider from SVIN2 to GND2 to adjust the output from 0.8V to 5.5V. 35 VSIN2 Sensing for output of SMPS2. Must be co nnected to channel 2 output side of inductor. 36 STB2 Standby output 2 enable input. Standby output 2 is held off when pin is pulled to ground. When voltage on this pin rises above 1.4V, standby output 2 controller is enabled. 37 PG2 Open drain power-good of SMPS2. Pulled to ground wh en output voltage is below regulation limits or during soft-start interval. Contains an internal 5MΩ pull-up resistor. 38 VSOUT2 Standby output 2. There is a switch between VSIN2 and VSOUT2. 39 BYP5 Connect BYP5 to 5V buck output or external 5V source, this will allow IC to disable VCC and LDO5, then the power source will be drawn from BYP5 to minimize internal power dissipation. Tie to GND if not use. 40 VCC Voltage bias for gate drivers as we ll as all other control circuitries. Power on or off by VIN. Decouple with at least 1µF of an MLCC capacitor across VCC and PAD1. 41 VIN Input LDO3P3, LDO5 and VCC. For decoupling, plac e a minimum of 1µF ceramic capacitance close to IC. 42 LDO5 5V linear regulator output. Power on or off by VI N. Can provide a total of 100mA external loads. Bypass LDO5 output with a minimum of 4.7µF ceramic. 43 BYP3P3 Connect BYP3P3 to 3.3V buck output or external 3. 3V source, this will allow IC to disable LDO3P3, then the power source will be drawn from BYP3P3 to minimize internal power dissipation. Tie to GND if not used. 44 MODE Mode selection pin. Connect to logic high or VCC for PWM mode. Connect to logic low or ground for DCM mode. An internal 5MΩ pull-down resistor prevents undefined logic state in case of MODE pin float. 45 LDO3P3 3.3V linear regulator output. Power on or off by VIN. Can provide a total of 100mA external loads. Bypass LDO3P3 output with a minimum of 4.7µF ceramic. 46 PG1 Open drain power-good of SMPS1. Pulled to ground when output voltage is below regulation limits or during soft-start interval. Contains an internal 5MΩ pull-up resistor. Pin Descriptions (Continued) PIN NUMBER SYMBOL PIN DESCRIPTION

Ordering Information

(Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISL95901IRZ 95901 IRZ -40 to +85 46 Ld QFN L46.5x6 ISL95901EVAL1Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95901. For more information on MSL please see Tech Brief TB363.

FIGURE 3. DUAL 4A OUTPUT AT 1MHz (V IN RANGE FROM 4.5V TO 16V)

6 FN7893.1 January 22, 2015 Submit Document Feedback Functional Block Diagram BOOT2 PHASE2 POR DIGITAL +150° DRIVER PWM CONTROL VSIN2 +CR PWM FREQUENCY CONTROL +gm +gm DRIVER SOFT-OVP- EN2 FB2 VREF UVP- OCP- PGND1 PG2 OT BOOT1 PHASE1 +150° DRIVER PWM CONTROL + CR PWM FREQUENCY CONTROL +gm +gm DRIVER OVP- EN1 UVP- OCP- PG1 OT PACKAGE BOTTOMGND START POR DIGITAL SOFT- START PGND2 VCC VCC VIN1 VIN2 VIN1 1.15%*VREF 0.85%*VREF VREF VCC VCC5M 5M VCC VIN1 EA FB1 VR1VR2 LDO5 LDO5 VSIN1 VSOUT2 LOGIC VIN STB2 NOCP- NOCP- + VREF MODE MODE R4™ MODULATOR 100Ω SD SD SD VR2VR1 PHASE2 4.65V BYP5 PHASE1 R4™ MODULATOR BIAS VCC PACKAGE BOTTOMGND LDO3 LDO3P3 3.1V BYP3P3 FS VSIN1 EA

7 FN7893.1 January 22, 2015 Submit Document Feedback Absolute Maximum Ratings Thermal Information -2V to 19V (100ns) ESD Rating Thermal Resistance  JA (°C/W) JC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications VIN = 4.5V to 16V, unless otherwise noted. Typical values are at TJ = +25°C. Boldface limits apply across the junction temperature range, -40°C to +125°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6)T Y P MAX (Note 6)U N I T S SUPPLY VOLTAGE V IN Voltage Range V IN 4.5 16 V VIN Quiescent Supply Current I Q MODE = 0V, IVSIN1/2 = 0A, ISOUT2 = 0A BYP5 = 5V 0.8 mA FB1/2 = 0.9V 1.2 1.6 mA VIN Shutdown Supply Current I SD EN1/2 = 0V 120 200 µA VCC Voltage V CC VIN = 12V; IOUT = 0mA, BYP5 = 0V, 6V < VIN <1 6 V 4.9 5.25 5.6 V LDO LDO5 V IN = 12V, BYP5 = 0V, 0mA < ILDO5 < 100mA 4.90 5.0 5.12 V LDO3P3 BYP3P3 = 0V, 0mA < ILDO3P3 < 100mA 3.23 3.32 3.4 V LDO5/LDO3P3 Output Short Current I OUTLDO 150 425 mA Reference Voltage V REF 0.792 0.8 0.808 V BYP5 Threshold Voltage Rising Edge 4.65 4.75 V Falling Edge 4.40 4.50 V BYP3P3 Threshold Voltage Rising Edge 3.1 3.2 V Falling Edge 2.9 3V BYP3P3 ON-resistance 2.2 4.2 Ω BYP5 ON-resistance 1.2 2.2 Ω POWER-ON RESET V CC POR Threshold Rising Edge 3.9 4.25 V Falling Edge 3.25 3.7 V Soft-Start Ramp Time EN1/2 = V IN 2 3 4 ms

8 FN7893.1 January 22, 2015 Submit Document Feedback Switching Frequency f SW FS = High 0.8 1.0 1.2 MHz FS = Float 400 500 600 kHz FS = GND 240 300 360 kHz OUTPUT REGULATION FB1/2 Leakage Current -200 1 200 nA POWER-GOOD OVP PG1/2 Trip Level Rise 115 118 % Fall 108 112 % UVP PG1/2 Trip Level Rise 90 93 % Fall 83 87 % PG1/2 Propagation Delay 20 µs PG1/2 Low Voltage I SINK = 3mA, PG1/2 = 0V 100 300 mV PG1/2 Leakage Current PG1/2 = 0V 1 1.5 µA PG1/2 Leakage Current PG1/2 = 5V 0.02 0.6 µA ENABLE, MODE, STB2 and FS INPUT EN1/2, STB2 Leakage Current EN1/2 = 0V/5V, STB2 = 0V/5V -0.2 0.01 0.2 µA MODE Leakage Current MODE = 0V -0.2 0.01 0.2 µA MODE = 5V 0.8 1 1.2 µA EN1/2, MODE, STB2 Input Threshold Voltage Low Level 0.40 V High Level 1.40 V FS Voltage Threshold Low Level 0.84 0.92 1 V Float Level 1.14 1.2 1.26 V High Level 1.76 1.81 1.86 V FAULT PROTECTION Thermal Shutdown Temperature T SD Rising Threshold 150 °C THYS Hysteresis 20 °C Overcurrent Protection Threshold Valley V IN1/2 to IPHASE1/2 (6 cycles delay) 4.8 7.8 12 A Zero Cross Threshold 350 mA Negative Current Limit INLIMIT I PHASE1/2 to PGND1/2 -10.5 -6.2 -2.8 A Standby Overcurrent Protection Threshold IVSOUT2 2A POWER MOSFET Highside R HDS IPHASE1/2 = 100mA 41 55 mΩ Lowside R LDS IPHASE1/2 = 100mA 9 14 mΩ PHASE Leakage Current (Note 7) EN1/2 = PHASE1/2 = 0V 0.01 2.5 µA PHASE Rise Time (Note 7)t RISE VIN = 16V 10 ns VSOUT2 Standby Power MOSFET IVS OUT2 = 100mA, VSIN1 = 5V 70 m Ω NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Care must be taken not to exceed the phase node max voltage rating. Electrical Specifications VIN = 4.5V to 16V, unless otherwise noted. Typical values are at TJ = +25°C. Boldface limits apply across the junction temperature range, -40°C to +125°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6)T Y P MAX (Note 6)U N I T S

The ISL95901 limits the current in all on-chip power devices. VCC, the two buck regulators and the standby outputs. remains latched off until POR or EN1/2 is toggled. damage. Toggle EN2 or STB2 to reset faulty condition. periods of no switching, as in no-load situations at PFM. The inductor value determines the converter’s ripple current. An output capacitor is required to filter the inductor current. capacitors may also be used. FIGURE 67. EXTERNAL RESISTOR DIVIDER

switching frequency, and COUT is the output capacitor. ripple and surge current ratings. possible. Additional capacitance may be used. maximum junction temperature of +125°C. voltage/output voltage combination and the switching frequency. thermal shutdown will occur. circuit board design minimize these voltage spikes. short, wide traces minimize the magnitude of voltage spikes. supply critical bypass current and signal coupling. break this plane into smaller islands of common voltage levels. printed circuit layers for small signal wiring. FIGURE 68. I RMS/IO vs DUTY CYCLE

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7893.1 January 22, 2015 For additional products, see www.intersil.com/en/products.html Submit Document Feedback To dissipate heat generated by the internal LDO and MOSFET, the pads should be connected to the PCB planes through at least eight vias. These allow heat to move away from the IC and also tie PAD1 to the ground plane through a low impedance path. The switching components should be placed close to the ISL95901 first. Minimize the length of connections between the input capacitors, C IN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible. Position the output inductor and output capacitors between PHASE1 (or PHASE2) and the load. The critical small-signal components include any bypass capacitors, feedback components and compensation components. Feedback resistors should be located as close as possible to the FB pins with vias tied straight to the ground plane as required. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE January 22, 2015 FN7893.1 Updated datasheet by changing the contin uous output current from 6A to 4A throughout document. Added Eval board to ordering information table on page 4. Updated datasheet with all Intersil standards. Dec. 17, 2014 FN7893.0 Initial Release.

24 FN7893.1 January 22, 2015 Submit Document Feedback Package Outline Drawing L46.5x6

46 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 6/11 BOTTOM VIEW DETAIL "X" SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW (4X) 0.15 INDEX AREA PIN 1 PIN #1 INDEX AREA C SEATING PLANE BASE PLANE 0.08 SEE DETAIL "X" C C 5 5.00 46X0.20 B0.10 MA C

0.00 MIN

0.2 REF

0.05 MAX

C0.10// b A B 0.90±0.1 0.203 0.035 0.70 6.00 4.50 3.60 46x 0.40 42x 0.40 (4.50) (5.80) (3.60) (4.80) (46X 0.60) (46X 0.20) (42X 0.40) 3.50 1.2752.85 2x 1.575 3.50 3.50 2x 1.575 2.85 1.275 0.60 0.60 3.50 located within the zone indicated. The pin #1 identifier may be Unless otherwise specified, tolerance : Decimal ± 0.05 Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.25mm from the terminal tip. Dimension b applies to the metallized terminal and is measured Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. either a mold or mark feature. Dimensions are in millimeters.1. NOTES: