954119DFLF

954119DFLF IDT | Alldatasheet

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Systems, Inc. ICS954119 Advance Information 0875—05/24/04 Pin Configuration Recommended Application: CK410 compliant clock Output Features: 2 - 0.7V current-mode differential CPU pairs 1 - 0.7V current-mode differential SRC pair 6 - PCI (33MHz) 3 - PCICLK_F , (33MHz) free-running 1 - USB, 48MHz 1 - 24/48 MHz 1 - DOT, 96MHz, 0.7V current differential pair 2 - REF , 14.318MHz 5 - PCI-Express 0.7V current differential pairs Key Specifications: CPU/SRC outputs cycle-cycle jitter < 85ps PCI outputs cycle-cycle jitter < 250ps +/- 300ppm frequency accuracy on CPU & SRC clocks Programmable Timing Control Hub™ for Next Gen P4™ processor Functionality Features/Benefits: Programmable output frequencies Programmable output skew. Programmable spread percentage for EMI control. Programmable watch dog safe frequency. Supports tight ppm accuracy clocks for Serial-ATA Supports spread spectrum modulation, 0 to -0.5% down spread, ±0.25% center spread, and ±0.3% center spread Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Supports undriven differential CPU, SRC pair in PD# for power management. ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. GND 1 56 VDDPCI PCICLK3 2 55 PCICLK2 PCICLK4 3 54 PCICLK1 PCICLK5 4 53 PCICLK0 GND 5 52 Reset# VDDPCI 6 51 REF0/FS LC PCICLK_F0 7 50 REF1 FS LA/PCICLK_F1 8 49 GND FS LB/PCICLK_F2 9 48 X1 V D D 4 81 0 4 7X 2 SEL24_48#/24_48MHz 11 46 VDDREF USB_48MHz 12 45 SCLK GND 13 44 SDATA DOTT_ 96MHz 14 43 CPUCLKT0 DOTC_96MHz 15 42 CPUCLKC0 Vtt_PwrGd#/PD 16 41 VDDCPU PCIEXT0 17 40 CPUCLKT1 PCIEXC0 18 39 CPUCLKC1 VDDPCIEX 19 38 GND GND 20 37 IREF PCIEXT1 21 36 GNDA P C I E X C 12 2 3 5V D D A PCIEXT2 23 34 VDDPCIEX P C I E X C 22 4 3 3P C I E X T 4 GND 25 32 PCIEXC4 SRCCLKT 26 31 PCIEXT3 SRCCLKC 27 30 PCIEXC3 VDDSRC 28 29 GND ICS954119 56-Pin SSOP Internal Pull-Down Resistor * Internal Pull-Up Resistor Bit2 Bit1 Bit0 CPU PCIE X SRC PCI FSLC FSLB FSLA MHz MHz MHz MHz 00000 266.66 100.00 100.00 33.33 00001 133.33 100.00 100.00 33.33 00010 200.00 100.00 100.00 33.33 00011 166.66 100.00 100.00 33.33 00100 333.33 100.00 100.00 33.33 00101 100.00 100.00 100.00 33.33 00110 400.00 100.00 100.00 33.33 00111 200.00 100.00 100.00 33.33 01000 266.66 133.33 133.33 33.33 01001 133.33 133.33 133.33 33.33 01010 200.00 133.33 133.33 33.33 01011 166.66 125.00 125.00 33.33 01100 333.33 125.00 125.00 33.33 01101 100.00 133.33 133.33 33.33 01110 400.00 133.33 133.33 33.33 01111 200.00 133.33 133.33 33.33 10000 269.33 101.00 101.00 33.67 10001 134.66 101.00 101.00 33.67 10010 202.00 101.00 101.00 33.67 10011 168.33 101.00 101.00 33.67 10100 274.66 103.00 103.00 34.33 10101 137.33 103.00 103.00 34.33 10110 206.00 103.00 103.00 34.33 10111 171.66 103.00 103.00 34.33 11000 279.99 105.00 105.00 35.00 11001 140.00 105.00 105.00 35.00 11010 210.00 105.00 105.00 35.00 11011 174.99 105.00 105.00 35.00 11100 287.99 108.00 108.00 36.00 11101 144.00 108.00 108.00 36.00 11110 216.00 108.00 108.00 36.00 11111 179.99 108.00 108.00 36.00 * Entries 00111 & 01111 are 250MHz on the B & C revision. Bit4 Bit3

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 GND PWR Ground pin. 2 PCICLK3 OUT PCI clock output. 3 PCICLK4 OUT PCI clock output. 4 PCICLK5 OUT PCI clock output. 5 GND PWR Ground pin. 6 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 7 PCICLK_F0 OUT Free running PCI clock not affected by PCI_STOP# .

8 FSLA/PCICLK_F1 I/O

3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock out put.

9 FSLB/PCICLK_F2 I/O

3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values./ 3.3V PCI free running clock output. 10 VDD48 PWR Power pin for the 48MHz output.3.3V 11 **SEL24_48#/24_48MHz I/O Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz. 12 USB_48MHz OUT 48.00MHz USB clock 13 GND PWR Ground pin. 14 DOTT_ 96MHz OUT True clock of differential pair for 96.00MHz DOT clock. 15 DOTC_96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock.

16 Vtt_PwrGd#/PD IN

Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 17 PCIEXT0 OUT True clock of differential PCI_Express pair. 18 PCIEXC0 OUT Complement clock of differential PCI_Express pair. 19 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 20 GND PWR Ground pin. 21 PCIEXT1 OUT True clock of differential PCI_Express pair. 22 PCIEXC1 OUT Complement clock of differential PCI_Express pair. 23 PCIEXT2 OUT True clock of differential PCI_Express pair. 24 PCIEXC2 OUT Complement clock of differential PCI_Express pair. 25 GND PWR Ground pin. 26 SRCCLKT OUT True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. 27 SRCCLKC OUT Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 Pin Description PIN # PIN NAME TYPE DESCRIPTION 29 GND PWR Ground pin. 30 PCIEXC3 OUT Complement clock of differential PCI_Express pair. 31 PCIEXT3 OUT True clock of differential PCI_Express pair. 32 PCIEXC4 OUT Complement clock of differential PCI_Express pair. 33 PCIEXT4 OUT True clock of differential PCI_Express pair. 34 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 35 VDDA PWR 3.3V power for the PLL core. 36 GNDA PWR Ground pin for the PLL core.

37 IREF OUT

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 38 GND PWR Ground pin. 39 CPUCLKC1 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 40 CPUCLKT1 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 41 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 42 CPUCLKC0 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 43 CPUCLKT0 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 44 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 45 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 46 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 47 X2 OUT Crystal output, Nominally 14.318MHz 48 X1 IN Crystal input, Nominally 14.318MHz. 49 GND PWR Ground pin. 50 REF1 OUT 14.318 MHz reference clock.

51 REF0/FSLC I/O

14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.

52 Reset# OUT Real time system reset signal for frequency gear ratio change or watchdog

timer timeout. This signal is active low. 53 PCICLK0 OUT PCI clock output. 54 PCICLK1 OUT PCI clock output. 55 PCICLK2 OUT PCI clock output. 56 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 ICS954119 follows Intel CK410 Y ellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS954119 is driven with a 14.318MHz crystal. General Description Block Diagram I REF PLL2 Frequency Dividers Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic 48MHz, USB X2 XTAL SDATA SCLK Vtt_PWRGD#/PD FSLA FSLB FSLC Sel24/48 Control Logic REF (1:0) CPUCLKT (1:0) CPUCLKC (1:0) SRCCLKT SRCCLKC PCICLK (5:0) PCICLKF (2:0) PCI-Express (4:0) Reset# DOTT_96MHz DOTC_96MHz 24/48MHz Power Busing VDD 6,56 19,34 GND Descri ption 1,5 PCI pads and Prepad

13 USB_48M Hz, DOT_96M Hz, Fix PLL

20,29 Differnetial PCIEX pair

25 Differnetial SRC pair

36 Analog Core, CPU PLL

38 Differnetial CPU pair

49 Xtal, Ref, CPU PLL Digital

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 General I2C serial interface information for the ICS954119 How to Write:

Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit ICS (Slave/Receiver) T WR ACK ACK ACK ACK ACK P stoP bit X Byte Index Block Write Operation Slave Address D2(H) Beginning Byte = N WRite starT bit Controller (Host) Byte N + X - 1 Data Byte Count = X Beginning Byte N T starT bit WR WRite RT Repeat starT RD ReaD Beginning Byte N Byte N + X - 1 N Not acknowledge Ps t o P b i t Slave Address D3(H) Index Block Read Operation Slave Address D2(H) Beginning Byte = N ACK ACK Data Byte Count = X ACK ICS (Slave/Receiver)Controller (Host) X Byte ACK ACK

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 Table1: Frequency Selection Table Bit2 Bit1 Bit0 CPU PCIEX SRC PCI Spread FSLC FSLB FSLA MHz MHz MHz MHz % Bit4 Bit3

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 I2C Table: Frequency Select Register Bit 7 FS Source Frequency H/W IIC Select RW 0 Bit 6 SS_EN1 PLL1 Spread Enable RW 1 Bit 5 Reserved Reserved RW 1 Bit 4 Bit4 Freq Select Bit 4 RW 0 Bit 3 Bit3 Freq Select Bit 3 RW 0 Bit 2 FSLC Freq Select Bit 2 RW Latch Bit 1 FSLB Freq Select Bit 1 RW Latch Bit 0 FSLA Freq Select Bit 0 RW Latch I2C Table: Output Control Register Bit 7 PCICLK_F0 Output Control RW 1 Bit 6 DOTT/C_96MHz Output Control RW 1 Bit 5 USB_48MHz Output Control RW 1 Bit 4 REF0 Output Control RW 1 Bit 3 REF1 Output Control RW 1 Bit 2 CPUCLKT/C1 Output Control RW 1 Bit 1 CPUCLKT/C0 Output Control RW 1 Bit 0 CPUCLK's PD Mode Output State Control RW 0 I2C Table: Output Control Register Bit 7 PCICLK5 Output Control RW 1 Bit 6 PCICLK4 Output Control RW 1 Bit 5 PCICLK3 Output Control RW 1 Bit 4 PCICLK2 Output Control RW 1 Bit 3 PCICLK1 Output Control RW 1 Bit 2 PCICLK0 Output Control RW 1 Bit 1 PCICLK_F2 Output Control RW 1 Bit 0 PCICLK_F1 Output Control RW 1 I2C Table: Output Control Register Bit 7 PCIEXCLK's PD Mode Output State Control RW 0 Bit 6 Reserved Reserved RW 1 Bit 5 PCIEXCLKT/C4 Output Control RW 1 Bit 4 PCIEXCLKT/C3 Output Control RW 1 Bit 3 SRCCLKT/C Output Control RW 1 Bit 2 PCIEXCLKT/C2 Output Control RW 1 Bit 1 PCIEXCLKT/C1 Output Control RW 1 Bit 0 PCIEXCLKT/C0 Output Control RW 1 I2C Table: Output Control Register Bit 7 PCI/SRC Stop EN Stop all PCI / PCIEX / SRC clocks 1 Bit 6 PCICLK_F2 Stop Control RW 0 Bit 5 PCICLK_F1 Stop Control RW 0 Bit 4 PCICLK_F0 Stop Control RW 0 Bit 3 PCIEXCLKT/C (5:3) Stop Control RW 1 Bit 2 SRCCLKT/C Stop Control RW 1 Bit 1 PCIEXCLKT/C (2:0) Stop Control RW 1 Bit 0 Reserved Reserved RW 1--- Free Running Stoppable Stoppable Free Running Stoppable Free Running Stoppable - Free Running Stoppable PWD Enable Disable - Free Running Stoppable Name Control Function Type 1 Disable Enable 18,17 Disable Enable Disable Enable 24,23 Disable Enable Disable Enable Disable Enable PWD Driven Hi-Z Disable Enable Byte 3 Pin # Name Control Function Type 0 1 Disable Enable

9 Disable Enable

Name Control Function Type 0 Disable Enable - Driven Hi-Z Disable Enable Disable Enable Disable Enable Disable Enable PWD Disable Enable Disable Enable See Table 1: PLL 1 Frequency Selection Table Byte 1 Pin # Name Control Function Type 0 1 OFF ON 1P W D Latch Inputs IIC Name Control Function Type 0 14,15 Pin # 27,26 Free Running Byte 2 Pin # 40,39 43,42 33,32 31,30 Byte 0 Pin # 22,21 Byte 4

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 I2C Table: Programmable Skew Control Register Bit 7 PCISkw3 RW 0000:0 0100:150 1000:300 1100:450 0 Bit 6 PCISkw2 RW 0001:N/A 0101:N/A 1001:N/A 1101:600 0 Bit 5 PCISkw1 RW 0010:N/A 0110:N/A 1010:N/A 1110:750 0 Bit 4 PCISkw0 RW 0011:N/A 0111:N/A 1011:N/A 1111:900 0 Bit 3 ASYNC1 RW 0 Bit 2 ASYNC0 RW 0 Bit 1 REF0 REF0 select RW 0 Bit 0 Reserved Reserved RW 0 I2C Table: Output Drive Control Register Bit 7 Reserved RW 1 Bit 6 Reserved RW 1 Bit 5 Reserved RW 1 Bit 4 Reserved RW 1 Bit 3 Reserved RW 0 Bit 2 Reserved RW 1 Bit 1 Reserved RW 0 Bit 0 Reserved RW 1 I2C Table: Vendor ID Register Bit 7 Reserved Reserved RW 0 Bit 6 Reserved Reserved RW 0 Bit 5 Reserved Reserved RW 0 Bit 4 Reserved Reserved RW 0 Bit 3 VID3 R 0 Bit 2 VID2 R 0 Bit 1 VID1 R 0 Bit 0 VID0 R 1 I2C Table: Byte Count Register Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 1 Bit 2 BC2 RW 1 Bit 1 BC1 RW 1 Bit 0 BC0 RW 1 I2C Table: WD Time Control Register Bit 7 WD_EN Watchdog Alarm Enable RW 0 Bit 6 WD_SEL Watchdog Hard/Soft Alarm Select RW 0 Bit 5 WD Hard Status WD Hard Alarm Status R X Bit 4 WD Soft Status WD Soft Alarm Status R X Bit 3 WDTCtrl Watch Dog Time base Control RW 0 Bit 2 WD2 WD Timer Bit 2 RW 1 Bit 1 WD1 WD Timer Bit 1 RW 1 Bit 0 WD0 WD Timer Bit 0 RW 1 These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s.- - Normal Alarm - 290ms Base 1160ms Base - Hard only Hard and Soft - Normal Alarm PWD - Disable Enable Control Function Type 0 1 Byte 9 Pin # Name PWD Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. - -- Byte 8 Pin # Name Control Function Type 0 1 VENDOR ID - -- - 001 = ICS - - -- - -- - -- - -- Type 0 1 PWDByte 7 Pin # Name Control Function Reserved -- Reserved -- Reserved -- - -- 1P W D Reserved -- Name Control Function Type 0 XTAL Fixed PLL - PCI Async Freq 00 = PLL1 10 = 37.7 - 01 = 33.0 11 = 44.0 PWD CPU-PCI 7 Steps Skew Control (ps) Byte 5 Pin # Name Control Function Type 0 1 Byte 6 Pin #

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 I2C Table: M/N Programming & WD Safe Frequency Control Register Bit 7 M/N_EN PLL1 M/N Programming Enable RW 0 Bit 6 Reserved Reserved RW 0 Bit 5 WD Safe Freq Source WD Safe Freq Source RW 0 Bit 4 WD SF4 RW 0 Bit 3 WD SF3 RW 0 Bit 2 WD SF2 RW 0 Bit 1 WD SF1 RW 0 Bit 0 WD SF0 RW 0 I2C Table: PLL1 Frequency Control Register Bit 7 N Div8 N Divider Prog bit 8 RW X Bit 6 N Div9 N Divider Prog bit 9 RW X Bit 5 M Div5 RW X Bit 4 M Div4 RW X Bit 3 M Div3 RW X Bit 2 M Div2 RW X Bit 1 M Div1 RW X Bit 0 M Div0 RW X I2C Table: PLL1 Frequency Control Register Bit 7 N Div7 RW X Bit 6 N Div6 RW X Bit 5 N Div5 RW X Bit 4 N Div4 RW X Bit 3 N Div3 RW X Bit 2 N Div2 RW X Bit 1 N Div1 RW X Bit 0 N Div0 RW X I2C Table: PLL1 Spread Spectrum Control Register Bit 7 SSP7 RW X Bit 6 SSP6 RW X Bit 5 SSP5 RW X Bit 4 SSP4 RW X Bit 3 SSP3 RW X Bit 2 SSP2 RW X Bit 1 SSP1 RW X Bit 0 SSP0 RW X I2C Table: PLL1 Spread Spectrum Control Register Bit 7 Reserved Reserved R 0 Bit 6 SSP14 RW X Bit 5 SSP13 RW X Bit 4 SSP12 RW X Bit 3 SSP11 RW X Bit 2 SSP10 RW X Bit 1 SSP9 RW X Bit 0 SSP8 RW X - -- Spread Spectrum Programming bit(14:8) These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL1 Type 0 1 PWDByte 14 Pin # Name Control Function Spread Spectrum Programming bit(7:0) These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL1 Type 0 1 PWDByte 13 Pin # Name Control Function N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6) The decimal representation of M and N Divier in Byte 11 and 12 will configure the PLL1 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] Type 0 1 PWDByte 12 Pin # Name Control Function The decimal representation of M and N Divier in Byte 11 and 12 will configure the PLL1 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] M Divider Programming bit (5:0) Type 0 1 PWDByte 11 Pin # Name Control Function - B10b(4:0) Latch Inputs Watch Dog Safe Freq Programming bits Writing to these bit will configure the safe frequency as Byte0 bit (4:0). - Disable Enable - -- Type 0 1 PWDByte 10 Pin # Name Control Function

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 I2C Table: Reserved Register Bit 7 Reserved Reserved RW X Bit 6 Reserved Reserved RW X Bit 5 Reserved Reserved RW X Bit 4 Reserved Reserved RW X Bit 3 Reserved Reserved RW X Bit 2 Reserved Reserved RW X Bit 1 Reserved Reserved RW X Bit 0 Reserved Reserved RW X I2C Table: Reserved Register Bit 7 Reserved RW X Bit 6 Reserved RW X Bit 5 Reserved RW X Bit 4 Reserved RW X Bit 3 Reserved RW X Bit 2 Reserved RW X Bit 1 Reserved RW X Bit 0 Reserved RW X I2C Table: Reserved Register Bit 7 Reserved RW X Bit 6 Reserved RW X Bit 5 Reserved RW X Bit 4 Reserved RW X Bit 3 Reserved RW X Bit 2 Reserved RW X Bit 1 Reserved RW X Bit 0 Reserved RW X I2C Table: Reserved Register Bit 7 Reserved RW 0 Bit 6 Reserved RW X Bit 5 Reserved RW X Bit 4 Reserved RW X Bit 3 Reserved RW X Bit 2 Reserved RW X Bit 1 Reserved RW X Bit 0 Reserved RW X I2C Table: Programmable Output Divider Register Bit 7 CPUDiv3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X Bit 6 CPUDiv2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X Bit 5 CPUDiv1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X Bit 4 CPUDiv0 RW 0011:/7 0111:/14 1011:/28 1111:/56 X Bit 3 PCIEXDiv3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X Bit 2 PCIEXDiv2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X Bit 1 PCIEXDiv1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X Bit 0 PCIEXDiv0 RW 0011:/7 0111:/14 1011:/28 1111:/56 X PCIEX Divider Ratio Programming Bits CPU Divider Ratio Programming Bits Type 0 1 PWDByte 19 Pin # Name Control Function Reserved 1P W D Reserved Name Control Function Type 0 Byte 18 Pin # 1P W D Reserved Reserved Name Control Function Type 0 Byte 17 Pin # 1P W D Reserved Reserved Name Control Function Type 0 Byte 16 Pin # 1P W D Reserved Name Control Function Type 0Byte 15 Pin #

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 I2C Table: Programmable Output Divider Register Bit 7 PCIDiv3 RW 0000:/2 0100:/4 1000:/8 1100:/16 X Bit 6 PCIDiv2 RW 0001:/3 0101:/6 1001:/12 1101:/24 X Bit 5 PCIDiv1 RW 0010:/5 0110:/10 1010:/20 1110:/40 X Bit 4 PCIDiv0 RW 0011:/15 0111:/30 1011:/60 1111:/120 X Bit 3 Reserved RW X Bit 2 Reserved RW X Bit 1 Reserved RW X Bit 0 Reserved RW X Reserved- PCI Divider Ratio Programming Bits Type 0 1 PWDByte 20 Pin # Name Control Function

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes 3.3V Core Supply Voltage VDD_A - VDD + 0.5V V 1 3.3V Logic Input Supply Voltage VDD_In - GND - 0.5 V DD + 0.5V V 1 Storage Temperature Ts - -65 150 °C 1 Ambient Operating Temp Tambient - 07 0 ° C 1 Case Temperature Tcase - 115 °C 1 Input ESD protection HBM ESD prot - 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS Notes Input High Voltage V IH 3.3 V +/-5% 2 V DD + 0.3 V 1 Input Low Voltage V IL 3.3 V +/-5% V SS - 0.3 0.8 V 1 Input High Current I IH VIN = VDD -5 5 uA 1 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 Low Threshold Input- High Voltage VIH_FSL 3.3 V +/-5% 0.7 V DD + 0.3 V 1 Low Threshold Input- Low Voltage VIL_FSL 3.3 V +/-5% V SS - 0.3 0.35 V 1 Operating Supply Current IDD3.3OP Full Active, CL = Full load; 350 mA 1 Operating Current I DD3.3OP all outputs driven 400 mA 1 all diff pairs driven 70 mA 1 all differential pairs tri-stated 12 mA 1 Input Frequency F i VDD = 3.3 V 14.31818 MHz 2 Pin Inductance L pin 7n H 1 C IN Logic Inputs 5 pF 1 C OU T Output pin capacitance 6 pF 1 C INX X1 & X2 pins 5 pF 1 Clk Stabilization T STAB From VDD Power-Up or de- assertion of PD# to 1st clock 1.8 ms 1 Modulation Frequency Triangular Modulation 30 33 kHz 1 Tdrive_PD# CPU output enable after PD# de-assertion 300 us 1 Tfall_Pd# PD# fall time of 5 ns 1 Trise_Pd# PD# rise time of 5 ns 1 SMBus Voltage V DD 2.7 5.5 V 1 Low-level Output Voltage V OL @ IPULLUP 0.4 V 1 Current sinking at VOL = 0.4 V IPULLUP 4m A 1 SCLK/SDATA Clock/Data Rise Time TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Clock/Data Fall Time TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. Input Low Current Powerdown Current I DD3.3PD Input Capacitance

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES Current Source Output Impedance Zo V O = Vx 3000 Ω 1 Voltage High VHigh 660 850 mV 1,3 Voltage Low VLow -150 150 mV 1,3 Max Voltage Vovs 1150 mV 1 Min Voltage Vuds -300 mV 1 Crossing Voltage (abs) Vx(abs) 250 550 mV 1 Crossing Voltage (var) d-Vx Variation of crossing over all edges 140 mV 1 Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 400MHz nominal 2.4993 2.5008 ns 2 400MHz spread 2.4993 2.5133 ns 2 333.33MHz nominal 2.9991 3.0009 ns 2 333.33MHz spread 2.9991 3.016 ns 2 266.66MHz nominal 3.7489 3.7511 ns 2 266.66MHz spread 3.7489 3.77 ns 2 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2 166.66MHz nominal 5.9982 6.0018 ns 2 166.66MHz spread 5.9982 6.0320 ns 2 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 7.5400 ns 2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 400MHz nominal/spread 2.4143 ns 1,2 333.33MHz nominal/spread 2.9141 ns 1,2 266.66MHz nominal/spread 3.6639 ns 1,2 200MHz nominal/spread 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.3728 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time t r VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time t f VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-t r VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-t f VOH = 0.525V VOL = 0.175V 125 ps 1 Duty Cycle d t3 Measurement from differential wavefrom 45 55 % 1 Skew t sk3 CPU(1:0), VT = 50% 100 ps 1 Skew t sk4 CPU(1:0) to CPU2_ITP, VT = 50% 150 ps 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom (CPU2_ITP) 125 ps 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom, (CPU(1:0)) 85 ps 1 *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS =33.2Ω , RP =49.9Ω, ΙRE F = 475Ω 1Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Average period Tperiod Absolute min period T absmin Statistical measurement on single ended signal Measurement on single ended signal using absolute value.

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 Electrical Characteristics - SRC/SATA/PCIEX 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS Notes Current Source Output Impedance Zo V O = Vx 3000 Ω 1 Voltage High VHigh 660 850 mV 1,3 Voltage Low VLow -150 150 mV 1,3 Max Voltage Vovs 1150 mV 1 Min Voltage Vuds -300 mV 1 Crossing Voltage (abs) Vx(abs) 250 550 mV 1 Crossing Voltage (var) d-Vx Variation of crossing over all edges 140 mV 1 Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time t r VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time t f VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-t r VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-t f VOH = 0.525V VOL = 0.175V 125 ps 1 Duty Cycle d t3 Measurement from differential wavefrom 45 55 % 1 Skew t sk3 VT = 50% 250 ps 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom 125 ps 1 *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS =33.2Ω , RP =49.9Ω, ΙRE F = 475Ω 1Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Average period Tperiod Statistical measurement on single ended signal Measurement on single ended signal using absolute value. Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES Output Impedance R DSP VO = VDD *(0.5) 12 55 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V 1 Output Low Voltage V OL IOL = 1 mA 0.55 V 1 V OH @MIN = 1.0 V -33 mA 1 VOH @MAX = 3.135 V -33 mA 1 VOL @ MIN = 1.95 V 30 mA 1 VOL @ MAX = 0.4 V 38 mA 1 Edge Rate t slewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time t r VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time t f VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle d t1 VT = 1.5 V 45 55 % 1 Group Skew t skew VT = 1.5 V 500 ps 1 Jitter, Cycle to cycle t jcyc-cyc VT = 1.5 V 250 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (unless otherwise specified) 1Guaranteed by design and characterization, not 100% tested in production. Output High Current I OH Output Low Current I OL

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1 Clock period T period 48.00MHz output nominal 20.8313 20.8354 ns Output Impedance R DSP VO = VDD *(0.5) 12 55 Ω 1 Output High Voltage V OH IOH = -1 mA 2.4 V 1 Output Low Voltage V OL IOL = 1 mA 0.55 V 1 V OH @MIN = 1.0 V -33 mA 1 VOH @MAX = 3.135 V -33 mA 1 VOL @ MIN = 1.95 V 30 mA 1 VOL @ MAX = 0.4 V 38 mA 1 Edge Rate t slewr/f Rising/Falling edge rate 1 4 V/ns 1 Edge Rate t slewr /f_USB USB48 Rising/Falling edge rate 1 2 V/ns 1 Rise Time t r VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time t f VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Rise Time t r_USB VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time t f_USB VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle d t1 VT = 1.5 V 45 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only) 1Guaranteed by design and characterization, not 100% tested in production. Output High Current I OH Output Low Current I OL Electrical Characteristics - DOT_96MHz 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS Notes Current Source Output Impedance Zo V O = Vx 3000 Ω 1 Voltage High VHigh 660 850 mV 1,3 Voltage Low VLow -150 150 mV 1,3 Max Voltage Vovs 1150 mV 1 Min Voltage Vuds -300 mV 1 Crossing Voltage (abs) Vx(abs) 250 550 mV 1 Crossing Voltage (var) d-Vcross Variation of crossing over all edges 140 mV 1 Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1,2 Average period Tperiod 96.00MHz nominal 10.4135 10.4198 ns 2 Absolute min period Tabsmin 96.00MHz nominal 10.1635 ns 1,2 Rise Time t r VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time t f VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-t r VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-t f VOH = 0.525V VOL = 0.175V 125 ps 1 Duty Cycle d t3 Measurement from differential wavefrom 45 55 % 1 Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom 250 ps 1 *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS =33.2Ω , RP =49.9Ω, ΙRE F = 475Ω 1Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Measurement on single ended signal using absolute value. Statistical measurement on single ended signal

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 Clock period T period 14.318MHz output nominal 69.8270 69.8550 ns 2 Output High Voltage V OH IOH = -1 mA 2.4 V 1 Output Low Voltage V OL IOL = 1 mA 0.4 V 1 Output High Current I OH VOH @MIN = 1.0 V, VOH @MAX = 3.135 V -29 -23 mA 1 Output Low Current I OL VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA 1 Edge Rate t slewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time t r1 VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time t f1 VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle d t1 VT = 1.5 V 45 55 % 1 Jitter t jcyc-cyc VT = 1.5 V 1000 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only) 1Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

Systems, Inc. ICS954119 Advance Information 0875—05/24/04 INDEX AREA INDEX AREA 121 2 N D h x 45°h x 45° E1 E α SEATING PLANE SEATING PLANE A e -C-- C - b c L

Ordering Information

Example: M I NM A XM I NM A X A 2.41 2.80 .095 .110 A1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 D E 10.03 10.68 .395 .420 E1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 L 0.50 1.02 .020 .040 N a0 °8 °0 °8 ° VARIATIONS M I NM A XM I NM A X 56 18.31 18.55 .720 .730 10-0034 0.635 BASIC 0. 025 BASIC COMMON DIMENSIONS In Millimeters In Inches COMMON DIMENSIONS Reference Doc.: JEDEC Publication 95, MO-118 56-Lead, 300 mil Body, 25 mil, SSOP N SEE VARIATIONS SEE VARIATIONS D mm. D (inch) SYMBOL SEE VARIATIONS SEE VARIATIONS Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device ICS XXXX y F LF- T

Summary

Programmable Timing Control Hub??for Next Gen P4??processor

Description