950905

Renesas Technology Corp

Programmable Timing Control Hub™ for P4™ Mar 2020

Manufacturer: Renesas Technology Corp

Document: 19 Pages / 392Kb

Request Quote Download Datasheet Read online HTML view

More from Renesas Technology Corp Browse 0-9 parts

Online Datasheet

Read 950905 online.

950905 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 19

Technical content

Systems, Inc. ICS950905 Advance Information Block Diagram

950905 Rev - 11/26/01

Pin ConfigurationRecommended Application: VIA P4X266 chipset with PC133 or DDR memory. Output Features:

2 - Pair of differential CPU clocks @ 3.3V 1 - Pair of differential push pull CPU_CS clocks @ 2.5V 3 - AGP @ 3.3V 9 - PCI @ 3.3V 1- IOAPIC @ 2.5V 1 - 48MHz @ 3.3V fixed 1 - 24_48MHz @ 3.3V 1 - REF @ 3.3V, 14.318MHz Features/Benefits: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2C Index read/write and block read/write operations. For DDR and or PC133 SDRAM system use ICS93718 as the memory buffer. Uses external 14.318MHz crystal. Key Specifications:
CPU_CS - CPU0: <±250ps CPU_CS - AGP: <±250ps PCI - PCI: <500ps CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns Programmable Timing Control Hub™ for P4™ 1. These outputs have 2X drive strength. * These inputs have a internal Pull-up resistor of 120K to VDD ** These inputs have a internal pull-down to GND 48-Pin 300-mil SSOP Frequency Table I REF PLL2 PLL1 Spread Spectrum 48MHz 24_48MHz IOAPIC PCICLK (7:0) AGPCLK (2:0) RESET# PCICLK_F XTAL OSC CPU DIVDER CPU DIVDER IOAPIC DIVDER PCI DIVDER AGP DIVDER Stop Stop Stop SEL24_48 SDATA SCLK FS (3:0) PD# PCI_STOP# CPU_STOP# MULTI_SEL Vtt_PWRGD# Control Logic Config. Reg. / 2 REF0 CPUCLKT_(1:0) CPUCLKC_(1:0) CPUCLK_PPT CPUCLK_PPC WDEN WDTB 0LESITLUM tegraTdraoB ZmreT/ecarT ,RecnerefeR =ferI V DD )rR*3(/ tuptuO tnerruC Z@hoV 0s mho05 ,%1122=rR Am00.5=ferI FERI*4=hoI0 5@V0.1 1s mho05 ,%1574=rR Am23.2=ferI FERI*6=hoI0 5@V7.0 3SF2 SF1 SF0 SF KLCUPC zHM PGA zHM KLCICP zHM 000 0 0 0.0610 0.080 0.04 000 1 0 0.4610 0.280 0.14 001 0 0 6.6610 6.660 3.33 001 1 0 0.0710 0.860 0.43 01 0 0 0 0.5710 0.070 0.53 01 0 1 0 0.0810 0.270 0.63 01 1 0 0 0.5810 0.470 0.73 01 1 1 0 0.0910 0.670 0.83 100 0 0 8.660 8.660 4.33 1001 0 9.0017 2.763 6.33 101 0 0 6.3310 8.660 4.33 101 1 0 4.0020 8.660 4.33 11 0 0 0 6.660 6.660 3.23 11 0 1 0 0.0010 6.660 3.33 111 0 0 0.0020 6.860 3.33 111 1 0 3.3310 6.860 3.33 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. 1**SEL24_48/REF0 VDDREF GND VDD48 *FS3/48MHz *FS2/24_48MHz GND *FS0/PCICLK_F **FS1/PCICLK0 *MULTI_SEL/PCICLK1 GND PCICLK2 PCICLK3 VDDPCI PCICLK4 PCICLK5 PCICLK6 GND PCICLK7 *PD# AGPCLK0 VDDAGP *WDTB/ **WDEN/ VDDLAPIC GND N/C IOAPIC GND VDDCPU_PP (2.5V) CPUCLK_PPT CPUCLK_PPC CPUCLKT_0 CPUCLKC_0 VDDCPU (3.3V) I REF GND CPUCLKT_1 CPUCLKC_1 Vtt_PWRGD# CPU_STOP#* PCI_STOP#* RESET# SDATA SCLK AGPCLK2 AGPCLK1 GND ICS950905

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Pin Description The ICS950905 is a single chip clock solution for desktop designs using the VIA P4X266 chipset with PC133 or DDR memory. with PC133 or DDR memory. When used with a fanout buffer such as the ICS93712, ICS93715 or the ICS93718 provides all the necessary clock signals for such a system. The ICS950905 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. General Description REBMUNNIPE MANNIPE PYTN OITPIRCSED 84_42LESN I .zHM86=1;zHM42=0.tuptuozHM84ro42rehtiestcelesottupnichtaL 0FERT UO. tuptuokcolcecnereferzHM813.41,V3.3 83,42,61,6,2D DVR WP. ylppusrewopV3.3 41 XN I .2Xmorfrotsiserkcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC 52 XT UO .)Fp33(pacdaollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC 3SFN I. norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL zHM84T UO. .tuptuokcolczHM84dexiFV3.3 2SFN I. norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL zHM84_42T UO. tuptuozHM84ro42elbatceleS ,52,02,31,9,3 74,44,63 DNGR WP. ylppusV3.3rofsnipdnuorG 0SFN I. norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL F_KLCICPT UOt uptuokcolcICPgninnureerFV3.3 1SFN I. norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL 0KLCICPT UO. tuptuokcolcICPV3.3 BTDWN I .pets/sm085=0;pets/sm092=1.tupnitcelesesabemitgodhctaW 2KLCICPT UO. tuptuokcolcICPV3.3 NEDWN I DW=1;elbasiDDW=0.zHM001siycneuqerfefastluafeD.tiucricgodhctawfoelbaneerawdraH .tupnihctalasisihT.elbanE 3KLCICPT UO. tuptuokcolcICPV3.3 71,81,91,12) 4:7(KLCICPT UO. stuptuokcolcICPV3.3 22# DPN I ehT.etatsrewopwolaotniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA rewopehtfoycnetalehT.deppotseralatsyrcehtdnaOCVehtdnadelbasideraskcolclanretni .sm3nahtretaergebtonlliwnwod 32,62,72) 0:2(PGAT UO. deppotsebtonyamesehT.ICPX2sadenifedstuptuoPGA 82K LCSN II rofnipkcolC 2 .tnarelotV5yrtiucricC 92A TADSO /II rofnipataD 2 .tnarelotV5yrtiucricC 03# TESERT UO .wolevitcasilangissihT.tuoemitremmitgodhctawroeulavycneuqerfroflangistesermetsysemitlaeR 33# DGRWP_ttVN I stupniLESTLUMdna)0:3(SFnehwenimretedotdesuebortsevitisneslevelasitupniLTTVLV3.3sihT .)wolevitca(delpmasebotydaereradnadilavera 93,43) 0:1(_CKLCUPCT UO lanretxednastuptuotnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"yrotnemelpmoC" .saibegatlovrofderiuqererasrotsiser 04,53) 0:1(_TKLCUPCT UO erasrotsiserlanretxednastuptuotnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT" .saibegatlovrofderiuqer 73F ERIT UO noisicerpdexifaseriuqernipsihT.sriapKLCUPCehtroftnerrucecnereferehtsehsilbatsenipsihT .tnerrucetairporppaehthsilbatseotredronidnuorgotdeitrotsiser 14C PP_KLCUPCT UO .stuptuollup-hsupV5.2eraesehT.stuptuoUPCriaplaitnereffidfoskcolc""yrotnemelpmoC 24T PP_KLCUPCT UO .stuptuollup-hsupV5.2eraesehT.stuptuoUPCriaplaitnereffidfoskcolc""eurT 34) V5.2(PP_UPCDDVR WP. V5.2stuptuoSC_KLCUPCrofrewoP 54C IPAOIT UOs tuptuokcolcV5.2 64C /N- . nipsihtotsnoitcennocoN 84C IPALDDVR WP. V5.2skcolcCIPArofrewoP

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information General I2C serial interface information How to Write:

Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit *See notes on the following page. ICS (Slave/Receiver) T WR ACK ACK ACK ACK ACK P stoP bit X Byte Index Block Write Operation Slave Address D2(H) Beginning Byte = N WRite starT bit Controller (Host) Byte N + X - 1 Data Byte Count = X Beginning Byte N T starT bit WR WRite RT Repeat starT RD ReaD Beginning Byte N Byte N + X - 1 N Not acknowledge Ps t o P b i t Slave Address D3(H) Index Block Read Operation Slave Address D2(H) Beginning Byte = N ACK ACK Data Byte Count = X ACK ICS (Slave/Receiver)Controller (Host) X Byte ACK ACK

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Byte 0: Functionality and frequency select register (Default=0) Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. tiB noitpircseD DWP tiB )4:7,2( 2tiB 7tiB6 tiB5 tiB4 tiB KLCUPC zHM KLCPGA zHM KLCICP zHM %daerpS xxxx1 3SF2 SF1 SF0 SF 00000 0 0.2010 0.860 0.43d aerpSretneC%03.0-/+ 00001 0 0.5010 0.070 0.53d aerpSretneC%03.0-/+ 00010 0 0.8010 0.270 0.63d aerpSretneC%03.0-/+ 00011 0 0.1110 0.470 0.72d aerpSretneC%03.0-/+ 001 00 0 0.4110 0.670 0.83d aerpSretneC%03.0-/+ 001 01 0 0.7110 0.870 0.93d aerpSretneC%03.0-/+ 00110 0 0.0210 0.080 0.04d aerpSretneC%03.0-/+ 00111 0 0.3210 0.280 0.14d aerpSretneC%03.0-/+ 01 0 00 0 0.6210 0.270 0.63d aerpSretneC%03.0-/+ 01 0 01 0 0.0310 3.470 1.73d aerpSretneC%03.0-/+ 01 01 0 0 9.3315 9.668 4.33d aerpSretneC%03.0-/+ 01 011 0 0.0410 0.070 0.53d aerpSretneC%03.0-/+ 011 00 0 0.4410 0.270 0.63d aerpSretneC%03.0-/+ 011 01 0 0.8410 0.470 0.73d aerpSretneC%03.0-/+ 011 1 0 0 0.2510 0.670 0.83d aerpSretneC%03.0-/+ 011 11 0 0.6510 0.870 0.93d aerpSretneC%03.0-/+ 10000 0 0.0610 0.080 0.04d aerpSretneC%03.0-/+ 1000 1 0 0.4610 0.280 0.14d aerpSretneC%03.0-/+ 100 10 0 6.6610 6.660 3.33d aerpSretneC%03.0-/+ 100 11 0 0.0710 0.860 0.43d aerpSretneC%03.0-/+ 10 100 0 0.5710 0.070 0.53d aerpSretneC%05.0-/+ 10 10 1 0 0.0810 0.270 0.63d aerpSretneC%05.0-/+ 10 110 0 0.5810 0.470 0.73d aerpSretneC%05.0-/+ 10 111 0 0.0910 0.670 0.83d aerpSretneC%03.0-/+ 11000 0 8.660 8.660 4.33d aerpSretneC%03.0-/+ 11001 0 9.0017 2.763 6.33d aerpSretneC%03.0-/+ 11010 0 6.3310 8.660 4.33d aerpSretneC%03.0-/+ 11011 0 4.0020 8.660 4.33d aerpSretneC%03.0-/+ 111 00 0 6.660 6.660 3.23d aerpSnwoD%6.0-ot0 111 01 0 0.0010 6.660 3.33d aerpSnwoD%6.0-ot0 11110 0 0.0020 6.860 3.33d aerpSnwoD%6.0-ot0 11111 0 3.3310 6.860 3.33d aerpSnwoD%6.0-ot0 3tiB .gnittes2tiBdnastupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0 4:7,2tiBybdetcelessiycneuqerF-1 0 1tiB lamroN-0 elbanemurtcepsdaerpS-1 1 0tiB stupnihctalybdetceleseblliwycneuqerfefasgodhctaW-0 )0:4(tib01etyBybdemmargorpeblliwycneuqerfefasgodhctaW-1 0

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Byte 1: CPU Active/Inactive Register (1 = enable, 0 = disable) Byte 3: Active/Inactive Register (1 = enable, 0 = disable) Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Byte 4: Frequency Select Active/Inactive Register (1 = enable, 0 = disable) tiB# niPD WPn oitpircseD 7tiB1 21 ) evitcanI/evitcA(7KLCICP 6tiB9 11 ) evitcanI/evitcA(6KLCICP 5tiB8 11 ) evitcanI/evitcA(5KLCICP 4tiB7 11 ) evitcanI/evitcA(4KLCICP 3tiB5 11 ) evitcanI/evitcA(3KLCICP 2tiB4 11 ) evitcanI/evitcA(2KLCICP 1tiB2 11 ) evitcanI/evitcA(1KLCICP 0tiB1 11 ) evitcanI/evitcA(0KLCICP tiB# niPD WPn oitpircseD 7tiB- 1 ) devreseR( 6tiB0 11 ) evitcanI/evitcA(F_KLCICP 5tiB- 1 ) devreseR( 4tiB- 1 ) devreseR( 3tiB- 0 ) x1=0,x2=1(htgnertSx2/x1SC_C/TKLCUPC 2tiB4 3,531 ) evitcanI/evitcA(1C/TKLCUPC 1tiB9 3,041 ) evitcanI/evitcA(0C/TKLCUPC 0tiB1 4,241 ) evitcanI/evitcA(SC_C/TKLCUPC tiB# niPD WPn oitpircseD 7tiB- X # 3SFdehctaL 6tiB- X # 2SFdehctaL 5tiB- X # 1SFdehctaL 4tiB- X # 0SFdehctaL 3tiB7 1 ) evitcanI/evitcA(zHM84 2tiB8 1 ) evitcanI/evitcA(zHM84_42 1tiB- X ) kcabdaeR(NEDW 0tiB1 1 ) evitcanI/evitcA(FER tiB# niPD WPn oitpircseD 7tiB- 1 d evreseR 6tiB1 1 z HM84=1zhM42=0,84_42LES 5tiB- 1 ) devreseR( 4tiB- - ) devreseR( 3tiB5 41 1 CIPAOI 2tiB3 21 0 KLCPGA 1tiB6 21 1 KLCPGA 0tiB7 21 2 KLCPGA

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Byte 7: Revision ID and Device ID Register Byte 8: Byte Count Read Back Register Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Byte 6: Vendor ID Register (1 = enable, 0 = disable) tiBe maND WPn oitpircseD 7tiB7 etyB0 wohdnatnuocetyberugifnoclliwretsigersihtotgnitirW:etoN sitluafed,kcabdaereblliwsetybynamF 0 H .setyb51= 6tiB6 etyB0 5tiB5 etyB0 4tiB4 etyB0 3tiB3 etyB1 2tiB2 etyB1 1tiB1 etyB1 0tiB0 etyB1 tiBe maND WPn oitpircseD 7tiB7 DIeciveD1 ecivedlaudividninodesabeblliwseulavDIeciveD .esacsihtni"h10" 6tiB6 DIeciveD0 5tiB5 DIeciveD0 4tiB4 DIeciveD1 3tiB3 DIeciveD1 2tiB2 DIeciveD0 1tiB1 DIeciveD1 0tiB0 DIeciveD0 tiBe maND WPn oitpircseD 7tiB3 tiBDInoisiveRX noisivers'ecivedlaudividninodesabeblliwseulavDInoisiveR6tiB2 tiBDInoisiveRX 5tiB1 tiBDInoisiveRX 4tiB0 tiBDInoisiveRX 3tiB3 tiBDIrodneV0 ) devreseR( 2tiB2 tiBDIrodneV0 ) devreseR( 1tiB1 tiBDIrodneV0 ) devreseR( 0tiB0 tiBDIrodneV1 ) devreseR( tiB# niPD WPn oitpircseD 7tiBX- ) devreseR( 6tiBX- ) devreseR( 5tiBX- ) devreseR( 4tiBX- ) devreseR( 3tiBX- ) devreseR( 2tiBX- ) devreseR( 1tiBX- ) devreseR( 0tiBX- ) devreseR(

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Byte 10: Programming Enable bit 8 Watchdog Control Register Byte 11: VCO Frequency M Divider (Reference divider) Control Register Byte 12: VCO Frequency N Divider (VCO divider) Control Register Byte 9: Watchdog Timer Count Register tiBe maND WPn oitpircseD 7tiB8 vidNX 8 tibredividN 6tiB6 vidMX ehtotdsopserroc)0:6(vidMfonoitatneserpserlamicedehT ehtotlauqesipurewoptatluafeD.eulavredividecnerefer .noitcelesstupnidehctal 5tiB5 vidMX 4tiB4 vidMX 3tiB3 vidMX 2tiB2 vidMX 1tiB1 vidMX 0tiB0 vidMX tiBe maND WPn oitpircseD 7tiB7 vidNX ehtotdnopserroc)0:8(vidNfonoitatneserperlamicedehT ehtotlauqesipurewoptatluafeD.eulavredividOCV .11etyBnidetacolsi8vidNecitoN.notcelesstupnidehctal 6tiB6 vidNX 5tiB5 vidNX 4tiB4 vidNX 3tiB3 vidNX 2tiB2 vidNX 1tiB1 vidNX 0tiB0 vidNX tiBe maND WPn oitpircseD 7tiB margorP elbanE 0 tibelbanEgnimmargorP 10etyBrosehctalWHybdetceleseraseicneuqerF.gnimmargorpon=0 Illaelbane= 2 .gnimargorpC 6tiBe lbanEDW0 .tibelbanEgodhctaW .elbanE=1,elbasid=0.eulavdehctalNEDWetirwrevolliwtibsihT 5tiBm ralADW0 s utatsmrala=1lamron=0sutatSmralAgodhctaW 4tiB4 FS0 efasehterugifnoclliwstibesehtotgnitirW.stibycneuqerfefasgodhctaW elbat4:7,2tiB0etyBotgnidnopsrrocycneuqerf 3tiB3 FS1 2tiB2 FS0 1tiB1 FS0 0tiB0 FS0 tiBe maND WPn oitpircseD 7tiB7 DW0 Xotdnopserrocstib8esehtfonoitatneserperlamicedehT edommralaotseogtierofebtiawlliwremitgodhctawehtsm092 sipurewoptatluafeD.gnittesefasehtotycneuqerfehtteserdna .sdnoces6.4=sm09261 6tiB6 DW0 5tiB5 DW0 4tiB4 DW0 3tiB3 DW1 2tiB2 DW0 1tiB1 DW0 0tiB0 DW0

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Byte 14: Spread Spectrum Control Register Byte 15: Output Divider Control Register Byte 13: Spread Spectrum Control Register Byte 16: Output Divider Control Register tiBe maND WPn oitpircseD 7tiB7 SSX daerpsehtmargorplliwtib)0:21(murtcepSdaerpSehT ehtnodesabdetaluclacebotsdeentnecerpdaerpS.egatnecerp daerpsdnatnuomagnidaerps,eliforpgnidaerps,ycneuqerfOCV daerpsroferawtfosSCIesuotdednemmocersitI.ycneuqerf .redividSFdehctalsinorewoptluafeD.gnimmargorp 6tiB6 SSX 5tiB5 SSX 4tiB4 SSX 3tiB3 SSX 2tiB2 SSX 1tiB1 SSX 0tiB0 SSX tiBe maND WPn oitpircseD 7tiBd evreseRX d evreseR 6tiBd evreseRX d evreseR 5tiBd evreseRX d evreseR 4tiB2 1SSX 2 1tiBmurtcepSdaerpS 3tiB1 1SSX 1 1tiBmurtcepSdaerpS 2tiB0 1SSX 0 1tiBmurtcepSdaerpS 1tiB9 SSX 9 tiBmurtcepSdaerpS 0tiB8 SSX 8 tiBmurtcepSdaerpS tiBe maND WPn oitpircseD 7tiB3 viD1/0UPC0 esehtaivderugifnocebnacoitarredividkcolc1/0UPC otreferelbatnoitcelesredividroF.yllaudividnistib4 .redividSFdehctalsipurewoptatluafeD.1elbaT 6tiB2 viD1/0UPC1 5tiB1 viD1/0UPC0 4tiB0 viD1/0UPC1 3tiB3 viDSC_UPC0 aivderugifnocebnacoitarredividkcolcSC_UPC referelbatnoitcelesredividroF.yllaudividnistib4eseht .redividSFdehctalsipurewoptatluafeD.1elbaTot 2tiB2 viDSC_UPC1 1tiB1 viDSC_UPC0 0tiB0 viDSC_UPC1 tiBe maND WPn oitpircseD 7tiB3 viDPGA0 4esehtaivderugifnocebnacoitarredividkcolcPGA otreferelbatnoitcelesredividroF.yllaudividnistib .redividSFdehctalsipurewoptatluafeD.1elbaT 6tiB2 viDPGA1 5tiB1 viDPGA0 4tiB0 viDPGA1 3tiB3 viDCIPA0 esehtaivderugifnocebnacoitarredividkcolcCIPAOI otreferelbatnoitcelesredividroF.yllaudividnistib4 .redividSFdehctalsipurewoptatluafeD.1elbaT 2tiB2 viDCIPA1 1tiB1 viDCIPA0 0tiB0 viDCIPA1

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Byte 17: Output Divider Control Register Byte 18: Group Skew Control Register Byte 19: Group Skew Control Register Table 1 Table 2 )2:3(viD 001 00 11 1)0:1(viD 002 /4 /8 /6 1/ 103 /6 /2 1/4 2/ 015 /0 1/0 2/0 4/ 117 /4 1/8 2/6 5/ )2:3(viD 001 00 11 1)0:1(viD 004 /8 /6 1/2 3/ 103 /6 /2 1/4 2/ 015 /0 1/0 2/0 4/ 119 /8 1/6 3/2 7/ tiBe maND WPn oitpircseD 7tiBV NI_ICP0 t ibnoisrevnIesahPKLCICP 6tiBP GA0 t ibnoisrevnIesahPPGA 5tiBV NI_1/0UPC0 t ibnoisrevnIesahP1/0UPC 4tiBV NI_SC_UPC0 t ibnoisrevnIesahPSC_UPC 3tiB 3viDICP1 stib4esehtaivderugifnocebnacoitarredividkcolcICP .2elbaTotreferelbatnoitcelesredividroF.yllaudividni .redividSFdehctalsipurewoptatluafeD 2tiB 2viDICP0 1tiB 1viDICP0 0tiB 0viDICP1 tiBe maND WPn oitpircseD 7tiB1 wekS_UPC0 ottcepserhtiwSC_T/CKLCUPCehtyaledstib2esehT )0:1(T/CKLCUPC sp057=11sp005=01sp052=10sp0=006tiB0 wekS_UPC0 5tiBd evreseR0 d evreseR 4tiBd evreseR0 d evreseR 3tiB1 wekS_UPC0 ehtyaledstib2esehT) 0:1(T/CKLCUPCo ttcepserhtiwkcolc SC_T/CKLCUPC sp052=10sp0=00s p057=11sp005=012tiB0 wekS_UPC0 1tiBd evreseR0 d evreseR 0tiBd evreseR0 d evreseR tiBe maND WPn oitpircseD 7tiB1 wekS_PGA1 KLCUPCottcepserhtiw)1:2(PGAehtyaledstib2esehT sp057=11sp005=01sp052=10sp0=006tiB0 wekS_PGA0 5tiBd evreseR0 d evreseR 4tiBd evreseR0 d evreseR 3tiB1 wekS_PGA0 KLCUPCottcepserhtiw0_PGAehtyaledstib2esehT sp057=11sp005=01sp052=10sp0=002tiB0 wekS_PGA1 1tiBd evreseR0 d evreseR 0tiBd evreseR0 d evreseR

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Byte 20: Group Skew Control Register Byte 21: Slew Rate Control Register Byte 22: Slew Rate Control Register Byte 23: Slew Rate Control Register tiBe maND WPn oitpircseD 7tiB3 wekS_ICP1 -sn4.1morfweks)0:7(ICPotUPCehtegnahcnacstib4esehT rotnemercniyranibhcaE.sn5.2-sipurewoptatluafeD.sn9.2 ehtfoyaledehtesaercedroesaercnilliw)0:3(stiBfotnemerced .sp001ybskcolcICP 6tiB2 wekS_ICP0 5tiB1 wekS_ICP0 4tiB0 wekS_ICP0 3tiB3 wekS_FICP1 -sn4.1morfweksFICPotUPCehtegnahcnacstib4esehT rotnemercniyranibhcaE.sn5.2-sipurewoptatluafeD.sn9.2 ehtfoyaledehtesaercedroesaercnilliw)0:3(tiBfotnemerced .sp001ybskcolcICP 2tiB2 wekS_FICP0 1tiB1 wekS_FICP0 0tiB0 wekS_FICP0 tiBe maND WPn oitpircseD 7tiB1 welSFER0 .stiblortnocetarwelskcolcFER kaew=01;lamron=11:gnorts=106tiB0 welSFER1 5tiB1 welS)4:7(ICP0 .stiblortnocetarwelskcolc)4:6(ICP kaew=01;lamron=11:gnorts=104tiB0 welS)4:7(ICP1 3tiB )1:3(ICP1 welS 0 .stiblortnocetarwelskcolc)1:3(ICP kaew=01;lamron=11:gnorts=102tiB )1:3(ICP0 welS 1 1tiB 0ICP1 welS 0 .stiblortnocetarwelskcolc0ICP kaew=01;lamron=11:gnorts=100tiB 0ICP0 welS 1 tiBe maND WPn oitpircseD 7tiB1 welS_1_FICP0 .stiblortnocetarwelskcolcFICP kaew=01;lamron=11:gnorts=106tiB0 welS_1_FICP1 5tiB1 welS_0_FICP0 .stiblortnocetarwelskcolcICP kaew=01;lamron=11:gnorts=104tiB0 welS_0_FICP1 3tiB1 welS_)1:2(PGA0 )1:2(PGA. stiblortnocetarwelskcolc kaew=01;lamron=11:gnorts=102tiB1 welS_)1:2(PGA1 1tiB1 welS_0_PGA0 .stiblortnocetarwelskcolc0_PGA kaew=01;lamron=11:gnorts=100tiB0 welS_0_PGA1 tiBe maND WPn oitpircseD 7tiBd evreseRX devreseR6tiBd evreseRX 5tiBd evreseRX devreseR4tiBd evreseRX 3tiB1 welS42-840 .stiblortnocetarwelskcolc42-84 kaew=01;lamron=11:gnorts=102tiB0 welS42-841 1tiB1 welS42-840 .stiblortnocetarwelskcolc42-84 kaew=01;lamron=11:gnorts=100tiB0 welS42-841

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2V DD +0.3 V Input Low Voltage VIL VSS -0.3 0.8 V Input High Current IIH VIN = VDD -5 5 m A Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 mA Input Low Current IIL2 VIN = 0 V; Inputs with pull-up res is tors -200 m A Operating C L = 0 pF; Select @ 66M 100 mA Supply Current C L = Full load 280 mA IREF=2.32 20 m A IREF= 5m A 37 m A Input frequency Fi VDD = 3.3 V; MHz Pin Inductance Lpin 7n H C IN Logic Inputs 5 pF C out Out put pin capacitance 6 pF C INX X1 & X2 pins 27 45 pF Transition Tim e1 Ttrans To 1st crossing of target Freq. 3 mS Settling Time1 Ts From 1st crossing to 1% target Freq. 3 mS Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. 3 m S tPZH ,tPZH output enable delay (all outputs) 1 10 nS tPLZ ,tPZH output disable delay (all outputs) 1 10 nS 1Guarenteed by design, not 100% tested in production. Input Capacitance1 Delay IDD3.3OP Power Down Supply Current IDD3.3PD

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Electrical Characteristics - CPUCLKTC_CS TA = 0 - 70º C; VDD = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output High Voltage VOH2B IOH = -12.0 mA 2V Output Low Voltage VOL2B IOL = 12 mA 0.4 V Output High Current IOH2B VOH = 1.7 V -19 mA Output Low Current IOL2B VOL = 0.7 V 19 mA Rise Time tr2B 1 VOL = 0.4 V, VOH = 2.0 V 1.6 ns Differential Crossover Voltage1 VX N o t e 3 4 55 05 5% Duty Cycle dt2B 1 VT = 1.25 V 45 55 % Skew tsk2B 1 VT = 1.25 V 175 ps Jitter, Cycle-to-cycletjcyc-cyc2B 1 VT = 1.25 V 250 ps Jitter, One Sigma tj1s2B 1 VT = 1.25 V 150 ps Jitter, Absolute tjabs2B 1 VT = 1.25 V -250 +250 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPUCLKC/T TA = 0 - 70º C; VDD = 3.3 V +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current Source Output Impedance ZO VO = VX 3000 Ω Output High Voltage VOH 0.71 1.2 V Output High Current IOH -13.92 mA Rise Time1 tr VOL = 20%, VOH = 80% 175 700 ps Differential Crossover Voltage1 VX N o t e 3 4 55 05 5% Duty Cycle1 dt VT = 50% 45 51 55 % Skew 1, CPU to CPU tsk VT = 50% 150 ps Jitter, Cycle-to-cycle1 tjcyc-cyc VT = VX 200 ps Notes: 1 - Guaranteed by design, not 100% tested in production. VR = 475W +1%; IREF = 2.32mA; IOH = 6*IREF

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 66.66 MHz Output Impedance R DSP1 1 VO = VDD *(0.5) 12 55 Ω Output High Voltage V OH1 IOH = -1 mA 2.4 V Output Low Voltage V OL1 IOL = 1 mA 0.4 V Output High Current I OH1 VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 -33 mA Output Low Current I OL1 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA Rise Time t r1 1 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns Fall Time t f1 1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns Duty Cycle d t1 1 VT = 1.5 V 45 55 % Skew t sk1 1 VT = 1.5 V 500 ps Jitter tjcyc-cyc1 VT = 1.5 V 250 ps 1Guarenteed by design, not 100% tested in production. Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F0 1 33.33 MHz Output Impedance R DSN1 1 VO = VDD *(0.5) 12 55 Ω Output High Voltage V OH1 IOH = -1 mA 2.4 V Output Low Voltage V OL1 IOL = 1 mA 0.55 V Output High Current I OH1 VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 -33 mA Output Low Current I OL1 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 38 mA Rise Time t r1 1 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns Fall Tim e t f1 1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns Duty Cycle d t1 1 VT = 1.5 V 45 55 % Skew t sk 1 1 VT = 1.5 V 500 ps Jitter tjcy c-cy c 1 VT = 1.5 V 250 ps 1Guarenteed by design, not 100% tested in production.

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Electrical Characteristics - REF TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 MHz Output Impedance R DSP1 1 VO = VDD *(0.5) 20 60 Ω Output High Voltage V OH1 IOH = -1 mA 2.4 V Output Low Voltage V OL1 IOL = 1 mA 0.4 V Output High Current I OH1 VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -29 -23 mA Output Low Current I OL1 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 29 27 mA Rise Time t r1 1 VOL = 0.4 V, VOH = 2.4 V 1 4 ns Fall Time t f1 1 VOH = 2.4 V, VOL = 0.4 V 1 4 ns Duty Cycle d t1 1 VT = 1.5 V 45 55 % Jitter tjcyc-cyc VT = 1.5 V 500 ps 1Guarenteed by design, not 100% tested in production. Electrical Characteristics - 48MHz TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O 1 VO = VDD *(0.5) 48 MHz Output Impedance R DSN1 1 VO = VDD *(0.5) 12 55 Ω Output High Voltage V OH1 IOH = -1 mA 2.4 V Output Low Voltage V OL1 IOL = 1 mA 0.55 V Output High Current I OH1 VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -29 -23 m A Output Low Current I OL1 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 29 27 mA 48DOT Rise Time t r1 1 VOL = 0.4 V, VOH = 2.4 V 0.5 1 ns 48DOT Fall Time t f1 1 VOH = 2.4 V, VOL = 0.4 V 0.5 1 ns VCH 48 U SB Rise Time tr 1 VOL = 0.4 V, VOH = 2.4 V 1 2 ns VCH 48 U SB Fall Tim e tf1 VOH = 2.4 V, VOL = 0.4 V 1 2 ns

48 DOT to 48 USB

Skew tskew1 VT=1.5V 1 ns Duty Cycle d t1 1 VT = 1.5 V 45 55 % Jitter tjcy c-cy c 1 VT = 1.5 V 350 ps 1Guarenteed by design, not 100% tested in production.

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Fig. 1 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when Via to VDD Clock trace to load Series Term. Res. Programming Header Via to Gnd Device Pad 2K /c87 8.2K/c87 a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz VCO Internal 0ns 25ns 50ns CPU 100MHz 3.3V 66MHz PCI 33MHz APIC 16.7MHz PD# SDRAM 100MHz REF 14.318MHZ 48MHZ

Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS950905 Advance Information Group Offset Waveforms Cycle Repeats 0ns CPU 66MHz CPU 100MHz CPU 133MHz SDRAM 133MHz SDRAM 100MHz 3.5V 66MHz PCI 33MHz APIC 16.7MHz REF 14.318MHz USB 48MHz 10ns 20ns 30ns 40ns

Systems, Inc. ICS950905 Advance Information For more information on Integrated Circuit Systems Inc. or any of our products please visit our web site at: http://www.icst.com Registered Company 9001

Ordering Information

Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device Example: ICS XXXX y F - T INDEX AREA INDEX AREA 121 2 N D h x 45°h x 45° E1 E /c97 SEATING PLANE SEATING PLANE A e -C-- C - b c L 300 mil SSOP Package MIN MAX MIN MAX A 2.41 2.80 .095 .110 A1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 D E 10.03 10.68 .395 .420 E1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 L 0.50 1.02 .020 .040 N α 0° 8° 0° 8° MIN MAX MIN MAX 48 15.75 16.00 .620 .630 10-0034 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS SEE VARIATIONS SEE VARIATIONS 0.635 BASIC 0.025 BASIC Reference Doc.: JEDEC Publication 95, MO-118 VARIATIONS SEE VARIATIONS SEE VARIATIONS N D mm. D (inch)

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.

Product Information

950905 specifications and overview.

Summary

Programmable Timing Control Hub™ for P4™ Mar 2020

Description

Programmable Timing Control Hub™ for P4™ Mar 2020

Source title 950905 Datasheet(PDF) - Renesas Technology Corp

Related Parts

More parts from the same family.

Browse manufacturer