950812YGLFT

ICS950812 IDT | Alldatasheet

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IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 Frequency Generator with 200MHz Differential CPU Clocks DATASHEET Pin ConfigurationRecommended Application: CK-408 clock with Buffered/Unbuffered mode supporting Almador, Brookdale, ODEM, and Montara-G chipsets with PIII/ P4 processor. Programmable for group to group skew. Output Features:

3 0.7V Differential CPU Clock Pairs 7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks 3 PCI_F (3.3V) @ 33.3MHz 1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz 1 REF (3.3V) @ 14.318MHz 5 3V66 (3.3V) @ 66.6MHz 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN or 66.6MHz Features: Provides standard frequencies and additional 5% and 10% over-clocked frequencies Supports spread spectrum modulation: No spread, Center Spread (±0.35%, ±0.5%, or ±0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%) Offers adjustable PCI early clock via latch inputs Selectable 1X or 2X strength for REF via I 2C interface Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. Uses external 14.318MHz crystal Stop clocks and functional control available through I 2C interface. Key Specifications:
CPU Output Jitter <150ps 3V66 Output Jitter <250ps 66MHz Output Jitter (Additive) (Buffered Mode) <100ps CPU Output Skew <100ps Note: Almador board level designs MUST use pin 22, 66MHZ_OUT1, as the feedback connection from the clock buffer path to the Almador (GMCH) chipset. VDDREF 1 56 REF X1 2 55 FS1 X2 3 54 FS0 GND 4 53 CPU_STOP#* PCICLK_F0 5 52 CPUCLKT0 PCICLK_F1 65 1 CPUCLKC0 PCICLK_F2 7 50 VDDCPU VDDPCI 8 49 CPUCLKT1 GND 9 48 CPUCLKC1 PCICLK0 10 47 GND E_PCICLK1/PCICLK1 11 46 VDDCPU PCICLK2 12 45 CPUCLKT2 E_PCICLK3/PCICLK3 13 44 CPUCLKC2 VDDPCI 14 43 MULTSEL* GND 15 42 IREF PCICLK4 16 41 GND PCICLK5 17 40 FS2 PCICLK6 18 39 48MHz_USB/FS3 VDD3V66 19 38 48MHz_DOT GND 20 37 VDD48 66MHZ_OUT0/3V66_2 21 36 GND 66MHZ_OUT1/3V66_3 22 35 3V66_1/VCH_CLK/FS4 66MHZ_OUT2/3V66_4 23 34 PCI_STOP#* 66MHZ_IN/3V66_5 24 33 3V66_0/FS5 ** *PD# 25 32 VDD3V66 VDDA 26 31 GND GND 27 30 SCLK Vtt_PWRGD# 28 29 SDATA 56-Pin 300mil SSOP 6.10 mm. Body, 0.50 mm. pitch TSSOP *These inputs have 120K internal pull-up resistors to VDD. **Internal pull-down resistors to ground. ICS950812 Block Diagram PLL2 PLL1 Spread Spectrum 3V66_5/66MHz_IN 3V66_3/66MHz_OUT1 3V66_(4,2)/66MHz_OUT(2,0) 48MHz_USB 48MHz_DOT XTAL OSC 3V66 DIVDER PD# CPU_STOP# PCI_STOP# MULTSEL SDATA SCLK FS (5:0) I REF Control Logic Config. Reg. REF 3V66_0 CPU DIVDER

3 CPUCLKT (2:0)

CPUCLKC (2:0) Stop 3V66_1/VCH_CLK PCICLK (6:4, 2, 0)PCI DIVDER PCICLK_F (2:0) Stop E_PCICLK(1,3)/PCICLK(1,3)2 VTT_PWRGD# Frequency Select 66MHz_OU T (2:0) 66MHz_IN PCICLK_F 3V66 (4:2) 3V66_5 PCICLK FS2 FS1 FS0 MHz MHz MHz MHz MHz 1 0 0 66.66 66.66 66MHz_IN Input 66MHz_IN/2 1 0 1 100.00 66.66 66MHz_IN Input 66MHz_IN/2 1 1 0 200.00 66.66 66MHz_IN Input 66MHz_IN/2 1 1 1 133.33 66.66 66MHz_IN Input 66MHz_IN/2 CPUCLK 3V66Bit

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 2 X1 IN Crystal input, Nominally 14.318MHz. 3 X2 OUT Crystal output, Nominally 14.318MHz 4 GND PWR Ground pin. 5 PCICLK_F0 OUT Free running PCI clock not affected by PCI_STOP# . 6 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# . 7 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP# . 8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 9 GND PWR Ground pin. 10 PCICLK0 OUT PCI clock output. 11 E_PCICLK1/PCICLK1 I/O Early/Normal PCI clock output latched at power up. 12 PCICLK2 OUT PCI clock output. 13 E_PCICLK3/PCICLK3 I/O Early/Normal PCI clock output latched at power up. 14 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 15 GND PWR Ground pin. 16 PCICLK4 OUT PCI clock output. 17 PCICLK5 OUT PCI clock output. 18 PCICLK6 OUT PCI clock output. 19 VDD3V66 PWR Power pin for the 3V66 clocks. 20 GND PWR Ground pin. 21 66MHZ_OUT0/3V66_2 OUT 3.3V 66.66MHz clock output selected via buffered or internal VCO. 22 66MHZ_OUT1/3V66_3 OUT 3.3V 66.66MHz clock output selected via buffered or internal VCO. 23 66MHZ_OUT2/3V66_4 OUT 3.3V 66.66MHz clock output selected via buffered or internal VCO. 24 66MHZ_IN/3V66_5 I/O 3.3V 66.66MHz clock from internal VCO, 66MHZ input to 66MHz output and PCI. 25 *PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. 26 VDDA PWR 3.3V power for the PLL core. 27 GND PWR Ground pin.

28 Vtt_PWRGD# IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input.

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Pin Description (continued) PIN # PIN NAME PIN TYPE DESCRIPTION

29 SDATA I/O Data pin for I2C circuitry 5V tolerant

30 SCLK IN Clock pin of I2C circuitry 5V tolerant

31 GND PWR Ground pin. 32 VDD3V66 PWR Power pin for the 3V66 clocks. 33 3V66_0/FS5** I/O Frequency select latch input pin / 3.3V 66.66MHz clock output.

34 PCI_STOP#* IN Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input

35 3V66_1/VCH_CLK/FS4 I/O Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz VCH clock output. 36 GND PWR Ground pin. 37 VDD48 PWR Power pin for the 48MHz output.3.3V 38 48MHz_DOT OUT 48MHz clock output. 39 48MHz_USB/FS3 I/O Frequency select latch input pin / 3.3V 48MHz clock output. 40 FS2 IN Frequency select pin. 41 GND PWR Ground pin.

42 IREF OUT

This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 43 MULTSEL* IN 3.3V LVTTL input for selection the current multiplier for CPU outputs 44 CPUCLKC2 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 45 CPUCLKT2 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 46 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 47 GND PWR Ground pin. 48 CPUCLKC1 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 49 CPUCLKT1 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 50 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 51 CPUCLKC0 OUT Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 52 CPUCLKT0 OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias.

53 CPU_STOP#* IN Stops all CPUCLK besides the free running clocks

54 FS0 IN Frequency select pin. 55 FS1 IN Frequency select pin. 56 REF OUT 14.318 MHz reference clock.

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Frequency Select Table 2 Frequency Select Table 1 66MHz_OU T (2:0) 66MHz_IN FS FS FS 0 3V66 (4:2) 3V66 _5 1 0 0 66.66 66.66 66MHz_IN Input 66MHz_IN/2 14.318 48.008 1 0 1 100.00 66.66 66MHz_IN Input 66MHz_IN/2 14.318 48.008 1 1 0 200.00 66.66 66MHz_IN Input 66MHz_IN/2 14.318 48.008 1 1 1 133.33 66.66 66MHz_IN Input 66MHz_IN/2 14.318 48.008 0 1 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 0 0 70.00 70.00 66MHz_IN Input 66MHz_IN/2 14.318 48.008 1 0 1 105.00 70.00 66MHz_IN Input 66MHz_IN/2 14.318 48.008 1 1 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 1 1 140.00 70.00 66MHz_IN Input 66MHz_IN/2 14.318 48.008 5% Overclocking 0 1 0 Test/2 Test/4 Test/4 Test/4 Test/8 Test Test/2 Test 1 0 0 73.32 73.32 66MHz_IN Input 66MHz_IN/2 14.318 48.008 1 0 1 110.00 73.32 66MHz_IN Input 66MHz_IN/2 14.318 48.008 1 1 0 Test/2 Test/4 Test/4 Test/4 Test/8 Test Test/2 Test 1 1 1 146.60 73.32 66MHz_IN Input 66MHz_IN/2 14.318 48.008 10% Overclocking 10% Overclocking 10% Overclocking Standard Clocking Standard Clocking 5% Overclocking 5% Overclocking 110 (See table 2) 111 (See table 2) REF MHz USB/DOT MHz Clocking Mode Freq Sel CPU MHz 3V66 MHz FS(5:3) PCI MHz From 000 to 101 (See table 2) FS FS FS 000 001 010 011 100 101 110 111 +/-0.35%, Center Spread 0 to -1.5%, Down Spread +/-0.5%, Center Spread +/-0.75%, Center Spread +/-0.35%, Center Spread 10% Overclocking Clocking Mode No Spread (default) or +/-0.4% 0 to -0.5%, Down Spread 0 to -1.0%, Down SpreadStandard Clocking Standard Clocking Standard Clocking Standard Clocking CPU, 3V66, 66MHz_OUT, 66MHz_IN, PCI 5% Overclocking Freq Sel Standard Clocking Standard Clocking Note : To enable spread, Byte 0 Bit 7 must be set to 1.

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Maximum Allowed Current Host Swing Select Functions MULTSEL PCI Select Functions Note: * Approximate values Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static in puts = Vdd or GND 40mA 280mA Condition Powerdown Mode (PD# = 0) Active Full Board Target Trace/Term Z Reference R, Iref = VDD/3*Rr Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA 50 ohms 50 ohms Output Current Ioh = 4 * I REF Ioh = 6 * I REF 1.0V @ 50 ohm 0.7V @ 50 ohm Voh @ Z E_PCICLK1 (11) E_PCICLK3 (13) E_PCICLK(3,1)* E_PCICLK1 = 10Kohm resistor. 0 0 0ns 0 1 0.5ns 1.0ns 1 1 1.5ns E_PCICLK3 = 10Kohm resistor. 0 = No resistor 1 = 10Kohm pull-up to VDD.

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Table 3 PCI_STOP# I2C Control Table-Byte 0, Bit 3 Note: When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped. Table 4 CPUCLKT/C (2:0) Outputs I2C Control Table Note: Individual CPUCLK outputs are controlled by Byte 1, Bit 3, 4, and 5. Table 5 PCICLK_F (2:0) Outputs I2C Control Table Note: Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5. Table 6 3V66 (5:2)/66MHz_OUT(2:0)/66MHz_IN I2C Control Table Note: Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 21, 22, 23, and 24. CPU_STOP# (Pin 53) Byte 5 Bit 5 3V66 (5:2) (Driven) 66MHZ_OUT(2:0)/66MHZ_IN (Buffered) 1\`1 Byte 0, Bit 3 Read Bit (Internal Status) PCI_STOP# (Pin 34) CPU_STOP# (Pin 53) Byte 1 Bit 3, 4, 5 Byte 0 Bit 3 Write Bit CPUCLKT/C (2:0) Outputs

00 S t o p

01 R u n n i n g

10 R u n n i n g

11 R u n n i n g

PCI_STOP# (Pin 34) Byte 3 Bit 3, 4, 5 PCICLK (2:0) Outputs

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks F S 5F S 4F S 3F S 1F S 0 Freq Center Down 11 12 13 14 11 12 13 14 000000 66.66 Center 0.40% 8D 9B 02 18 10001101 10011011 00000010 00011000 100001 99.99 Center 0.40% 8D 9B 02 18 10001101 10011011 00000010 00011000 200010 199.98 Center 0.40% 8D 9B 02 18 10001101 10011011 00000010 00011000 300011 133.32 Center 0.40% 8D 9B 02 18 10001101 10011011 00000010 00011000 400100 66.50 Down -0.48% 8D 9A EF 17 10001101 10011010 11101111 00010111 500101 99.75 Down -0.48% 8D 9A EF 17 10001101 10011010 11101111 00010111 600110 199.50 Down -0.48% 8D 9A EF 17 10001101 10011010 11101111 00010111 700111 133.00 Down -0.48% 8D 9A EF 17 10001101 10011010 11101111 00010111 801000 66.34 Down -0.98% 8D 99 E7 17 10001101 10011001 11100111 00010111 901001 99.51 Down -0.98% 8D 99 E7 17 10001101 10011001 11100111 00010111 1 0 01010 199.02 Down -0.98% 8D 99 E7 17 10001101 10011001 11100111 00010111 1 1 01011 132.68 Down -0.98% 8D 99 E7 17 10001101 10011001 11100111 00010111 1 2 01100 66.16 Down -1.52% 90 EB DD 17 10010000 11101011 11011101 00010111 1 3 01101 99.23 Down -1.52% 90 EB DD 17 10010000 11101011 11011101 00010111 1 4 01110 198.47 Down -1.52% 90 EB DD 17 10010000 11101011 11011101 00010111 1 5 01111 132.31 Down -1.52% 90 EB DD 17 10010000 11101011 11011101 00010111 1 6 10000 66.66 Center 0.51% 8D 9B 05 18 10001101 10011011 00000101 00011000 1 7 10001 99.99 Center 0.51% 8D 9B 05 18 10001101 10011011 00000101 00011000 1 8 10010 199.98 Center 0.51% 8D 9B 05 18 10001101 10011011 00000101 00011000 1 9 10011 133.32 Center 0.51% 8D 9B 05 18 10001101 10011011 00000101 00011000 2 0 10100 66.66 Center 0.74% 8D 9B 0B 18 10001101 10011011 00001011 00011000 2 1 10101 99.99 Center 0.74% 8D 9B 0B 18 10001101 10011011 00001011 00011000 2 2 10110 199.98 Center 0.74% 8D 9B 0B 18 10001101 10011011 00001011 00011000 2 3 10111 133.32 Center 0.74% 8D 9B 0B 18 10001101 10011011 00001011 00011000 2 4 11000 70.00 Center 0.35% 8D B0 35 19 10001101 10110000 00110101 00011001 2 5 11001 105.00 Center 0.35% 8D B0 35 19 10001101 10110000 00110101 00011001 2 6 11010 210.00 Center 0.35% 8D B0 35 19 10001101 10110000 00110101 00011001 2 7 11011 140.00 Center 0.35% 8D B0 35 19 10001101 10110000 00110101 00011001 2 8 11100 73.33 Center 0.34% 89 4A 68 1A 10001001 01001010 01101000 00011010 2 9 11101 109.99 Center 0.34% 89 4A 68 1A 10001001 01001010 01101000 00011010 3 0 11110 219.98 Center 0.34% 89 4A 68 1A 10001001 01001010 01101000 00011010 3 1 11111 146.65 Center 0.34% 89 4A 68 1A 10001001 01001010 01101000 00011010 I2C read back v alues in Hex. Bytes I2C read back values in binary.SpreadCPUADDRESS Table 8: Byte 11-14 Defaults Table 7 3V66 (0:1) I2C Control Table Note: Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 33 and 35. CPU_STOP# (Pin 53) Byte 5 Bit 4 3V66 (1:0) 0 0 Running 1 1 Running 0 1 Stopped 1 0 Running

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Absolute Maximum Ratings Supply Voltage 5.5 V Logic Inputs GND –0.5 V to V DD +0.5 V Ambient Operating Temperature 0°C to +90°C Case Temperature 115°C Storage Temperature –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 90°C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2 VDD+0. 3 V Input Low Voltage V IL VSS- 0.3 0.8 V IIH VIN = VDD; Inputs with no pull-down resistors 5.75 mA IIH VIN = VDD; Inputs with pull-down resistors 200 µA IIL1 VIN = 0 V; Inputs with no pull-up resistors -5.75 mA IIL2 VIN = 0 V; Inputs with pull-up resistors -200 µA IDD3.3OP CL = Full load; Select @ 100 MHz 233 280 mA IDD3.3OP CL =Full load; Select @ 133 MHz 234 280 mA IDD3.3PD IREF=5 mA 20 52 mA IDD3.3PDHIz 0.289 0.5 mA Input Frequency F i VDD = 3.3 V 14.32 MHz Pin Inductance L pin 7n H CIN Logic Inputs 5 pF COUT Output pin capacitance 6 pF CINX X1 & X2 pins 27 30 45 pF Clk Stabilization1,2 TSTAB From PowerUp or deassertion of PowerDown to 1st clock. 12 . 1 m s tPZH,tPZL Output enable delay (all outputs) 1 12 ns tPHZ,tPLZ Output disable delay (all outputs) 1 12 ns 1Guaranteed by design, not 100% tested in production. 2See timing diagrams for buffered and un-buffered timing requirements. Delay1 Input Capacitance1 Input High Current Input Low Current Operating Supply Current Powerdown Current

1 VT = 50% 40 175 ps

1Guaranteed by design, not 100% tested in production.

2 IOWT

can be varied and is selectable thru the MULTSEL pin. VMeasured from Single Ended Waveform Electrical Characteristics - CPU (0.7V Select) 100MHz TA = 0 - 90°C; VDD=3.3V +/-5%; (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current Source Output Impedance Zo1 VO = Vx 3000 Ω Average Period T PERIOD Fig. 1 10.00 10.01 10.20 ns Voltage High VHigh 660 720 850 Voltage Low VLow -150 15 150 Max Voltage Vovs 750 1150 Min VoltageV u d s - 4 5 0 - 2 Crossing Voltage (abs) Vcross(abs) Fi g. 3 250 319 550 mV Crossing Voltage (var) d-Vcross Variation of crossing over all edges (Fig. 4) 12 140 mV Rise Time t r VOL = 0.175V, V OH = 0.525V (Fig. 3) 175 310 810 ps Fall Time t f VOH = 0.525V VOL = 0.175V (Fig. 3) 175 300 810 ps Rise Time Variation d-t r 10 125 ps Fall Time Variation d-t f 10 125 ps Duty Cycle d t3 Measurement from differential wavefrom (Fig 1) 45 51 55 % Skew t sk3 VT = 50% 16 100 ps Jitter, Cycle to cycle t jcyc-cyc 1 VT = 50% (Fig. 1) 48 175 ps 1Guaranteed by design, not 100% tested in production. can be varied and is selectable thru the MULTSEL pin. mVStatistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. mV

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Electrical Characteristics - PCICLK Buffered Mode TA = 0 - 90°C; VDD = 3.3V +/-5%; C L = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance RDSP1 1 VO = VDD*(0.5) 12 33 65 Ω Output High Voltage VOH 1 IOH = -1 mA 2.05 V Output Low Voltage VOL 1 IOL = 1 mA 0.65 V Output High Current IOH 1 VOH@MIN = 1.0V, V OH@MAX = 3.135V -33 -28 mA Output Low Current IOL 1 VOL @MIN = 1.95V, V OL @MAX = 0.4V 26 38 mA Rise Time t r1 Fall Time t f1 Duty Cycle d t1 1 VT = 1.5 V 45 52 55 % Skew tsk1 1 VT = 1.5 V 35 500 ps Jitter,cycle to cyc t jcyc-cyc 1 VT = 1.5 V (Additive) (Fig. 8) 60 120 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU (0.7V Select) 133.33MHz TA = 0 - 90°C; VDD=3.3V +/-5%; (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current Source Output Impedance Zo1 VO = Vx 3000 Ω Average Period T PERIOD Fig. 1 7.50 7.51 7.65 ns Voltage High VHigh 660 718 850 Voltage Low VLow -150 17 150 Max Voltage Vovs 730 1150 Min Voltage Vuds -450 7 Crossing Voltage (abs) Vcross(abs) Fig. 3 250 340 550 mV Crossing Voltage (var) d-Vcross Variation of crossing over all edges (Fig. 4) 15 140 mV Rise Time t r VOL = 0.175V, V OH = 0.525V (Fig. 3) 175 310 810 ps Fall Time t f VOH = 0.525V VOL = 0.175V (Fig. 3) 175 315 810 ps Rise Time Variation d-t r 5 125 ps Fall Time Variation d-t f 5 125 ps Duty Cycle d t3 Measurement from differential wavefrom (Fig 1) 45 51 55 % Skew t sk3 VT = 50% 14 100 ps Jitter, Cycle to cycle t jcyc-cyc 1 VT = 50% (Fig. 1) 75 175 ps 1Guaranteed by design, not 100% tested in production. can be varied and is selectable thru the MULTSEL pin. Statistical measurement on single ended signal using oscilloscope math function. mV Measurement on single ended signal using absolute value. mV

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Electrical Characteristics - PCICLK Un-Buffered Mode TA = 0 - 90°C; VDD=3.3V +/-5%; C L = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance RDSP1 1 VO = VDD*(0.5) 12 33 65 Ω Average Period T PERIOD Fig. 8 30.00 30.01 ns Output High Voltage VOH 1 IOH = -1 mA 2.05 V Output Low Voltage VOL 1 IOL = 1 mA 0.65 V Output High Current IOH 1 VOH@MIN = 1.0V, V OH@MAX = 3.135V -33 -28 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, V OL @MAX = 0.4 V 26 38 mA Rise Time tr1 Fall Time tf1 Duty Cycle d t1 1 VT = 1.5 V (Fig. 8) 45 50 55 % Skew tsk1 1 VT = 1.5 V 65 500 ps Jitter,cycle to cyc t jcyc-cyc 1 VT = 1.5 V (Fig. 8) 101 290 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics- 3V66 - Buffered Mode: 66MHz_OUT [2:0] TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance RDSP1 1 VO = VDD*(0.5) 12 33 65 Ω Output High Voltage VOH 1 IOH = -1 mA 2.05 V Output Low Voltage VOL 1 IOL = 1 mA 0.65 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -28 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 26 38 mA Rise Time tr1 Fall Time tf1 Duty Cycle dt1 1 VT = 1.5 V (Fig. 8) 45 52 55 % Jitter tjcyc-cyc 1 VT = 1.5 V 66MHz_OUT [2:0] (Additive) (Fig. 8) 83 120 ps Skew tsk1 1 VT = 1.5 V 66MHz_OUT [2:0] 169 250 ps 1Guaranteed by design, not 100% tested in production.

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0] TA = 0 - 90°C; VDD=3.3V +/-5%; C L = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Impedance RDSP1 1 VO = VDD*(0.5) 12 33 65 Ω Average Period T PERIOD Fig. 8 15.00 15.01 15.30 ns Output High Voltage VOH 1 IOH = -1 mA 2.05 V Output Low Voltage VOL 1 IOL = 1 mA 0.65 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -28 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, V OL @MAX = 0.4 V 26 38 mA Rise Time tr1 Fall Time tf1 Duty Cycle d t1 1 VT = 1.5 V (Fig. 8) 45 48 55 % Skew t sk1 1 VT = 1.5 V 40 250 ps Jitter t jcyc-cyc 1 VT = 1.5 V (Fig. 8) 133 290 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency FO1 Fig. 8 48 MHz Output Impedance RDSP1 1 VO = VDD*(0.5) 20 48 70 Ω Output High Voltage VOH 1 IOH = -1 mA 2.05 V Output Low Voltage VOL 1 IOL = 1 mA 0.5 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -20 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 25 27 mA 48DOT Rise Time tr1 48DOT Fall Time tf1 VCH 48 USB Rise Time tr1 VCH 48 USB Fall Time tf1

48 DOT Duty Cycle dt1

1 VT = 1.5 V (Fig. 8) 45 53 55 % VCH 48 USB Duty Cycle dt1 1 VT = 1.5 V (Fig. 8) 45 53 55 %

48 DOT Jitter tjcyc-cyc

1 VT = 1.5 V (Fig. 8) 183 410 ps USB to DOT Skew tsk1 1 VT = 1.5 V (180 degrees out of phase) 0.43 1 ns VCH Jitter tjcyc-cyc 1 VT = 1.5 V (Fig. 8) 157 410 ps 1Guaranteed by design, not 100% tested in production.

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Electrical Characteristics - REF (1X select) TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency FO1 Fig. 8 14.318 MHz Output Impedance RDSP1 1 VO = VDD*(0.5) 20 48 70 Ω Output High Voltage VOH 1 IOH = -1 mA 2.05 V Output Low Voltage VOL 1 IOL = 1 mA 0.45 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -25 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 25 27 mA Rise Time tr1 Fall Time tf1 Duty Cycle dt1 1 VT = 1.5 V 45 53 55 % Jitter tjcyc-cyc 1 VT = 1.5 V (Fig. 8) 180 1200 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF (2X select) TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 20-40 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency FO1 Fig. 8 14.318 MHz Output Impedance RDSP1 1 VO = VDD*(0.5) 12 33 65 Ω Output High Voltage VOH 1 IOH = -1 mA 2.05 V Output Low Voltage VOL 1 IOL = 1 mA 0.65 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -28 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 26 38 mA Rise Time tr1 Fall Time tf1 Duty Cycle dt1 1 VT = 1.5 V 45 53 55 % Jitter tjcyc-cyc 1 VT = 1.5 V (Fig. 8) 180 1200 ps 1Guaranteed by design, not 100% tested in production.

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks General SMBus serial interface information for the ICS950812 How to Write:

Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit ICS (Slave/Receiver) T WR ACK ACK ACK ACK ACK P stoP bit X Byte Index Block Write Operation Slave Address D2(H) Beginning Byte = N WRite starT bit Controller (Host) Byte N + X - 1 Data Byte Count = X Beginning Byte N T starT bit WR WRite RT Repeat starT RD ReaD Beginning Byte N Byte N + X - 1 N Not acknowledge Ps t o P b i t Slave Address D3(H) Index Block Read Operation Slave Address D2(H) Beginning Byte = N ACK ACK Data Byte Count = X ACK ICS (Slave/Receiver)Controller (Host) X Byte ACK ACK

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Pin # Name 0 1 PWD Bit 7 - Spread Enabled Spread Spectrum Control RW OFF ON 0 Bit 6 - CPUCLKT(2:0) Power down mode output level 0= CPU driven in power down 1= undriven RW HIGH LOW 0 Bit 5 35 3V66_1/VCH_CLK/FS4** VCH/66.66 Select RW 66.66 48.00 0 Bit 4 53 CPU_STOP#* Reflects value of pin R Stop Active X Bit 3 34 PCI_STOP#* Reflects value of pin at power up. Also can be set. RW Stop Active X Bit 2 39 FS3 Frequency Selection RW - - X Bit 1 55 FS1 Frequency Selection R - - X Bit 0 54 FS0 Frequency Selection R - - X Note: For PCI_STOP# function, refer to table 3. Type Bit ControlControl FunctionAffected PinBYTE Pin # Name 0 1 PWD Bit 7 43 MULTSEL* Reflects value of pin R - - x Bit 6 - CPUCLKT(2:0) CPU_Stop mode output level 0= CPU driven when stopped 1 = undriven RW HIGH LOW 0 Bit 5 45, 44 CPUCLKT2, CPUCLKC2 (see note) Allow control of output with assertion of CPU_STOP#. RW Not Freerun Freerun 0 Bit 4 49, 48 CPUCLKT1, CPUCLKC1 (see note) Allow control of output with assertion of CPU_STOP#. RW Not Freerun Freerun 0 Bit 3 52, 51 CPUCLKT0, CPUCLKC0 (see note) Allow control of output with assertion of CPU_STOP#. RW Not Freerun Freerun 0 Bit 2 45, 44 CPUCLKT2, CPUCLKC2 Output control RW Disable Enable 1 Bit 1 49, 48 CPUCLKT1, CPUCLKC1 Output control RW Disable Enable 1 Bit 0 52, 51 CPUCLKT0, CPUCLKC0 Output control RW Disable Enable 1 Note: Type Bit ControlControl FunctionAffected PinBYTE CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4. Pin # Name 0 1 PWD Bit 7 56 REF 1X or 2X Strength control RW 1X 2X 0 Bit 6 18 PCICLK6 Output control RW Disable Enable 1 Bit 5 17 PCICLK5 Output control RW Disable Enable 1 Bit 4 16 PCICLK4 Output control RW Disable Enable 1 Bit 3 13 E_PCICLK3/PCICLK3 Output control RW Disable Enable 1 Bit 2 12 PCICLK2 Output control RW Disable Enable 1 Bit 1 11 E_PCICLK1/PCICLK1 Output control RW Disable Enable 1 Bit 0 10 PCICLK0 Output control RW Disable Enable 1 Note: BYTE

2 Control Function Bit Control

PCICLK(6:0) can be turned on/off by PCI_STOP#. Refer to table 3. Affected Pin Type Pin # Name 0 1 PWD Bit 7 38 48MHz_DOT Output control RW Disable Enable 1 Bit 6 39 48MHz_USB/FS3** Output control RW Disable Enable 1 Bit 5 7 PCICLK_F2 (see note) Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 4 6 PCICLK_F1 (see note) Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 3 5 PCICLK_F0 (see note) Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 2 7 PCICLK_F2 Output control RW Disable Enable 1 Bit 1 6 PCICLK_F1 Output control RW Disable Enable 1 Bit 0 5 PCICLK_F0 Output control RW Disable Enable 1 Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5. BYTE

3 Control FunctionAffected Pin Bit Control Type

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Pin # Name 0 1 PWD Bit 7 35 FS4 Frequency Selection RW Disable Enable X Bit 6 33 FS5 Frequency Selection RW Disable Enable X Bit 5 33 3V66_0/FS5 Output control RW Disable Enable 1 Bit 4 35 3V66_1/VCH_CLK/FS4 Output control RW Disable Enable 1 Bit 3 24 66MHZ_IN/3V66_5 Output control RW Disable Enable 1 Bit 2 23 66MHZ_OUT2/3V66_4 Output control RW Disable Enable 1 Bit 1 22 66MHZ_OUT1/3V66_3 Output control RW Disable Enable 1 Bit 0 21 66MHZ_OUT0/3V66_2 Output control RW Disable Enable 1 TypeControl FunctionAffected PinBYTE Bit Control Pin # Name 0 1 PWD Bit 7 X - Unused - - - 0 Bit 6 X - Reserved X - - 0 Bit 5 X 3V66(5:2)/66MHZ_OUT(2:0) (See table 6) Allow control of output with assertion of CPU_STOP#. X Freerun Not Freerun 0 Bit 4 X 3V66(1:0) (See table 7) Allow control of output with assertion of CPU_STOP#. X Freerun Not Freerun 0 Bit 3 RW - - 0 Bit 2 RW - - 0 Bit 1 RW - - 0 Bit 0 RW - - 0 Note: Control Function 00 = Medium (default), 01 = Low, 11,10 =High Type 38 48MHz_DOT Slew Control Affected PinBYTE Functions in Byte 5 of CK408 were intended as a test and debug byte only. 00 = Medium (default), 01 = Low, 11,10 =High Bit Control 48MHz_USB Slew Control39 Pin # Name 0 1 PWD Bit 7 X Revision ID Bit 3 R - - X Bit 6 X Revision ID Bit 2 R - - X Bit 5 X Revision ID Bit 1 R - - X Bit 4 X Revision ID Bit 0 R - - X Bit 3 X Vendor ID Bit 3 (Reserved) R - - 0 Bit 2 X Vendor ID Bit 2 (Reserved) R - - 0 Bit 1 X Vendor ID Bit 1 (Reserved) R - - 0 Bit 0 X Vendor ID Bit 0 (Reserved) R - - 1 Revision ID Value Based on Device Revision Control Function Type Bit ControlAffected PinBYTE Pin # Name 0 1 PWD Bit 7 X - Unused R - - 0 Bit 6 X - Unused R - - 0 Bit 5 X - Unused R - - 0 Bit 4 X - Unused R - - 0 Bit 3 X - Unused R - - 0 Bit 2 X - Unused R - - 0 Bit 1 X - Unused R - - 0 Bit 0 X - Unused R - - 0 TypeControl Function Bit ControlAffected PinBYTE Pin # Name 0 1 PWD Bit 7 X - (Reserved) X - - 0 Bit 6 X - (Reserved) X - - 0 Bit 5 X - (Reserved) X - - 0 Bit 4 X - (Reserved) X - - 0 Bit 3 X - R - - 1 Bit 2 X - R - - 1 Bit 1 X - R - - 1 Bit 0 X - R - - 1 Note: Byte 8 is for ICS test only. Do not write as system damage may occur. Bit(3:0) contain the readback Byte count. Bit ControlAffected Pin Control Function Readback Byte Count TypeBYTE

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Pin # Name 0 1 PWD Bit 7 RW - - 0 Bit 6 RW - - 0 Bit 5 RW - - 0 Bit 4 RW - - 0 Bit 3 RW - - 0 Bit 2 RW - - 0 Bit 1 RW - - 0 Bit 0 RW - - 0 Bit Control 00 (default), 11 = Medium 01 = Low, 10 =High 00 (default), 11 = Medium 10 = Low, 01 =High 00 (default), 11 = Medium 10 = Low, 01 =High 00 = High(default), 01 = Low, 11,10 = MediumVCHCLK Slew Control TypeBYTE Affected Pin Control Function 7, 6, 5 PCICLK_F (2:0) Slew Contol 13, 12, 11, 10 PCICLK (3:0) Slew Contol 1 8, 1 7, 1 6, 13 , 12 , 11, 10PCICLK (6:0) Slew Contol Pin # Name 0 1 PWD Bit 7 X - M/N Enable (Enable access to Byte 11 - 14) RW HW/B0 Byte (11-14) 0 Bit 6 X - Unused - - - 0 Bit 5 RW - - 0 Bit 4 RW - - 0 Bit 3 RW - - 0 Bit 2 RW - - 0 Bit 1 X - Unused - - - 0 Bit 0 X - Unused - - - 0 Bit ControlControl Function TypeBYTE Affected Pin 24, 23, 22, 21 3V66(5:2)/66MHZ_OUT(2:0) Skew Approx 250ps per bit (Ref to PCI) 33, 35 3V66(1:0) Skew Approx 250ps per bit (Ref to PCI) Pin # Name 0 1 PWD Bit 7 X - VCO Divider Bit8 RW - - X Bit 6 X - REF Divider Bit6 RW - - X Bit 5 X - REF Divider Bit5 RW - - X Bit 4 X - REF Divider Bit4 RW - - X Bit 3 X - REF Divider Bit3 RW - - X Bit 2 X - REF Divider Bit2 RW - - X Bit 1 X - REF Divider Bit1 RW - - X Bit 0 X - REF Divider Bit0 RW - - X Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the REF divider value. BYTE Affected Pin Control Function Type Bit Control Pin # Name 0 1 PWD Bit 7 X - VCO Divider Bit7 RW - - X Bit 6 X - VCO Divider Bit6 RW - - X Bit 5 X - VCO Divider Bit5 RW - - X Bit 4 X - VCO Divider Bit4 RW - - X Bit 3 X - VCO Divider Bit3 RW - - X Bit 2 X - VCO Divider Bit2 RW - - X Bit 1 X - VCO Divider Bit1 RW - - X Bit 0 X - VCO Divider Bit0 RW - - X Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divider value. Bit ControlBYTE Affected Pin Control Function Type

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Pin # Name 0 1 PWD Bit 7 X - Spread Spectrum Bit7 RW - - X Bit 6 X - Spread Spectrum Bit6 RW - - X Bit 5 X - Spread Spectrum Bit5 RW - - X Bit 4 X - Spread Spectrum Bit4 RW - - X Bit 3 X - Spread Spectrum Bit3 RW - - X Bit 2 X - Spread Spectrum Bit2 RW - - X Bit 1 X - Spread Spectrum Bit1 RW - - X Bit 0 X - Spread Spectrum Bit0 RW - - X Affected Pin Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure. BYTE

13 Control Function Type Bit Control

Pin # Name 0 1 PWD Bit 7 X - (Reserved) RW - - X Bit 6 X - (Reserved) RW - - X Bit 5 X - Spread Spectrum Bit13 RW - - X Bit 4 X - Spread Spectrum Bit12 RW - - X Bit 3 X - Spread Spectrum Bit11 RW - - X Bit 2 X - Spread Spectrum Bit10 RW - - X Bit 1 X - Spread Spectrum Bit9 RW - - X Bit 0 X - Spread Spectrum Bit8 RW - - X BYTE Affected Pin Control Function Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure. Bit ControlType Note: See table 8 for Byte 11-14 default information Spread Spectrum Enable Procedure Step 1: Power-up ---- Latched inputs, FS(5:0), set frequency per Hardware default on board. SS is off. BIOS program set IIC Byte0, bit7 to 1, SS will be enable Spread. Note that Byte 10, bit 7 is default to 0. This allows all setup to be controlled by the Frequency Select Tables, 1 and 2. Step 3: To set up Linear programming and SS% adjust using Byte 11 through 14, the BIOS must set Byte 10, bit 7 to a 1. This will enable access to Byte 11 and 12, M/N linear programming and Byte 13 and 14, Spread Spectrum % adjust. Step 2: After power up, SS% can be changed to the fixed selections shown in Frequency Table 2. This is achieved by Writing to Byte 4, bit 6/7 (FS5:4) and/or Byte 0 (FS3), The data written to these bytes will overwrite the existing contents and switch to the desired selection.

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation value. Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship Group to Group Skews at Common Transition Edges: Buffered Mode GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS 66MHz_IN 66MHz_OUT1,2 Tpd Propogation delay from 66MHz_IN to 66MHz_OUT (2:0) 2.5 2.9 4.5 ns 66MHz_OUT to PCI1,2 Tpci 66MHz_OUT (2:0) leads 33 MHz PCICLK 1.5 3.5 ns 1Guaranteed by design, not 100% tested in production. 2500ps Tolerance E_PCICLK to PCICLK Skews GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS TE_PCI-PCI1 E_PCICLK1 (pin 11)=0 E_PCICLK3 (pin 13)=1 0.3 0.5 0.7 ns TE_PCI-PCI2 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=0 0.8 1.0 1.2 ns TE_PCI-PCI3 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=1 1.3 1.5 1.7 ns 1Guaranteed by design, not 100% tested in production. E_PCICLK to PCICLK1 66MHz_IN 66MHz_OUT 3V66 Tpd Tpci No Relationship E_PCICLK (3,1) Tepci PCICLK_F (2:0) PCICLK (6:0)

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. Un-Buffered Mode 3V66 & PCI Phase Relationship Group to Group Skews at Common Transition Edges: Unbuffered Mode GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS 3V66 to PCI1,2 S3V66-PCI 3V66 (5:0) leads 33MHz PCI 1.5 2.55 3.5 ns 1Guarenteed by design, not 100% tested in production. 2500ps Tolerance 3V66 (1:0) 3V66 (4:2) 3V66_5 E_PCICLK (3,1) PCICLK_F (2:0) PCICLK (6:0) Tpci Tepci E_PCICLK to PCI CLK Skews GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS TE_PCI-PCI0 E_PCICLK1 (pin 11)=0 E_PCICLK3 (pin 13)=0 -0.2 0 0.2 ns E_PCICLK to PCICLK 1 TE_PCI-PCI1 E_PCICLK1 (pin 11)=0 E_PCICLK3 (pin 13)=1 0.3 0.5 0.7 ns TE_PCI-PCI2 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=0 0.8 1.0 1.2 ns TE_PCI-PCI3 E_PCICLK1 (pin 11)=1 E_PCICLK3 (pin 13)=1 1.3 1.5 1.7 ns

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next risin g edge. PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz tsu Assertion of PCI_STOP# Waveforms PCI_STOP# - Assertion (transition from logic "1" to logic "0") CPU_STOP# - Assertion (transition from logic "1" to logic "0") Assertion of CPU_STOP# Waveforms CPU_STOP# Functionality #POTS_UPCT UPCC UPC 1l amroNl amroN 0t luM*ferit aolF The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I 2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the I 2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not be driven. CPU_STOP# CPUCLKT CPUCLKC

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks PD# Functionality #DPT KLCUPCC KLCUPC6 6V3T UO_zHM66 F_KLCICP KLCICP KLCICP TOD/BSU zHM84 1l amroNl amroNz HM66N I_zHM66 2/NI_zHM662 /NI_zHM66 zHM84 0t luM*ferit aolFw oLw oLw oLw oLw oL CPU_STOP# - De-assertion (transition from logic "0" to logic "1") De-assertion of CPU_STOP# Waveforms All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de- assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of By te 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# de-assertion. When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU an d CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# - Assertion (transition from logic "1" to logic "0") Power Down Assertion of Waveforms 0ns PD# CPUCLKT 100MHz CPUCLKC 100MHz 3V66MHz 66MHz_IN 66MHz_OUT PCICLK 33MHz USB 48MHz REF 14.318MHz 25ns 50ns CPU_STOP# CPUCLKT(2:0) *CPUCLKT(2:0)TS CPUCLKC(2:0) Tdrive_CPU_STOP# <10ns @ 200mV *Signal TS is CPUCLKT in Tri-State mode

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks Power Down De-Assertion Mode The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping of the power supply until the time that stable clocks are output from the clock chip. If the I 2C Bit 6 of Byte 0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration. Test Configuration Diagrams CPU 1.0V Configuration test load board termination TLA TLB RREF=221 Ohms MULTSEL Pin must be Low Rs=33 Ohms Rs=33 Ohms Rp=63.4 Ohms 1% Rp=63.4 Ohms Rdif=475 Ohms 2pF 2pF CPUCLKT test point CPUCLKC test point CLK408 CPU 0.7V Configuration test load board termination TLA TLB MULTSEL Pin must be High Rs=33 Ohms Rs=33 Ohms Rp=49.9 Ohms 1% Rp=49.9 Ohms Rset=475 Ohms 2pF 2pF CPUCLKT test point CPUCLKC test point CLK408

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks INDEX AREA INDEX AREA 121 2 N D h x 45°h x 45° E1 E /c97 SEATING PLANE SEATING PLANE A e -C-- C - b c L 300 mil SSOP Package MIN MAX MIN MAX A 2.41 2.80 .095 .110 A1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 D E 10.03 10.68 .395 .420 E1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 L 0.50 1.02 .020 .040 N α 0° 8° 0° 8° MIN MAX MIN MAX 56 18.31 18.55 .720 .730 1 0-0034 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS SEE VARIATIONS SEE VARIATIONS 0.635 BASIC 0.025 BASIC Ref erence Do c.: JEDEC Pub licat io n 9 5, M O-118 VARIATIONS SEE VARIATIONS SEE VARIATIONS N D mm. D (inch)

Ordering Information

Example: Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) XXXX y F LF T

IDTTM Frequency Generator with 200MHz Differential CPU Clocks 0542J—01/25/10 ICS950812 Frequency Generator with 200MHz Differential CPU Clocks N D E1 E /c97 SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C 6.10 mm. Body, 0.50 mm. pitch TSSOP (240 mil) (20 mil) MIN MAX MIN MAX A- - 1 . 2 0 - - . 0 4 7 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D E E1 6.00 6.20 .236 .244 e L 0.45 0.75 .018 .030 N α 0° 8° 0° 8° VARIATIONS MIN MAX MIN MAX 56 13.90 14.10 .547 .555 1 0-0039 N D mm. D (inch) Ref erence Doc.: JEDEC Pub licat io n 95, M O-153 0.50 BASIC 0.020 BASIC SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS Example: Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) XXXX y G LF T

Frequency Generator with 200MHz Differential CPU Clocks Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc.

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Revision History

Rev. Issue Date Description Page # I 8/4/2005 1. Moved SMBus after page 22. 2. Corrected 3V66 Buffered mode on Electrical Characteristics Table. 3. Added DC Characteristics to REF2X Electrical Characteristics Table. 4. Updated LF Orderin g Information to RoHS Compliant. 11, 13, 28, 29 J 1/25/2010 Updated document template

Summary

Frequency Generator with 200MHz Differential CPU Clocks

Description