950811YFLFT | DigiCamel IC Datasheet

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Systems, Inc. ICS950811 0482E—08/09/07 Block Diagram Recommended Application: CK-408 clock for Brookdale-Mobile chipsets. Programmable for group to group skew. Output Features: 3 Differential CPU Clock Pairs (differential current mode) 7 PCI (3.3V) @ 33.3MHz 3 PCI_F (3.3V) @ 33.3MHz 1 USB (3.3V) @ 48MHz 1 DOT (3.3V) @ 48MHz 1 REF (3.3V) @ 14.318MHz 5 3V66 (3.3V) @ 66.6MHz 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features: Supports spread spectrum modulation, down spread 0 to -0.5%. Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. Key Specifications:

CPU Output Jitter <150ps 3V66 Output Jitter <250ps 66MHz Output Jitter (Buffered Mode Only) <100ps CPU Output Skew <100ps Pin Configuration 56 pin SSOP/TSSOP Frequency Generator with 200MHz Differential CPU Clocks Functionality * These inputs have 150K internal pull-up resistor to VDD. 2SF1 SF0 SF UPC )zHM( )0:1(66V3 )zHM( )0:2(tuOzHM66 )2:4(66V3 )zHM( F_ICP ICP )zHM( nIzHM66 )5(66V3 )zHM( 10 0 6 6.666 6.66 edoMdereffuB detroppuStoN 508059SCIeeS 10 1 0 0.0016 6.66 110 0 0.0026 6.66 11 1 3 3.3316 6.66 diM00 e tatsirTe tatsirTe tatsirTe tatsirTe tatsirT diM01 2 /KLCT4 /KLCT4 /KLCT8 /KLCT4 /KLCT diM1 0 -vreseR de devreseRd evreseRd evreseRd evreseR diM1 1 -vreseR de devreseRd evreseRd evreseRd evreseR

0482E—08/09/07 Pin Configuration REBMUNNIPE MANNIPE PYTN OITPIRCSED ,62,91,41,8,1 05,64,73,23 DDVR WPy lppusrewopV3.3

21 X latsyrC2X

tupnI tupnilatsyrCzHM813.41

32 X latsyrC1X

tuptuO tuptuolatsyrCzHM813.41 5,6,7 )0:2(F_KLCICPT UO rof#POTS_ICPybdetceffatonkcolcICPgninnureerF .tnemeganamrewop ,72,02,51,9,4 74,14,63,13 DNGR WPy lppusV3.3rofsnipdnuorG ,31,61,71,81 01,11,21 )0:6(KLCICPT UOs tuptuokcolcICP 12,22,32,42) 2:5(66V3T UOO CVlanretnimorf,skcolcecnereferzHM66 52# DPN I. woLevitcA.edomnwod-rewopsekovnI 82# DGRWP_ttV NI 92A TADS O/II rofnipataD 2 tnarelotV5yrtiucricC 03K LCS NII fonipkcolC 2 tnarelotV5yrtiucricC 330 _66V3T UOO CVlanretnimorf,skcolcecnereferzHM66 43# POTS_ICPN I tpecxewoltupninehw,level0cigoltaskcolcKLCICPstlaH gninnureerferahcihwF_KLCICP 53K LC_HCV/1_66V3T UO hguorhtelbatcelestuptuoV3.3 I2C lanretnimorfzHM66ebot )CSS-non(zHM84roOCV 83T OD_zHM84T UOT ODrofkcolctuptuozHM84 93B SU_zHM84T UOB SUrofkcolctuptuozHM84 042 SFN In oitcelesedoMroftupniV3.3laicepS 24F ERIT UO KLCUPCehtroftnerrucecnereferehtsehsilbatsenipsihT dnuorgotdeitrotsisernoisicerpdexifaseriuqernipsihT.sriap .tnerrucetairporppaehthsilbatseotredroni 340 LESTLUMN I UPCrofreilpitlumtnerrucehtgnitcelesroftupniLTTVLV3.3 stuptuo 15,84,44) 0:2(CKLCUPCT UO esehT.stuptuoUPCriaplaitnereffidfoskcolc"yrotnemelpmoC" rofderiuqererasrotsiserlanretxednastuptuotnerrucera .saibegatlov 25,94,54) 0:2(TKLCUPCT UO tnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT" .saibegatlovrofderiuqererasrotsiserlanretxednastuptuo 35# POTS_UPCN Iw oltupninehw,level0cigoltaskcolcKLCUPCstlaH 45,55) 0:1(SFN Is niptcelesycneuqerF 65F ERT UO. kcolcecnereferzHM813.41 Power Groups (Analog) VDDA = PLL1 VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR (Digital) VDDPCI VDD3V66 VDDCPU

0482E—08/09/07 Host Swing Select Functions Truth Table Maximum Allowed Current noitidnoC noitpmusnocylppusV3.3xaM ,sdaolpacetercsidxaM V564.3=ddV DNGroddV=stupnicitatsllA edoMnwodrewoP )0=#NWDRWP( Am04 evitcAlluF Am063 2SF1 SF0 SF UPC )zHM( 66V3 )0:1( )zHM( )0:2(ffuB66 )2:4(66V3 )zHM( /NI_zHM66 5_66V3 F_ICP ICP )zHM( 0FER )zHM( TOD/BSU )zHM( 100 6 6.666 6.66 detroppuStoNedoMdereffuB 508059SCIeeS 10 1 0 0.0016 6.66 110 0 0.0026 6.66 111 3 3.3316 6.66 diM0 0 e tatsirTe tatsirTe tatsirTe tatsirTe tatsirTe tatsirTe tatsirT diM01 2 /KLCT4 /KLCT4 /KLCT4 /KLCT8 /KLCTK LCT2 /KLCT diM1 0 d evreseRd evreseRd evreseRd evreseRd evreseRd evreseRd evreseR diM1 1 d evreseRd evreseRd evreseRd evreseRd evreseRd evreseRd evreseR 0LESITLUM tegraTdraoB ZmreT/ecarT ,RecnerefeR =ferI V DD )rR*3(/ tuptuO tnerruC Z@hoV 0 detroppuStoNedoMdereffuB 508059SCIeeS 1s mho05 ,%1574=rR Am23.2=ferI FERI*6=hoI0 5@V7.0

0482E—08/09/07 1. The ICS clock generator is a slave/receiver, I 2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol . 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I 2C interface, the protocol is set to use only " Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown. General I 2C serial interface information The information in this section assumes familiarity with I 2C programming. How to Write:

Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0) through byte 5
ICS clock will acknowledge each byte one at a time. How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit Notes: Controller (Host) ICS (Slave/Receiver) Start Bit Address D2(H) ACK Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit How to Write: Controller (Host) ICS (Slave/Receiver) Start Bit Address D3(H) ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit How to Read:

0482E—08/09/07 Byte 0: Control Register Byte 1: Control Register tiB# niPe maND WP 2 epyT 1 noitpircseD 0tiB4 50 SFX R nodelpmasnip0SFfoeulavehtstcelfeR purewop 1tiB5 51 SFX R nodelpmasnip1SFfoeulavehtstcelfeR purewop 2tiB0 42 SFX R nodelpmasnip2SFfoeulavehtstcelfeR purewop 3tiB4 3# POTS_ICP 3 XR foeulavehtstcelfeR:edomerawdraH DWPnodelpmasnip#POTS_ICP 1W R :edomerawtfoS deppotsKLCICP=0 deppotstonKLCICP=1 4tiB3 5# POTS_UPCX R lanretxeehtfoeulavtnerrucehtstcelfeR nip#POTS_UPC 5tiB5 3H CV/1_66V30 W R zHM84/zHM66tceleSHCV zHM84=1,zHM66=0 6tiB- ) 0:2(T_UPC0 leveltuptuoslortnocedomnwodrewopnI hgihpots=0 wolpots=1 7tiB- daerpS delbanE 0W Rn OdaerpS=1,ffOdaerpS=0 Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP functionality via I 2C Byte 0 Bit 3. In Hardware mode it is not allowed to write to the I 2C Byte 0 Bit3. In Software mode it is not allowed to pull the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONL Y , it is not allowed to mix these modes. In Hardware mode the I 2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in PCI_STOP mode. Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I 2C Byte 0 Bit 3 = 0)]. 4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low. tiB# niPe maND WP 2 epyT 1 noitpircseD 0tiB1 5,25 0TKLCUPC 0CKLCUPC 1W Rd elbanE=1delbasiD=0 4 1tiB8 4,94 1TKLCUPC 1CKLCUPC 1W Rd elbanE=1delbasiD=0 4 2tiB4 4,54 2TKLCUPC 2CKLCUPC 1W Rd elbanE=1delbasiD=0 4 3tiB1 5,25 0TKLCUPC 0CKLCUPC 0W R noitressahtiw0C/0TKLCUPCfolortnocwollA eerF=1gninnureerftoN=0#POTS_UPCfo gninnur 4tiB8 4,94 1TKLCUPC 1CKLCUPC 0W R noitressahtiw1C/1TKLCUPCfolortnocwollA eerF=1gninnureerftoN=0#POTS_UPCfo gninnur 5tiB4 4,54 2TKLCUPC 2CKLCUPC 0W R noitressahtiw2C/2TKLCUPCfolortnocwollA eerF=1gninnureerftoN=0#POTS_UPCfo gninnur 6tiB- - 0 - ) devreseR( 7tiB3 40 LESTLUMX R 0 LESTLUMfoeulavtnerrucehtstcelfeR

0482E—08/09/07 Byte 2: Control Register Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default tiB# niPe maND WPe pyTn oitpircseD 0tiB0 10 KLCICP1 W Rd elbanE=1delbasiD=0 1tiB1 11 KLCICP1 W Rd elbanE=1delbasiD=0 2tiB2 12 KLCICP1 W Rd elbanE=1delbasiD=0 3tiB3 13 KLCICP1 W Rd elbanE=1delbasiD=0 4tiB6 14 KLCICP1 W Rd elbanE=1delbasiD=0 5tiB7 15 KLCICP1 W Rd elbanE=1delbasiD=0 6tiB8 16 KLCICP1 W Rd elbanE=1delbasiD=0 7tiB- - 0 - ) devreseR( Byte 3: Control Register Byte 4: Control Register tiB# niPe maND WPe pyTn oitpircseD 0tiB1 22 -66V31 W Rd elbanE=1delbasiD=0 1tiB2 23 -66V31 W Rd elbanE=1delbasiD=0 2tiB3 24 -66V31 W Rd elbanE=1delbasiD=0 3tiB4 25 _66V31 W Rd elbanE=1delbasiD=0 4tiB5 3K LC_HCV/1_66V31 W Rd elbanE=1delbasiD=0 5tiB3 30 _66V31 W Rd elbanE=1delbasiD=0 6tiB- - 0 R ) devreseR( 7tiB- - 0 R ) devreseR( tiB# niPe maND WPe pyTn oitpircseD 0tiB5 0 F_KLCICP1 W Rd elbanE=1delbasiD=0 1tiB6 1 F_KLCICP1 W Rd elbanE=1delbasiD=0 2tiB7 2 F_KLCICP1 W Rd elbanE=1delbasiD=0 3tiB5 0 F_KLCICP0 W R fonoitressahtiw0F_KLCICPfolortnocwollA eerftoN=1,gninnuReerF=0.#POTS_ICP gninnur 4tiB6 1 F_KLCICP0 W R fonoitressahtiw1F_KLCICPfolortnocwollA eerftoN=1,gninnuReerF=0.#POTS_ICP gninnur 5tiB7 2 F_KLCICP0 W R fonoitressahtiw2F_KLCICPfolortnocwollA eerftoN=1,gninnuReerF=0.#POTS_ICP gninnur 6tiB9 3B SU_zHM841 W Rd elbanE=1delbasiD=0 7tiB8 3T OD_zHM841 W Rd elbanE=1delbasiD=0

0482E—08/09/07 Byte 6: Vendor ID Register (1 = enable, 0 = disable) tiB# niPe maND WPe pyTn oitpircseD 0tiBX 0 tiBDIrodneV1 R ) devreseR( 1tiBX 1 tiBDIrodneV1 R ) devreseR( 2tiBX 2 tiBDIrodneV1 R ) devreseR( 3tiBX 3 tiBDIrodneV1 R ) devreseR( 4tiBX 0 tiBDInoisiveR1 R nodesabeblliwseulavDInoisiveR noisivers'ecivedlaudividni5tiBX 1 tiBDInoisiveR1 R 6tiBX 2 tiBDInoisiveR1 R 7tiBX 3 tiBDInoisiveR1 R Byte 5: Programming Edge Rate (1 = enable, 0 = disable) Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default tiB# niPe maND WPe pyTn oitpircseD 0tiBX B SU_zHM840 W Rl ortncetaregdeBSU 1tiBX B SU_zHM840 W Rl ortncetaregdeBSU 2tiBX T OD_zHM840 W Rl ortnocetaregdeTOD 3tiBX T OD_zHM840 W Rl ortnocetaregdeTOD 4tiBX - 0 - ) devreseR( 5tiBX - 0 - ) devreseR( 6tiBX - 0 - ) devreseR( 7tiBX - 0 - ) devreseR(

0482E—08/09/07 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2V DD + 0.3 V Input Low Voltage V IL VSS - 0.3 0.8 V Input High Current I IH VIN = VDD -5 5 mA IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 mA IIL2 VIN = 0 V; Inputs with pull-up resistors -200 mA Operating Supply Current IDD3.3OP CL = Full load; Select @ 100 MHz 229 230 360 mA IDD3.3OP CL =Full load; Select @ 133 MHz 220 233 360 mA Powerdown Current I DD3.3PD IREF=5 mA 38.1 45 mA Input Frequency F i VDD = 3.3 V 14.318 MHz Pin Inductance L pin 7n H CIN Logic Inputs 5 pF COUT Output pin capacitance 6 pF CINX X1 & X2 pins 27 36 45 pF Transition time1 Ttrans To 1st crossing of target frequency 3 ms Settling time1 Ts From 1st crossing to 1% target frequency 3 ms Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target frequency 1 3 ms Time to first clock 1 T1C Time to first clock 1.8 ms tPZH,tPZL Output enable delay (all outputs) 1 10 ns tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns 1Guaranteed by design, not 100% tested in production. Delay1 Input Capacitance1 Input Low Current

0482E—08/09/07 Electrical Characteristics - CPU TA = 0 - 70°C; VDD=3.3V +/-5%; C L = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current Source Output Impedance Zo 1 VO = Vx 3000 Ω Output High Voltage V OH3 IOH = -1 mA 2.4 V Output Low Voltage V OL3 IOL = 1 mA 0.4 Rise Time t r3 VOL = 0.41V, V OH = 0.86V 175 240 700 ps Fall Time t f3 VOH = 0.86V VOL = 0.41V 175 242 700 ps Duty Cycle d t3 measurement from differential wavefrom - 0.35V to +035V 45 51 55 % Skew t sk3 VT = 50% 50 100 ps Jitter, Cycle to cycle tjcyc-cyc

1 VT = 50% 76 150 ps

1Guaranteed by design, not 100% tested in production.

2 IOWT

can be varied and is selectable thru the MULTSEL pin. Electrical Characteristics - PCICLK TA = 0 - 70C; VDD=3.3V +/-5%; C L = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 33.33 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 12 33 55 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.55 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, V OL @MAX = 0.4 V 30 38 mA Rise Time t r1 Fall Time t f1 Duty Cycle d t1 1 VT = 1.5 V 45 52 55 % Skew t sk1 1 VT = 1.5 V 247 500 ps Jitter,cycle to cyc tjcyc-cyc 1 VT = 1.5 V 111 500 ps 1Guaranteed by design, not 100% tested in production.

0482E—08/09/07 Electrical Characteristics - 3V66 TA = 0 - 70°C; VDD=3.3V +/-5%; C L = 10-30 pF (unless otherwise specified) PARAMETER SYMBO L CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 66.66 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 12 33 55 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.55 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 -33 -33 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, V OL @MAX = 0.4 V 30 38 mA Rise Time t r1 1 VOL = 0.4 V, V OH = 2.4 V 0.5 1.38 2 ns Fall Time t f1 1 VOH = 2.4 V, V OL = 0.4 V 0.5 1.45 2 ns Duty Cycle d t1 1 VT = 1.5 V 45 54.4 55 % Skew t sk1 1 VT = 1.5 V 243 500 ps Jitter tjcyc-cyc 1 VT = 1.5 V 3V66 139 300 ps 1Guaranteed by design, not 100% tested in production. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB TA = 0 - 70°C; VDD=3.3V +/-5%; C L = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 48 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 20 48 60 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.4 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, V OL @MAX = 0.4 V 29 27 mA 48DOT Rise Time tr1 1 VOL = 0.4 V, V OH = 2.4 V 0.5 0.6 1 ns 48DOT Fall Time tf1 1 VOH = 2.4 V, V OL = 0.4 V 0.5 0.8 1 ns VCH 48 USB Rise Time t r1 1 VOL = 0.4 V, V OH = 2.4 V 1 1.2 2 ns VCH 48 USB Fall Time t f1 1 VOH = 2.4 V, V OL = 0.4 V 1 1.3 2 ns

48 DOT Duty Cycle d t1

1 VT = 1.5 V 45 52.8 55 % VCH 48 USB Duty Cycle d t1 1 VT = 1.5 V 45 53.5 55 %

48 DOT Jitter t jcyc-cyc

1 VT = 1.5 V 183 350 ps VCH Jitter tjcyc-cyc 1 VT = 1.5 V 223 350 ps 1Guaranteed by design, not 100% tested in production.

0482E—08/09/07 Electrical Characteristics - REF TA = 0 - 70°C; VDD=3.3V +/-5%; C L = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency F O1 14.318 MHz Output Impedance R DSP1 1 VO = VDD*(0.5) 20 48 60 Ω Output High Voltage V OH 1 IOH = -1 mA 2.4 V Output Low Voltage V OL 1 IOL = 1 mA 0.4 V Output High Current IOH 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA Output Low Current IOL 1 VOL @MIN = 1.95 V, V OL @MAX = 0.4 V 29 27 mA Rise Time t r1 1 VOL = 0.4 V, V OH = 2.4 V 1 1.25 2 ns Fall Time t f1 1 VOH = 2.4 V, V OL = 0.4 V 1 1.15 2 ns Duty Cycle d t1 1 VT = 1 . 5 V 4 55 35 5 % Jitter tjcyc-cyc 1 VT = 1.5 V 723 1000 ps 1Guaranteed by design, not 100% tested in production.

0482E—08/09/07 All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. Un-Buffered Mode 3V66 & PCI Phase Relationship 3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci Group Skews at Common Transition Edges: (Un-Buffered Mode) GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS 3V66 3V66 3V66 (5:0) pin to pin skew 0 42 500 ps PCI PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 0 130 500 ps 3V66 to PCI S 3V66-PCI 3V66 (5:0) leads 33MHz PCI 1.5 2.86 3.5 ns 1Guaranteed by design, not 100% tested in production.

0482E—08/09/07 Normal operation transition to Suspend State S1 Entry sequence of events: 1. Power-Down (PD#) pin is taken from a high to low to start into S1 Suspend state with digital filtering of the transition in the clock circuit. 2. The first clocks to be forced to a Stop Low power down condition are the PCI buffer output clocks after a full clock cycle. If the PCI_Stop# is low, then the free-running PCI clocks (for PCI and APIC signals) are the remaining PCI buffer clocks stopped. 3. Immediately after the PCI clocks have been stopped the 66Buf_0:2 clocks are stopped low after the next high to low transition. It will always be a sequence of PCI stopping, THEN the 66Buf clocks. 4. Following the two buffer output clocks being stopped (PCI then 66.6Buffer outputs), the remaining clocks within a short delay will transition to a stopped power-down state. The first of these driven clocks that transition to a stopped state are all of the CPU PLL clocks: the CPU and the driven 3V66 clocks. 5. After the CPU PLL clocks are stopped, the 48 MHz clocks (USB, DOT clocks) will stop low, then the REF clock 14.318 MHz clock will stop low. 6. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to a low power stopped condition. 7. As a note to power management calculations, please be aware that the CPU design requires that in the Power-Down (S1 mode) the CPU outputs have a differential bias voltage driving the differential input stage of the CPU in this S1 state. For this PD condition of the clock generator, the IDD_PD is running around 30 to 45 mA from having the Iref running (5 mA), the output multiplier bias generator at a 2X condition and the output current source outputs are running at a 2xIref bias level (for approx 10 mA each CPU output). This results in a higher level of Clock generator IDD_PD than in prior generations of clocks due to the CPU output differential requirements. Suspend State S1 Exit transition to normal operation sequence of events: 1. Power-Down (PD#) pin is taken from Low to High with digital filtering of the transition in the clock circuit to return to normal running operation. 2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation. No clocks will operate until the Lock detect circuitry verifies the PLL has reached stable final frequency (the same as normal initial power-up). 3. The CPU PLL clocks (differential CPU outputs and the driven 3V66_(0:1) clocks are operating first as soon as the Lock detect releases the clocks. With the release of these clocks, the single 66Buf_1 buffer driven output (at pin 22) is also released from the PD stopped state (but NOT the other 66Buf0,2 and not the PCI outputs). This allows the GMCH chipset 66.6 MHz DLL stage to start operating and have an operating feedback path before the other buffer outputs are released. This change is why the requirement is made that pin 22 be the connection from the clock to the GMCH chipset. Note that along with the 66Buf_0,2 and the PCI clocks, the 48 MHz and REF (14.318 MHz) clocks are also NOT released at this point. 4. A delay is built into the clock generator that allows the CPU, driven 3V66_0,1 and the single buffer clock 66Buf_1 (at pin 22) to operate before other clocks are released. This delay is larger than 30 uS and shorter than 400 uS, and after this the other clocks are staged for a sequential release. 5. The initial clocks released after the delay are the 66Buf_0, 2 outputs. 6. After the 66Buf_0,2 clocks are released, then the PCI clocks are released. 7. It will always be the sequence of 66_1 (pin 22) released with the CPU clocks, then after the delay the remaining 66Buf_0,2 first, THEN the PCI clocks. 8. Following the 66Buf_0,2 clocks, the 48 MHz (DOT and USB clocks) and the REF (14.318MHz) clocks are released. 9. Note, the initial power-up time is the same as this PD release, the PLL will power-up and the outputs will be running within a 3 ms time point.

0482E—08/09/07 Assertion of PCI_STOP# Waveforms PCI_STOP# - Assertion (transition from logic "1" to logic "0") CPU_STOP# CPUT CPUC CPU_STOP# - Assertion (transition from logic "1" to logic "0") Assertion of CPU_STOP# Waveforms CPU_STOP# Functionality #POTS_UPCT UPCC UPC 1l amroNl amroN 0t luM*ferit aolF PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz tsu The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I 2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.

0482E—08/09/07 When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200MHz. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# - Assertion (transition from logic "1" to logic "0") PD# Functionality #POTS_UPCT UPCC UPC6 6V3T UO_zHM66 F_KLCICP KLCICP KLCICP TOD/BSU zHM84 1l amroNl amroNz HM66N I_zHM66N I_zHM66N I_zHM66z HM84 0t luM*ferit aolFw oLw oLw oLw oLw oL Power Down Assertion of Waveforms - Buffered Mode 0ns PD# CPUT 100MHz CPUC 100MHz 3V66MHz 66MHz_IN 66MHz_OUT PCI 33MHz USB 48MHz REF 14.318MHz 25ns 50ns

0482E—08/09/07

Ordering Information

Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Example: XXXX y G - LF - T INDEX AREA INDEX AREA 121 2 N D E1 E /c97 SEATING PLANE SEATING PLANE AA2 e -C-- C - b c L aaa C 6.10 mm. Body, 0.50 mm. pitch TSSOP (240 mil) (0.020 mil) MIN MAX MIN MAX A- - 1 . 2 0 - - . 0 4 7 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D E E1 6.00 6.20 .236 .244 e L 0.45 0.75 .018 .030 N α 0° 8° 0° 8° MIN MAX MIN MAX 56 13.90 14.10 .547 .555 1 0-0039 VARIATIONS N D mm. D (inch) Reference Doc.: JEDEC Publication 95, M O-1 53 0.50 BASIC 0. 020 BASIC SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0. 319 BASIC SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS

0482E—08/09/07 Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Example: XXXX y F - LF - T M I NM A XM I NM A X A 2.41 2.80 .095 .110 A1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 D E 10.03 10.68 .395 .420 E1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 L 0.50 1.02 .020 .040 N α 0° 8° 0° 8° VARIATIONS M I NM A XM I NM A X 56 18.31 18.55 .720 .730 10-0034 0.635 BASIC 0.025 BASIC COMMON DIMENSIONS In Millimeters In Inches COMMON DIMENSIONS Reference Doc.: JEDEC Publication 95, MO-118 56-Lead, 300 mil Body, 25 mil, SSOP N SEE VARIATIONS SEE VARIATIONS D mm. D (inch) SYMBOL SEE VARIATIONS SEE VARIATIONS

0482E—08/09/07

Revision History

Rev. Issue Date Description Page # D 12/21/06 1. Removed SSOP Package Information. 2. Added LF Ordering Information. 16 E 08/09/07 Added SSOP Package Information. 17

Product Information

950811YFLFT specifications and overview.

Summary

Frequency Generator with 200MHz Differential CPU Clocks 08/09/07

Description

Frequency Generator with 200MHz Differential CPU Clocks 08/09/07

Source title 950811YFLFT Datasheet(PDF) - Renesas Technology Corp

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