9403A FAIRCHILD | Alldatasheet
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Technical content
Features
■ Serial or parallel input ■ Serial or parallel output ■ Expandable without external logic ■ 3-STATE outputs ■ Fully compatible with all TTL families ■ Slim 24-pin package Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Order Number Package Number Package Description 9403APC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.400 Wide
www.fairchildsemi.com 2 9403A Unit Loading/Fan Out Block Diagram Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH /IOL D 0–D 8 Parallel Data Inputs 2.0/0.667 40 µA/400 µA D S Serial Data Input 2.0/0.667 40 µA/400 µA PL Parallel Load Input 2.0/0.667 40 µA/400 µA CPSI Serial Input Clock 2.0/0.667 40 µA/400 µA IES Serial Input Enable 2.0/0.667 40 µA/400 µA TTS Transfer to Stack Input 2.0/0.667 40 µA/400 µA OES Serial Output Enable 2.0/0.667 40 µA/400 µA TOS Transfer Out Serial 2.0/0.667 40 µA/400 µA TOP Transfer Out Parallel 2.0/0.667 40 µA/400 µA MR Master Reset 2.0/0.667 40 µA/400 µA OE Output Enable 2.0/0.667 40 µA/400 µA CPSO Serial Output Clock 2.0/0.667 40 µA/400 µA Q 0 - Q3 Parallel Data Outputs 285/26.7 5.7 mA/16 mA Q S Serial Data Output 285/26.7 5.7 mA/16 mA IRF Input Register Full 20/13.3 −400 µA/8 mA ORE Output Register Empty 20/13.3 −400 µA/8 mA
only when it is necessary to wait for an empty next location. logic diagram of the output section. FIGURE 3. Conceptual Output Section data outputs (provided the 3-STATE buffer is enabled). indicating that there is no valid data at the outputs. LOW and disables the serial output, QS (refer to Figure 3). previous one has been shifted out.
FIGURE 4. A Vertical Expansion Scheme form a 16-word by 12-bit FIFO are shown in Figure 5. 9403A’s flexibility for serial/parallel input and output.
- The final position of data after serial insertion of 496 bits
into the FIFO array of Figure 6 is shown in Figure 9. from a row master or a slave of higher priority. all devices, the IRF outputs of all devices will be HIGH. A similar operation takes place for the output register. put will be LOW until an OES input is received.
9 www.fairchildsemi.com 9403A Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +175°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.5 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.4 V Min I OH = −400 µA (IRF, ORE) Voltage 10% V CC 2.4 I OH = −5.7 mA (Qn, Qs) VOL Output LOW 10% V CC 0.5 V Min I OL = 8 mA (IRF, ORE) Voltage 10% V CC 0.5 I OL = 16 Ma (Qn, Qs) IIH Input HIGH Current 40 µAM a x V IN = 2.7V IBVI Input HIGH Current Breakdown Test 100 µAM a x V IN = 7.0V IIL Input LOW Current −0.45 mA Max V IN = 0.4V IOZH Output Leakage Current 100 µAM a x V OUT = 2.4V IOZL Output Leakage Current −100 µAM a x V OUT = 0.5V IOS Output Short-Circuit Current −30 −130 mA Max V OUT = 0V ICEX Output HIGH Leakage Current 250 µAM a x V OUT = VCC ICC Power Supply Current 170 mA Max V O = LOW
11 www.fairchildsemi.com 9403A Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V Figure C L = 50 pF C L = 50 pF Number Min Max Min Max tPLH Propagation Delay, 1.5 39.5 1.5 41.0 nsPositive-Going OES to ORE tPLH Propagation Delay, 1.5 20.0 1.5 21.0 ns Figure 18Positive-Going IES to Positive-Going IRF tPLH Propagation Delay, 1.5 20.0 1.5 20.0 ns MR to IRF tPHL Propagation Delay, 1.5 33.0 1.5 35.0 ns MR to ORE tPZH Propagation Delay, 1.5 14.0 1.5 14.0 ns tPZL OE to Q0, Q1, Q2, Q3 1.5 14.0 1.5 14.0 tPHZ Propagation Delay, 1.5 14.0 1.5 14.0 tPLZ OE to Q0, Q1, Q2, Q3 1.5 14.0 1.5 14.0 tPZH Propagation Delay, 1.5 16.5 1.5 17.0 ns tPZL Negative-Going 1.5 17.0 1.5 17.0 OES to QS tPHZ Propagation Delay, 1.5 14.0 1.5 14.0 tPLZ Negative-Going 1.5 14.0 1.5 14.0 OES to QS tPZH Turn On Time 1.5 60.0 1.5 60.0 ns tPZL TOS to QS 1.5 60.0 1.5 60.0 tDFT Fall Through Time 500 500 ns Figure 16 tAP Parallel Appearance Time, −19.0 6.5 −20.0 7.0 ns ORE to Q0-Q3 tAS Serial Appearance Time, −9.5 14.5 −10.0 15.0 ORE to QS tDBU Bubble-Up Time 470 500 ns
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 9403A First-In First-Out (FIFO) Buffer Memory LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.400 Wide Package Number N24E