93S46

93S46 FAIRCHILD | Alldatasheet

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93846 010° HIGH SPEED 6-BIT IDENTITY COMPARATOR DESCRIPTION — The '46 is a very high speed 6-bit identity comparator. The device compares two words of up to six bits and indicates identity in less than 12ns. It is easily expandable to any word length by using either serial or para- aol a vec Hel expansion techniques. When the Enable input (E) is LOW, it forces the ° output LOW. Bo [2] [Je re [ray as © COMPARES TWO 6-BIT WORDS IN 12 ns og fia}. © EASILY EXPANDABLE TO ANY WORD SIZE wo aac © ACTIVE HIGH ENABLE FOR FAST RIPPLE EXPANSION B2[6] [17] 83 e [ia] a> ORDERING CODE: See Section 9 np [a] [9]A=8 pin [COMMERCIAL GRADE] MILITARY GRADE | p,q PKGS Veco = +5.0 V +5%, Vec = +5.0 V +10%, OUT) Te=0°C to +70°C | Ta =-85°C to +125°C | TYPE Plastic Ceramic DIP (D) 9984600 esesom | ow | INPUT LOADING/FAN-OUT: See Section 3 for ULL. definitions 938 (UL) PIN NAMES DESCRIPTION HIGH/LOW Ao —As Word A inputs 4.25/1.25 Bo —Bs Word B Inputs 4.25/1.25 i= Enable Input (Active HIGH) 1.25/1.25 A=B A Equal to 8 Output 25/12.5 LoGic SYMBOL 12 3 4 5 6 10 11 12 13 14 15 ‘Ao Bo Ar By Az Bz A3 B3 As Ba As Bs 7 e Ans Vec = Pin 16 GND = Pin 8 6-106

FUNCTIONAL DESCRIPTION — The ‘46 is a very high speed 6-bit identity comparator. The A=B. output is HIGH when the Enable (E) is HIGH and the two 6-bit words are equal. Equality is determined by Exclusive-NOR circuits which individually compare the equivalent bits from each word. When any two of the equivalent bits from each word have different logic levels, the A = B output is LOW. (A= B) = (Ao © Bo) e (Ar @ Bi) (Ag @ Bz) © (Ag © Ba) © (Ay © Ba) 0 (Ag © Bs) e E An active HIGH Enable (E) provides a means of fast ripple expansion. By connecting the A= Boutput of the first stage of the comparator to the enable of the next stage, the comparator can be expanded in 6-bit increments at an additional 4.5 ns per stage. An even faster expansion technique is achieved by connecting the A=B outputs toa Schottky NAND gate. This method compares two words of up to 78 bits each in 1 ns (typical) using the'133 13-input Schottky NAND gate. TRUTH TABLE INPUTS OUTPUT L | An=Bn L L | An# Bn L H | An# Bn L H | An= Bn H L = LOW Voltage Level RIPPLE EXPANSION AoBo seeeeeeeeens ABs AcBS see ee eee eee ABI Ai2Bi2 eee ee eee ANyBy ‘Ao Bo Ay By Az B2 As By As Be As Bs ‘Ao Bo Ai By A2B2 As Bs As Bs As Bs ‘Ao Bo Ar By A2B2 AyBs Ac Bs As Bs e—e 93846 E 93846 e 93846 A-8 A=8 A=8 (A=B)0E NOTE: This simple method of expansion adds 4.5 ns for each additional '46 used. PARALLEL EXPANSION AoBo tee eeeeeeeee AsBs AGB te eee eee eee ANB ArDBi2 eee cece eee ee Air Bir ‘Ao Bo Ar By A2B2 ASBs Ac Bs ASBs ‘Ao Bo Ar Bi Az B2 Ag By AcBy As Bs ‘Ao Bo Ar By A2B2 Aa B5 Ac Ba AsBs E-PqE 93846 € 93846 € 93846 l A=8 | A=8 i A=8 SCHOTTKY NAND GATE renrr NOTE: This method of expansion adds one gate delay (=3 ns! to the '46, independent of the word length that is compared. 6-107

Ao Bo AY By A2Be As By As Ba As Bs e ane DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) smmnot ; owwem be | conpmons AC CHARACTERISTICS: Voc = +5.0 V, Ta = +25°C (See Section 3 for waveforms and load configurations) SYMBOL PARAMETER CONDITIONS tel Propagation Delay 3.0 17 E= 4.5 V, Other Inputs Neel nee tO AaB 30 0 = 45 V, Test each input individually, Figs. 3-1, 3-5 tPuH Propagation Delay 30 14 E = 4.5 V, Other Inputs te An or Ba toA=B 30 15 = Gnd, Test each input HL individually, Figs. 3-1, 3-4 teu Propagation Delay 20 10 An = Bn tea EtoA=B 20 10 Figs. 3-1, 3-5 6-108