93LC46A-E/MSG

93AA46A MICROCHIP | Alldatasheet

Document overview

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Technical content

Features

• Low-power CMOS technology  ORG pin to select word size for ‘46C version  128 x 8-bit organization ‘A’ ver. devices (no ORG)  64 x 16-bit organization ‘B’ ver. devices (no ORG)  Self-timed ERASE/WRITE cycles (including auto-erase)  Automatic ERAL before WRAL  Power-on/off data protection circuitry  Industry standard 3-wire serial I/O  Device Status signal (READY/BUSY  Sequential READ function  1,000,000 E/W cycles  Data retention > 200 years  Temperature ranges supported Pin Function Table

Description

The Microchip Technology Inc. 93XX46A/B/C devices are 1K bit low voltage serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as the 93AA46C, 93LC46C or 93C46C are dependent upon external logic levels driving the ORG pin to set word size. For dedicated 8-bit communication, the 93AA46A, 93LC46A or 93C46A devices are available, while the 93AA46B, 93LC46B and 93C46B devices provide dedicated 16-bit communication. Advanced CMOS technology makes these devices ideal for low power, nonvolatile memory applications. The entire 93XX Series is available in standard packages includ- ing 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP , 6-lead SOT-23, and 8-lead TSSOP . Pb-free (Pure Matte Sn) finish is also available. Package Types (not to scale) Part Number V CC Range ORG Pin Word Size Temp Ranges Packages 93AA46A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT 93AA46B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT 93LC46A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT 93LC46B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT 93C46A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT 93C46B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT 93AA46C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST, MS 93LC46C 2.5-5.5 Yes 8 or 16-bit I, E P , SN, ST, MS 93C46C 4.5-5.5 Yes 8 or 16-bit I, E P , SN, ST, MS - Industrial (I) -40°C to +85°C - Automotive (E) -40°C to +125°C Name Function CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output VSS Ground NC No internal connection ORG Memory Configuration VCC Power Supply CS CLK DI DO VCC NC ORG* VSS PDIP/SOIC (P, SN) CS CLK DI DO V CC NC ORG* VSS ROTATED SOIC (ex: 93LC46BX) TSSOP/MSOP CS CLK DI DO VCC NC ORG* VSS (ST, MS) SOT-23 DO VSS DI VCC CS CLK (OT) * ORG pin is NC on A/B devices 1K Microwire Compatible Serial EEPROM

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 2  2003 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†) TABLE 1-1: DC CHARACTERISTICS † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All parameters apply over the specified ranges unless otherwise noted. V CC = range by device (see Table on Page 1) Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Param. No. Symbol Parameter Min Typ Max Units Conditions D1 V IH1 VIH2 High-level input voltage 2.0

0.7 VCC

V CC +1 VCC +1 V V VCC ≥ 2.7V VCC < 2.7V D2 V IL1 VIL2 Low-level input voltage -0.3 -0.3 0.8

0.2 VCC

V V V CC ≥ 2.7V VCC < 2.7V D3 V OL 1 VOL 2 Low-level output voltage — 0.4 0.2 V V IOL = 2.1 mA, VCC = 4.5V IOL = 100 µA, VCC = 2.5V D4 V OH 1 VOH 2 High-level output voltage 2.4 VCC - 0.2 V V IOH = -400 µA, VCC = 4.5V IOH = -100 µA, VCC = 2.5V D5 I LI Input leakage current — — ±1 µAV IN = VSS to VCC D6 I LO Output leakage current — — ±1 µAV OUT = VSS to VCC D7 C IN, C OUT Pin capacitance (all inputs/outputs) ——7p F V IN/VOUT = 0V (Note 1) TA = 25°C, FCLK = 1 MHz D8 I CC write Write current — 500 mA µA FCLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 2.5V D9 I CC read Read current — 100 500 mA µA µA F CLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 3.0V FCLK = 2 MHz, VCC = 2.5V D10 I CCS Standby current — µA µA I-Temp E-Temp CLK = CS = 0V ORG = DI = V SS or VCC (Note 2) (NOTE 3) D11 V POR VCC voltage detect 93AA46A/B/C, 93LC46A/B/C 93C46A/B/C 1.5V 3.8V V V (Note 1) Note 1: This parameter is periodically sampled and not 100% tested. 2: ORG pin not available on ‘A’ or ‘B’ versions. 3: READY/BUSY status must be cleared from DO, see Section 3.4 "Data Out (DO)".

 2003 Microchip Technology Inc. DS21749D-page 3 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C TABLE 1-2: AC CHARACTERISTICS All parameters apply over the specified ranges unless otherwise noted. VCC = range by device (see Table on Page 1) Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Param. No. Symbol Parameter Min Max Units Conditions A1 F CLK Clock frequency — 3 MHz MHz MHz 4.5V ≤ VCC < 5.5V, 93XX46C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V A2 T CKH Clock high time 200 250 450 —n s ns ns 4.5V ≤ VCC < 5.5V, 93XX46C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V A3 T CKL Clock low time 100 200 450 —n s ns ns 4.5V ≤ VCC < 5.5V, 93XX46C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V A4 T CSS Chip Select setup time 50 100 250 —n s ns ns 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V A5 T CSH Chip Select hold time 0 — ns 1.8V ≤ VCC < 5.5V A6 T CSL Chip Select low time 250 — ns 1.8V ≤ VCC < 5.5V A7 T DIS Data input setup time 50 100 250 —n s 4 . 5 V ≤ VCC < 5.5V, 93XX46C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V A8 T DIH Data input hold time 50 100 250 —n s 4 . 5 V ≤ VCC < 5.5V, 93XX46C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V A9 T PD Data output delay time — 200 250 400 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 2.5V ≤ VCC < 4.5V, CL = 100 pF 1.8V ≤ VCC < 2.5V, CL = 100 pF A10 T CZ Data output disable time — 100 200 ns 4.5V ≤ VCC < 5.5V, (Note 1) 1.8V ≤ VCC < 4.5V, (Note 1) A11 T SV Status valid time — 200 300 500 ns 4.5V ≤ V CC < 5.5V, CL = 100 pF 2.5V ≤ VCC < 4.5V, CL = 100 pF 1.8V ≤ VCC < 2.5V, CL = 100 pF A12 T WC Program cycle time — 6 ms Erase/Write mode (AA and LC versions) A13 T WC — 2 ms Erase/Write mode (93C versions) A14 T EC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V A15 T WL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V A16 — Endurance 1M — cycles 25°C, V CC = 5.0V, (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. 2: This application is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which may be obtained from www.microchip.com.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 4  2003 Microchip Technology Inc. FIGURE 1-1: SYNCHRONOUS DATA TIMING TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1) TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 1 1 A 5A 4A 3A 2A 1A 0 — ( R D Y / B S Y )9 ERAL 1 00 1 0 X X X X — (RDY/BSY )9 EWDS 1 00 0 0 X X X X — HIGH-Z 9 EWEN 1 00 1 1 X X X X — HIGH-Z 9 READ 1 1 0 A 5A 4A 3A 2A 1A 0 — D 1 5 - D 0 2 5 WRITE 1 0 1 A 5A 4A 3A 2A 1A 0 D 1 5 - D 0 ( R D Y / B S Y )2 5 WRAL 1 00 0 1 X X X X D15 - D0 (RDY/BSY )2 5 Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 1 1 A 6A 5A 4A 3A 2A 1A 0 — ( R D Y / B S Y )1 0 ERAL 1 0 0 10XXXXX — ( R D Y / B S Y )1 0 EWDS 1 0 0 00XXXXX — H I G H - Z 1 0 EWEN 1 0 0 11XXXXX — H I G H - Z 1 0 READ 1 1 0 A 6A 5A 4A 3A 2A 1A 0 — D 7 - D 0 1 8 WRITE 1 0 1 A 6A 5A 4A 3A 2A 1A 0 D 7 - D 0 ( R D Y / B S Y )1 8 WRAL 1 00 0 1 X X X X X D7 - D0 (RDY/BSY )1 8 CS VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL CLK DI DO (READ) DO (PROGRAM) TCSS TDIS TCKH TCKL TDIH TPD TCSH TPD TCZ STATUS VALID TSV TCZ Note: TSV is relative to CS.

 2003 Microchip Technology Inc. DS21749D-page 5 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.0 FUNCTIONAL DESCRIPTION

When the ORG* pin is connected to VCC , the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/ BUSY status during a programming operation. The READY/BUSY status can be verified during an Erase/ Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. DO will enter the HIGH-Z state on the falling edge of CS.

2.1 Start Condition

The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a Start condition is detected, CS, CLK, and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, or WRAL). As soon as CS is high, the device is no longer in Standby mode. An instruction following a Start condition will only be executed if the required opcode, address and data bits for any particular instruction are clocked in.

2.2 Data In/Data Out (DI/DO)

It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO.

2.3 Data Protection

All modes of operation are inhibited when VCC is below a typical voltage of 1.5V for '93AA' and '93LC' devices or 3.8V for '93C' devices. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. Note: For added protection, an EWDS command should be performed after every write operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before the initial ERASE or WRITE instruction can be executed. Block Diagram Memory Array Data Register Mode Decode Logic Clock Register Address Decoder Address Counter Output Buffer DO DI ORG* CS CLK VCC VSS *ORG input is not available on A/B devices

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 6  2003 Microchip Technology Inc.

2.4 ERASE

The ERASE instruction forces all data bits of the specified address to the logical ‘1’ state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle, except on ‘93C’ devices where the rising edge of CLK before the last address bit initiates the write cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL ). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been erased and the device is ready for another instruction. Note: Issuing a Start bit and then taking CS low will clear the READY/BUSY status from DO. FIGURE 2-1: ERASE TIMING FOR 93AA AND 93LC DEVICES FIGURE 2-2: ERASE TIMING FOR 93C DEVICES CS CLK DI DO TCSL CHECK STATUS 1 1 1A N AN -1 A N -2  A0 TSV TCZ BUSY READY HIGH-Z TWC HIGH-Z CS CLK DI DO TCSL CHECK STATUS 1 1 1A N AN -1 A N -2  A0 TSV TCZ BUSY READY HIGH-Z TWC HIGH-Z

 2003 Microchip Technology Inc. DS21749D-page 7 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.5 ERASE ALL (ERAL)

The Erase All (ERAL) instruction will erase the entire memory array to the logical ‘1’ state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS, except on ‘93C’ devices where the rising edge of CLK before the last data bit initiates the write cycle. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL ). Note: Issuing a Start bit and then taking CS low will clear the READY/BUSY status from DO. VCC must be ≥ 4.5V for proper operation of ERAL. FIGURE 2-3: ERAL TIMING FOR 93AA AND 93LC DEVICES FIGURE 2-4: ERAL TIMING FOR 93C DEVICES CS CLK DI DO TCSL CHECK STATUS 10 0 1 0X  X TSV TCZ BUSY READY HIGH-Z TEC HIGH-Z VCC must be ≥ 4.5V for proper operation of ERAL. CS CLK DI DO TCSL CHECK STATUS 10 0 1 0X  X TSV TCZ BUSY READY HIGH-Z TEC HIGH-Z

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 8  2003 Microchip Technology Inc.

2.6 ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)

The 93XX46A/B/C powers up in the ERASE/WRITE Disable (EWDS) state. All Programming modes must be preceded by an ERASE/WRITE Enable ( EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or Vcc is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. FIGURE 2-5: EWDS TIMING FIGURE 2-6: EWEN TIMING

2.7 READ

The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (If ORG pin is low or A-Version devices) or 16-bit (If ORG pin is high or B-version devices) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (T PD ). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. FIGURE 2-7: READ TIMING CS CLK DI 10 00 0 X  X TCSL CS CLK DI 00 1 1X TCSL  CS CLK DI DO 11 0 An  A0

 2003 Microchip Technology Inc. DS21749D-page 9 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.8 WRITE

The WRITE instruction is followed by 8 bits (If ORG is low or A-version devices) or 16 bits (If ORG pin is high or B-version devices) of data which are written into the specified address. For 93AA46A/B/C and 93LC46A/B/ C devices, after the last data bit is clocked into DI, the falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93C46A/B/C devices, the self-timed auto-erase and programming cycle is initiated by the rising edge of CLK on the last data bit. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL ). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. Note: Issuing a Start bit and then taking CS low will clear the READY/BUSY status from DO. FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES FIGURE 2-9: WRITE TIMING FOR 93C DEVICES CS CLK DI DO BUSY READY HIGH-Z HIGH-Z Twc TCSL TCZTSV CS CLK DI DO BUSY READY HIGH-Z HIGH-Z Twc TCSL TCZTSV

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 10  2003 Microchip Technology Inc.

2.9 WRITE ALL (WRAL)

The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. For 93AA46A/B/C and 93LC46A/B/C devices, after the last data bit is clocked into DI, the falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93C46A/B/C devices, the self-timed auto- erase and programming cycle is initiated by the rising edge of CLK on the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL ). Note: Issuing a Start bit and then taking CS low will clear the READY/BUSY status from DO. VCC must be ≥ 4.5V for proper operation of WRAL. FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES FIGURE 2-11: WRAL TIMING FOR 93C DEVICES CS CLK DI DO HIGH-Z HIGH-Z BUSY READY TWL VCC must be ≥ 4.5V for proper operation of WRAL. TCSL TSV TCZ CS CLK DI DO HIGH-Z HIGH-Z BUSY READY TWL TCSL TSV TCZ

 2003 Microchip Technology Inc. DS21749D-page 11 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN DESCRIPTIONS

3.1 Chip Select (CS)

A high level selects the device; a low level deselects the device and forces it into Standby mode. However, a programming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (T CSL ) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status.

3.2 Serial Clock (CLK)

The Serial Clock is used to synchronize the communi- cation between a master device and the 93XX series device. Opcodes, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T CKH ) and clock low time (TCKL ). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “Don't Care” if CS is low (device deselected). If CS is high, but the Start condition has not been detected (DI = 0), any number of clock cycles can be received by the device without changing its status (i.e., waiting for a Start condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed. CLK and DI then become don't care inputs waiting for a new Start condition to be detected.

3.3 Data In (DI)

Data In (DI) is used to clock in a Start bit, opcode, address and data synchronously with the CLK input.

3.4 Data Out (DO)

Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status informa- tion during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum Chip Select low time (TCSL ) and an ERASE or WRITE operation has been initiated. The Status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready. Note: Issuing a Start bit and then taking CS low will clear the READY/BUSY status from DO.

3.5 Organization (ORG)

When the ORG pin is connected to VCC or Logic HI, the (x16) memory organization is selected. When the ORG pin is tied to VSS or Logic LO, the (x8) memory organization is selected. For proper operation, ORG must be tied to a valid logic level. 93XX46A devices are always x8 organization and 93XX46B devices are always x16 organization. Name SOIC/PDIP/ MSOP/ TSSOP SOT-23 Rotated SOIC Function CS 1 5 3 Chip Select CLK 2 4 4 Serial Clock DI 3 3 5 Data In DO 4 1 6 Data Out Vss 5 2 7 Ground ORG/NC 6 N/A 8 Organization / 93XX46C No internal connection / 93XX46A/B NC 7 N/A 1 No Internal Connection V CC 8 6 2 Power Supply

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 12  2003 Microchip Technology Inc.

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Part number T Temperature Blank Commercial I Industrial E Extended YY Year code (last 2 digits of calendar year) except TSSOP and MSOP which use only the last 1 digit WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: Custom marking available. Example:6-Lead SOT-23 8-Lead MSOP (150 mil) Example: XXXXXXT YWWNNN 3L46BI 2281L7 XXNN 1EL7 XXXXXNNN XXXXXXXX YYWW 8-Lead PDIP 8-Lead SOIC XXXXYYWW XXXXXXXX NNN XXXX TYWW 8-Lead TSSOP NNN I/SN 1L7 93LC46B 0228 Example: Example: I/SN 0228 93LC46B 1L7 1L7 L46B I228 Example: MSOP 1st Line Marking Codes Device 93AA46A 93AA46B 93AA46C 93LC46A 93LC46B 93LC46C 93C46A 93C46B 93C46C std mark 3A46AT 3A46BT 3A46CT 3L46AT 3L46BT 3L46CT 3C46AT 3C46BT 3C46CT Pb-free mark GA46AT GA46BT GA46CT GL46AT GL46BT GL46CT GC46AT GC46BT GC46CT T = blank for commercial, “I” for Industrial, “E” for Extended. TSSOP 1st Line Marking Codes Device 93AA46A 93AA46B 93AA46C 93LC46A 93LC46B 93LC46C 93C46A 93C46B 93C46C std mark A46A A46B A46C L46A L46B L46C C46A C46B C46C Pb-free mark GAAA GAAB GAAC GLAA GLAB GLAC GCAA GCAB GCAC Temperature grade is marked on line 2. SOT23 Marking Codes Device 93AA46A 93AA46B 93LC46A 93LC46B 93C46A 93C46B I-temp 1BNN 1LNN 1ENN 1PNN 1HNN 1TNN E-temp 1FNN 1RNN 1JNN 1UNN Pb-free topside mark is same; Pb-free noted only on carton label.

 2003 Microchip Technology Inc. DS21749D-page 13 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) D A L c (F) α E p B n 1 φ β Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not .037 REFFFootprint (Reference) exceed .010" (0.254mm) per side. Notes: Drawing No. C04-111 *Controlling Parameter Mold Draft Angle Top Mold Draft Angle Bottom Foot Angle Lead Width Lead Thickness β α c B φ .003 .009 .006 .012 Dimension Limits Overall Height Molded Package Thickness Molded Package Width Overall Length Foot Length Standoff Overall Width Number of Pins Pitch A L D E .016 .024 .118 BSC .118 BSC .000 .030 .193 TYP. .033 MIN p n Units .026 BSC NOM INCHES

0.95 REF

.009 .016 0.08 0.22 0.23 0.40 MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043 .031 .037 .006 0.40 0.00 0.75 MINMAX NOM 1.10 0.80 0.15 0.95 MAX 15°5° - 15°5° - JEDEC Equivalent: MO-187 0° - 8° 5° - 15° 15° - -

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 14  2003 Microchip Technology Inc. 6-Lead Plastic Small Outline Transistor (OT) (SOT-23) 10501050βMold Draft Angle Bottom 10501050αMold Draft Angle Top 10501050φFoot Angle 1.90.075p1Outside lead pitch (basic) 0.95.038pPitch 66nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units D B n E L c β φ α A2A exceed .005" (0.127mm) per side. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not Notes: JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 *Controlling Parameter

 2003 Microchip Technology Inc. DS21749D-page 15 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) B A L p α E eB β c n D Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 88 Pitch p .100 2.54 Base to Seating Plane A1 .015 0.38 Mold Draft Angle Top α 51 01 5 51 01 5 Mold Draft Angle Bottom β 51 01 5 51 01 5 * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed JEDEC Equivalent: MS-001 Drawing No. C04-018 .010” (0.254mm) per side. § Significant Characteristic

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 16  2003 Microchip Technology Inc. 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) Foot Angle φ 048048 1512015120βMold Draft Angle Bottom 1512015120αMold Draft Angle Top 1.27.050pPitch 88nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units D n p B E h Lβ c 45° φ α A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 § Significant Characteristic

 2003 Microchip Technology Inc. DS21749D-page 17 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) 10501050βMold Draft Angle Bottom 10501050αMold Draft Angle Top 1.10.043AOverall Height 0.65.026pPitch 88nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits α A L c β φ D n p B E Foot Angle φ 048048 * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 § Significant Characteristic

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 18  2003 Microchip Technology Inc. APPENDIX A: REVISION HISTORY Revision D Corrections to Section 1.0, Electrical Characteristics. Section 4.1, 6-Lead SOT-23 package to OT.

 2003 Microchip Technology Inc. DS21749D-page 19 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape ® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is:  Latest Microchip Press Releases  Technical Support Section with Frequently Asked Questions  Design Tips  Device Errata  Job Postings  Microchip Consultant Program Member Listing  Links to other useful web sites related to Microchip Products  Conferences for products, Development Systems, technical information and more  Listing of seminars and events SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 20  2003 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response From: Name Company Address City / State / ZIP / Country Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: DS21749D93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document?

 2003 Microchip Technology Inc. DS21749D-page 21 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support Device 93AA46A: 1K 1.8V Microwire Serial EEPROM 93AA46B: 1K 1.8V Microwire Serial EEPROM 93AA46C: 1K 1.8V Microwire Serial EEPROM w/ORG 93LC46A: 1K 2.5V Microwire Serial EEPROM 93LC46B: 1K 2.5V Microwire Serial EEPROM 93LC46C: 1K 2.5V Microwire Serial EEPROM w/ORG 93C46A: 1K 5.0V Microwire Serial EEPROM 93C46B: 1K 5.0V Microwire Serial EEPROM 93C46C: 1K 5.0V Microwire Serial EEPROM w/ORG Pinout: Blank = Standard pinout X = Rotated pinout Tape & Reel: Blank = Standard packaging T = Tape & Reel Temperature Range I = -40°C to +85°C E = -40°C to +125°C Package MS = Plastic MSOP (Micro Small outline, 8-lead) OT = SOT-23, 6-lead (Tape & Reel only) P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (150 mil body), 8-lead ST = TSSOP, 8-lead Lead Finish: Blank = Standard 63% / 37% SnPb G = Pure Matte Sn Examples: a) 93AA46C-I/MS: 1K, 128x8 or 64x16 Serial EEPROM, MSOP package, 1.8V b) 93AA46B-I/MS: 1K, 64x16 Serial EEPROM, MSOP package, 1.8V c) 93AA46AT-I/OT: 1K, 128x8 Serial EEPROM, SOT-23 package, tape and reel, 1.8V d) 93AA46CT-I/MS: 1K, 128x8 or 16x16 Serial EEPROM, MSOP package, tape and reel, 1.8V a) 93LC46A-I/MS: 1K, 128x8 Serial EEPROM, MSOP package, 2.5V b) 93LC46BT-I/OT: 1K, 64x16 Serial EEPROM, SOT-23 package, tape and reel, 2.5V c) 93LC46B-I/MS: 1K, 64x16 Serial EEPROM, MSOP package, 2.5V d) 93LC46BXT-I/SNG: 1K, 64x16 Serial EEPROM, SOIC package, rotated pinout, Industrial temperature, Pb-free finish, 2.5V a) 93C46B-I/MS: 1K, 64x16 Serial EEPROM, MSOP package, 5.0V b) 93C46C-I/MS: 1K, 128x8 or 16x16 Serial EEPROM, MSOP package, 5.0V c) 93C46AT-I/OT: 1K, 128x8 Serial EEPROM, SOT-23 package, tape and reel, 5.0V PART NO. X /XX PackageTemperature Range Device X Lead Finish X Tape & Reel X Pinout Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C DS21749D-page 22  2003 Microchip Technology Inc. NOTES:

 2003 Microchip Technology Inc. DS21749D-page 23 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical com- ponents in life support systems is not authorized except with express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEE LOQ , MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices:  Microchip products meet the specification contained in their particular Microchip Data Sheet.  Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.  There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  Microchip is willing to work with the customer who is concerned about the integrity of their code.  Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEE LOQ ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

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