93L425A

93L425A NSC | Alldatasheet

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& Semiconductor 1024 x 1-Bit Static Random Access Memory General Description Features The 931425A is a 1024-bit read write Random Access ™ New design to replace old 93425/93L425 Memory (RAM), organized 1024 words by one bit. It is de- @ Improved ESD thresholds signed for high speed cache control and buffer storage ap- = Alpha hard without die coat plications. The device includes full on-chip decoding, sepa- __g Commercial address access time rate Data input and non-inverting Data output, as well as an 93L425A 25 ns max Active LOW Chip Select ine. m Features TRI-STATE® output ™ Power dissipation decreases with increasing tempera- ture Connection Diagram 16-Pin DIP _ a, oi 16 Voc AO—T2 15——D As 14 WE Al—T4 13 Ag AB-5 12F- As . Mas iif a7 o-7 10 A6 GND—-48 oR AS ‘TL/D/10004-1 Top View Order Number 93L425ADC or 93L425APC See NS Package Number J16A* or N16E° Optional Processing QR = Burn-in *For most current package information, contact product marketing. Logic Symbol 1 15 “ Pin Names Q . Chip Select (Active LOW) cs D WE 2—40 Address Inputs 3 At we [ WE _| __ Write Enable input (Active LOW) sp [lo | ouwme

6 Ad 93L425A

WW |A7 Voc = Pin 16 GND = Png 12—~JA8

13 Ag 0

TUD/s0004~3 5-26

o Absolute Maximum Ratings Guaranteed Operating Ranges o Above which the useful life may be impaired Supply Voltage (Vc) hd If Military/Aerospace specified devices are required, Commercial 5.0V +5% > Please contact the National Semiconductor Sales Case Temperature (Tc) Office/Distributors for availability and specifications. Commercial O°C to +75°C ‘Storage Temperature —65°C to + 150°C Supply Voltage Range —0.5V to +7.0V Input Voltage (DC) (Note 1) —0.5V to Veg Input Current (DC) —12mAto +5.0mA Voltage Applied to Outputs (Note 2) —0.5V to 5.5V Lead Temperature (Soldering, 10 sec.) 300°C Maximum Junction Temperature (Ty) +175°C Output Current +20mA DC Characteristics over operating temperature ranges (Note 3) Symbol | Parameter | Conaitione | in| typ | Max | unite Vin Input HIGH Voltage Guaranteed Input HIGH Voltage 24 v for All Inputs (Notes 4, 5, & 6) ” Vit Input LOW Voltage Guaranteed Input LOW Voltage v for All Inputs (Notes 4, 5, & 6) in Voo = Max, Viv = 0.4V |_| -180 | -s00 | pa im Input HIGH Curent | voo=Manvw=esv | | so [40 | na Ws Input Breakdown Curent | Vog=MaxVin=Voo | | 4.0 ma Vic Input Diode Clamp Voltage | Voc=Maxliy=—10mA | | -10 | -15 |v lozn Output Current (HIGH Z) Voc = Max, Vour = 2.4V re ee ee lozt Voo=Maxvour=osv [| | 50 | na los Output Current Short Circuit Voc = Max (Note 7) nA to Ground (Note 7) lec Power Supply Current Voc = Max, All Inputs = GND, A Output Open mi 5-27

w . | AC Electrical Characteristics (Note 6) voc = 5.0 +5%, GND = OV, Tc = 0°C to + 75°C a B}__svmbot_ [Parameter | Conaitions [win [| Max | Units READ TIMING a tacs Chip Select Access Time Figures ns tzrcs Chip Selact to HIGH Z za | | 1 | ns taa ‘Address Access Time (Note 8) ee ee WRITE TIMING tw Write Pulse Width to Guarantee hs Writing (Note 9) ‘wso Data Setup Time Prior to Write pos [| ns twp Data Hold Time after Write [ 5s | | os twsa Address Setup Time Prior . to Write (Note 9) Figure 4 § ns twHa Address Hold Time after Write [ s | | os twsos Chip Select Setup Time Prior to Write [ s | | os twHcs Chip Select Hold Time after Write [ 5s | | ns tzws Write Enable to Output Disable ee ce ns ‘wa Write Recovery Time es ee Note 1: Either input voltage limit or input current limit is sufficient to protect the inputs. Note 2: Output current limit required. Note 3: Typical values are at Voc = 5.0V, Tc = +25°C and maximum loading. Note 4: Static condition only. ‘Note 5: Functional testing done at input levels Vix = 0.45V (Vo, Max) and Vij = 2.4V (Von Min). Note 6: AC testing done at input levels Viy = 3V, Vi. = OV. o Note 7: Short circuit to ground not to exceed one second. Note 8: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern. Note 9: ty measured at twsq = Min. twsa measured at tw = Min. 5-28

' x] Logic Diagram S oN 32x32 DRIVER SENSE AMPS a AND O = were FC BOTTI o¢_ p—s ae FO O _ ADDRESS ADORESS = C—: AD AIAZ ASA4 AS AGAT ABA TL/D/10004-2 Functional Description The 93L425A is a fully decoded 1024-bit read write Random The 93L425A has a three-state output which provides an Access Memory organized 1024 words by one bit. Bit selec- active pull-up or pull-down when enabled and a high imped- tion is achieved by means of a 10-bit address AO-A9. ance (HIGH Z) state when disabled. The active pull-up pro- One Chip Select (CS) input is provided for easy memory vides drive capability for high capacitive loads while the high array expansion of up to 2048 bits without the need for ex- impedance state allows optimization of word expansion in ternal decoding. For larger memories the fast chip select bus organized systems. access time permits direct address decoding without an in- crease in overall memory access time. Truth Table - The read and write functions of the 93L425A are controlled by the state of the active LOW Write Enable WE input. ae Pe | When WE is held LOW and the chip is selected, the data at Dis written into the location specified by the binary address Les [wefo| o | Present at AO through AQ. Since the write function is level H H x HIGH Z Not Selected triggered, data must be held stable at the data input for at L L L HIGH Z Write 0 least ‘wsiminy plus tw(min) Plus twHD(min) t0 insure a valid L L H HIGH Z Write 1 write. When WE is held HIGH and the chip selected, data is L H x Dour Read read from the addressed location and presented at the out- put O. H = HIGH Voltage Level: 2.4v L = LOW Voltage Level: 0.45V X = Don't Care HIGH or LOW HIGH Z = High-Impedance 5-29

22 HIGH Zoqeee | cHIGH Z--

FIGURE 1. AC Test Output Load FIGURE 3. Read Mode Timing

3.0 Vpp

FIGURE 2. AC Test Input Levels.

Note 2: input voltage levels for worst case AC test are 3.0V-OV. FIGURE 4. Write Mode Timing