93L415A

93L415A NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

o Cc J National 5 “4 Semiconductor s 93L415A 1024 x 1-Bit Static Random Access Memory General Description Features The 931415A is a 1024-bit read write Random Access ™ New design to replace old 93415/93L415 Memory (RAM), organized 1024 words by one bit. It is de- ™ Improved ESD thresholds signed for high speed cache, control and buffer storage ap- _™ Alpha hard without die coat plications. The device includes full on-chip decoding, sepa- _@ Commercial address access time rate Data input and non-inverting Data output, as well as an 93L415A 25 ns max active LOW Chip Select line. m Features open collector output ™ Power dissipation decreases with Increasing temperature en Connection Diagram 16-Pin DIP ay, a1 16 FVog nom 15d Mos 14 WE a4 13Fe a9 as 12-48 M—q6 11Pa7 . 0-47 10 Fas cNo—]8 ob as TL/D/10003~1 Top View Order Number 93L415ADC or 93L415APC See NS Package Number J16A” and N16E* Optional Processing QR = Burn-in *For most current package information, contact product marketing. Logic Symbol Pin Names | 15 4 Chip Select Input 6 9 Active LOW = A0-A9 4 x WE Write Enable Input ss Active LOW 9—f a5 93LAISA eer [oT ata outpue 13—] a9 TU/0/10003-3 = 5 GND = Pins 5-15

wo . =| Absolute Maximum Ratings Guaranteed Operating Ranges a If Military/Aerospace specified devices are required, Supply Voltage (Voc) a please contact the National Semiconductor Sales Commercial 5.0V +5% Office/Distributors for availability and specifications. Case Temperature (To) Above which the useful life may be impaired ‘Commercial OC to +75°C Storage Temperature 65°C to + 150°C ‘Supply Voltage Range -0.5V to +7.0V Input Voltage (DC) (Note 1) —0.5V to Vec Input Current (DC) —12mAto +5.0mA Voltage Applied to Outputs (Note 2) ~0.5V to 5.5V Lead Temperature (Soldering, 10 sec.) 300°C Maximum Junction Temperature (Ty) +1758°C Output Current +20mA DC Characteristics over operating temperature ranges (Note 3) symbol | Parameter | Conations_ | min | typ | Max | Unite Vou Output LOW Vottage Voo=Minin= tema | | | ows |v Vin Input HIGH Voltage Guaranteed Input HIGH Voltage for All Inputs (Notes 4, 5, & 6) Vit Input LOW Voltage Guaranteed Input LOW Voltage Vv for All Inputs (Notes 4, 5, & 6)

7 Vee =MaxYn= Veo | |__| 10 | ma

Vic Input Diode Clamp Voltage | Voo=Maxin=-1oma | | -10 | -15 |v loex Output Leakage Current Voc = Max, Vout = 4.5V [ [10 [ 100 | ya lec Power Supply Current Voc = Max, All Inputs = GND mA Output is Open 5-16

o ao symbol_[ Parameter | Conditions [win | max | units | 2 READ TIMING E Chip Select Access T ee {ACS ip ime Figures ns tres Chip Select Recovery Time a ee taa Address Access Time (Note 7) [| a [ os WRITE TIMING tw Write Pulse Width to Guarantee ns Writing (Note 8) twso Data Setup Time Prior to Write [ 5s | [| ‘wx Data Hold Time after Write [5 | [| os twsa Address Setup Time Prior 5 to Write (Note 8) Figure 4 ns twHa Address Hold Time after Write | 5s [| | os twscs Chip Select Setup Time Prior to Write | 5s [| | os twrcs Chip Select Hold Time after Write [| s | | oo tws Write Enable to Output Disable | [| 1 | ns Note 1: Either input voltage limit or input current limit sufficient to protect the inputs. Note 2: Output current limit required. Note 3: Typical values are at Voc = 5.0V, Tc = +25°C and maximum loading. Note 4: Tested under static condition only. Note 5: Functional testing done at input levels Vj_ = 0.45V (Vo. Max) and Vij, = 2.4V (Vox Min). Note 6: AC testing done at input levels Vij = 3V, Vy = OV. - Note 7: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern. Note 8: ty, measured at twsa = Min. twsa measured at tw = Min. 5-17

wo . : = | Logic Diagram a oO oa Al 22. reece Oaver 32x32 ARRAY AS: AM T SENSE AMPS ° C | p— & bb WRITE DRIVERS a ‘L=o ° ADDRESS 3 DECODER AS AG A7 AB AD ‘TL/D/10003-2 (AO through A9). To assure a valid write, data setup-(twsp), Truth Table address setup (twsa), data hold (twp), and address hold [inputs | Outputs | (twua) times must be met. When WE is held HIGH and the chip selected, data is read from the addressed location and [os [we[o]{ o | presented atthe output O. H x x H Not Selected An open collector output is provided to allow maximum flexi- L L L H Write “0” bility in output connection. In many applications such as L L H H Write "1" memory expansion, the outputs of many 93L415As can be tied together. In other applications the wired-OR is not used. L H x Dout Read In either case an external pull-up resistor of R, value must H = HIGH Voltage Levet: 2.4V be used to provide a HIGH at the output when the chip is kr bone atte tom deselected. Any R,_ value within the range specified below may be used. Functional Description Yoo (Max), < Voc (Min) ~ Vou _ The 9314154 is a fully decoded 1024-bit read/write Ran- to ~ FO(.8) nilcex) + FO (0.04) dom Access Memory organized 1024 words by one bit. Bit RL is in ko . selection is achieved by means of a 10-bit address AQ = number of wired-OR outputs tied together through Ag. FO = number of TTL Unit Loads (UL) driven an loex = Memory Output Leakage Current One Chip Select input is provided for easy memory array CEX = i expansion of up to 2048 bits without the need for external Nor = Beau et aon ‘evel at Output Node decoding. For larger memories, the fast chip select access OL utp ure} | time permits direct address decoding without an increase in The minimum R_ value is limited by the output current sink- overall memory access time. ing ability. The maximum R, value is determined by the out- The read and write functions of the 93L415A are controlled Put and input leakage current which must be supplied to by the state of the active low chip select (CS) input. The old the output at Vou. write function is controlled by the active low write enable One Unit Load = 40 wA HIGH/1.6 mA LOW. (WE) input. With CS held low and WE held low, the data (0) FOmax = 5 UL. | is written into the memory location specified by addresses 518

3.0 Vpp

FIGURE 1. AC Test Circuit FIGURE 2. AC Test Input Levels FIGURE 3. Read Mode Timing FIGURE 4. Write Mode Timing fit various applications as long as the worst case limits are not violated.