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Y Serial to parallel capability Y Eight bits of storage with output of each bit available Y Random (addressable) data entry Y Active high demultiplexing or decoding capability Y Easily expandable Y Common conditional clear Connection Diagram Dual-In-Line Package TL/F/10201 1 Order Number 93L34DMQB or 93L34FMQB See NS Package Number J16A or W16A Logic Symbol TL/F/10201 2 VCC Pin 16 GND Pin 8 Pin Names Description A0–A3 Address Inputs D Data Input E Enable Input (Active LOW) CL Clear Input (Active LOW) Q0–Q7 Parallel Latch Outputs C1995 National Semiconductor Corporation RRD B30M105/Printed in U S A

Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range Military b55§Ct o a125§C Storage Temperature Range b65§Ct o a150§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter 93L34 (Mil) Units Min Nom Max VCC Supply Voltage 4.5 5 5.5 V VIH High Level Input Voltage 2 V VIL Low Level Input Voltage 0.7 V IOH High Level Output Voltage b400 mA IOL Low Level Output Current 4.8 mA TA Free Air Operating Temperature b55 125 §C ts (H) Setup Time HIGH, D to E 45 ns th (H) Hold Time HIGH, D to E b5n s ts (L) Setup Time LOW, D to E 45 ns th (L) Hold Time LOW, D to E b7n s ts (H) Setup Time HIGH or LOW 10 nsts (L) An to E 10 tw (L) E Pulse Width LOW 26 ns tw (L) CL Pulse Width LOW 35 ns Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units(Note 1) VI Input Clamp Voltage VCC Min, I I b10 mA b1.5 V VOH High Level Output Voltage V CC Min, I OH Max, 2.4 VVIL Max, V IH Min VOL Low Level Output Voltage V CC Min, I OL Max, 0.3 VVIH Min, V IL Max II Input Current @ Max VCC Max, V I 5.5V 1m AInput Voltage IIH High Level Input Current V CC Max, V I 2.4V Inputs 20 mA E 30 IIL Low Level Input Current V CC Max, V I 0.3V Inputs b0.4 mA E b0.6 IOS Short Circuit VCC Max (Note 2) b2.5 b25 mAOutput Current ICC Supply Current VCC Max (Note 3) 21 mA Note 1: All typicals are at V CC 5V, T A 25§C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICC is measured with all outputs open and all inputs grounded.

Switching Characteristics VCC a5.0V, T A a25§C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter CL 15 pF Units Min Max tPLH Propagation Delay 45 nstPHL E to Q n 42 tPLH Propagation Delay 65 nstPHL Dt oQ n 45 tPLH Propagation Delay 66 nstPHL An to Q n 66 tPHL Propagation Delay 55 nsCL to Q n Functional Description The 93L34 has four modes of operation which are shown in the Mode Select Table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the Data input with all non-ad- dressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the Enable should be held HIGH while the Address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output will follow the state of the D input with all other outputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the 93L34 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. Mode Select Table E CL Mode L H Addressable Latch H H Memory L L Active HIGH 8-Channel Demultiplexer H L Clear

CL E A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L H X X X LLLLLLLL Clear L L L L L DLLLLLLL Demultiplex L L H L L LDLLLLLL L L L H L LLDLLLLL L L H H H LLLLLLLL H H X X X Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Memory H L L L L D Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Addressable H L H L L Qt–1 D Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Latch H L L H L Qt–1 Qt–1 D Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 H L H H H Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 Qt–1 D H HIGH Voltage Level L LOW Voltage Level X Immaterial Qt–1 Previous Output State

Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 93L34DMQB

93L34 8-Bit Addressable Latch Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 93L34FMQB LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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