93L28DMQB

93L28 NSC | Alldatasheet

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Y 2-input multiplexer provided at data input of each register Y Gated clock input circuitry Y Both true and complementary outputs provided from last bit of each register Y Asynchronous master reset common to both registers Connection Diagram Dual-In-Line Package TL/F/10200–1 Order Number 93L28DMQB or 93L28FMQB See NS Package Number J16A or W16A Logic Symbol TL/F/10200–2 VCC e Pin 16 GND e Pin 8 Pin DescriptionNames S Data Select Input D0, D1 Data Inputs CP Clock Pulse Input (Active HIGH) Common (Pin 9) Separate (Pins 7 and 10) MR Master Reset Input (Active LOW) Q7 Last Stage Output Q

7 Complementary Output

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range MIL b55§Ct o a125§C Storage Temperature Range b65§Ct o a150§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter 93L28 (MIL) Units Min Nom Max VCC Supply Voltage 4.5 5 5.5 V VIH High Level Input Voltage 2 V VIL Low Level Input Voltage 0.7 V IOH High Level Output Current b400 mA IOL Low Level Output Current 4.8 mA TA Free Air Operating Temperature b55 125 §C ts(H) Setup Time HIGH or LOW 30 nsts(L) D n to CP 30 th(H) Hold Time HIGH or LOW 0 nsth(L) D n to CP 0 tw(H) Clock Pulse Width 55 nstw(L) HIGH or LOW 55 tw(L) MR Pulse Width with CP HIGH 60 ns tw(L) MR Pulse Width with CP LOW 70 ns

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units(Note 1) VI Input Clamp Voltage V CC e Min, I I eb 10 mA b1.5 V VOH High Level Output Voltage V CC e Min, I OH e Max, 2.4 VVIL e Max, V IH e Min VOL Low Level Output Voltage V CC e Min, I OL e Max, 0.3 VVIH e Min, V IL e Max II Input Current @ Max V CC e Max, V I e 5.5V 1m AInput Voltage IIH HIGH Level V CC e Max, V I e 2.4V MR ,D x 2 0 Input Current CP (7, 10) 30 mA S4 0 CP Com 60 IIL LOW Level V CC e Max, V I e 0.3V MR ,D x b400 Input Current CP (7, 10) b600 mA S b800 CP Com b1200 IOS Short Circuit V CC e Max b2.5 b25 mAOutput Current (Note 2) ICC Supply Current V CC e Max 25.3 mA Note 1: All typicals are at V CC e 5V, T A e 25§C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC ea 5.0V, T A ea 25§C (See Section 1 for test waveforms and output load) Symbol Parameter CL e 15 pF Units Min Max fmax Maximum Shift Right Frequency 5.0 MHz tPLH Propagation Delay 45 nstPHL CP to Q 7 or Q 7 80 tPHL Propagation Delay MR to Q 7 110 ns

The two 8-bit shift registers have a common clock input (pin 9) and separate clock inputs (pins 10 and 7). The clocking of each register is controlled by the OR function of the sep- arate and the common clock input. Each register is com- posed of eight clocked RS master/slave flip-flops and a number of gates. The clock OR gate drives the eight clock inputs of the flip-flops in parallel. When the two clock inputs (the separate and the common) to the OR gate are LOW, the slave latches are steady, but data can enter the master latches via the R and S input. During the first LOW-to-HIGH transition of either, or both simultaneously, of the two clock inputs, the data inputs (R and S) are inhibited so that a later change in input data will not affect the master; then the now trapped information in the master is transferred to the slave. When the transfer is complete, both the master and the slave are steady as long as either or both clock inputs re- main HIGH. During the HIGH-to-LOW transition of the last remaining HIGH clock input, the transfer path from master to slave is inhibited first, leaving the slave steady in its pres- ent state. The data inputs (R and S) are enabled so that new data can enter the master. Either of the clock inputs can be used as clock inhibit inputs by applying a logic HIGH signal. Each 8-bit shift register has a 2-input multiplexer in front of the serial data input. The two data inputs D0 and D1 are controlled by the data select input (S) following the Boolean expression: Serial data in: S D e SD0 a SD1 An asynchronous master reset is provided which, when acti- vated by a LOW logic level, will clear all 16 stages indepen- dently of any other input signal. Shift Select Table Inputs Output SD 0D 1Q 7 ( t na8) LL X L LH X H HX L L HX H H H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial na8 e Indicates state after eight clock pulse Logic Diagram TL/F/10200–3

Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 93L28DMQB

93L28 Dual 8-Bit Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 93L28FMQB LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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