93L00

93L00 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

Features

Y Asynchronous master reset Y J, K inputs to first stage Connection Diagram Dual-In-Line Package TL/F/9576–1 Order Number 93L00DMQB or 93L00FMQB See NS Package Number J16A or W16A Logic Symbol TL/F/9576–2 VCC e Pin 16 GND e Pin 8 Pin Names Description PE Parallel Enable Input (Active LOW) P0–P3 Parallel Inputs J First Stage J Input (Active HIGH) K First Stage K Input (Active LOW) CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input Q0–Q3 Parallel Outputs Q

3 Complementary Last Stage Output

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range MIL b65§Ct o a125§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter 93L00 (MIL) Units Min Nom Max VCC Supply Voltage 4.5 5 5.5 V VIH High Level Input Voltage 2 V VIL Low Level Input Voltage 0.7 V IOH High Level Output Voltage b0.4 mA IOL Low Level Output Current 4.8 mA TA Free Air Operating Temperature b55 125 §C ts (H) Setup Time HIGH or LOW, 60 nsts (L) J, K and P0–P3 to CP 60 th (H) Hold Time HIGH or LOW, 0 nsth (L) J, K and P0–P3 to CP 0 ts (H) Setup Time HIGH or LOW, 68 nsts (L) PE to CP 68 th (H) Hold Time HIGH or LOW, 0 nsth (L) PE to CP 0 tw (H) CP Pulse Width 38 nstw (L) HIGH or LOW 38 tw (L) MR Pulse Width LOW 53 ns trec Recovery Time, MR to CP 70 ns

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units(Note 1) VI Input Clamp Voltage V CC e Min, I I eb 10 mA b1.5 V VOH High Level Output Voltage V CC e Min, I OH e Max, 2.4 3.4 VVIL e Max, V IH e Min VOL Low Level Output Voltage V CC e Min, I OL e Max, 0.3 VVIH e Min, V IL e Max II Input Current @ Max V CC e Max, V I e 5.5V 1m AInput Voltage IIH High Level Input Current V CC e Max, V I e 2.4V Inputs 20 CP 40 mA PE 46 IIL Low Level Input Current V CC e Max, V I e 0.3V Inputs b400 CP b800 mA PE b920 IOS Short Circuit V CC e Max b2.5 b25 mAOutput Current (Note 2) ICC Supply Current V CC e Max 23 mA Note 1: All typicals are at V CC e 5V, T A e 25§C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC ea 5.0V, T A ea 25§C (See Section 1 for waveforms and load configurations) 93L Symbol Parameter C L e 15 pF Units Min Max fmax Maximum Shift Frequency 10 MHz tPLH Propagation Delay 35 nstPHL CP to Q n 51 tPHL Propagation Delay, MR to Q n 60 ns

The Logic Diagrams and Truth Table indicate the functional characteristics of the 93L00 4-bit shift register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial-to-parallel, or parallel-to-serial data transfers. The 93L00 has two primary modes of operation, shift right (Q0 xQ1) and parallel load, which are controlled by the state of the Parallel Enable (PE ) input. When the PE input is HIGH, serial data enters the first flip-flop Q0 via the J and K inputs and is shifted one bit in the direction xQ1xQ2xQ3 following each LOW-to-HIGH clock transition. The JK inputs provide the flexibility of the JK type input for special applications, and the simple D-type input for general applications by tying the two pins together. When the PE input is LOW, the 93L00 appears as four com- mon clocked D flip-flops. The data on the parallel inputs P0–P3 is transferred to the respective Q0–Q3 outputs fol- lowing the LOW-to-HIGH clock transition. Shift left opera- tion (Q3 xQ2) can be achieved by tying the Qn outputs to the Pn b1 inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occur- ing after each LOW-to-HIGH clock transition. Since the 93L00 utilizes edge triggering, there is no restriction on the activity of the J, K , Pn and PE inputs for logic operationÐex- cept for the setup and release time requirements. A LOW on the asynchronous Master Reset (MR ) input sets all Q out- puts LOW, independent of any other input condition. Truth Table Operating Inputs (MR e H) Outputs @ tna1 Mode PE JK P0 P1 P2 P3 Q0 Q1 Q2 Q3 Q 3 H L L X X X X L Q0 Q1 Q2 Q 2 Shift Mode H LH X X X X Q 0Q 0Q 1Q 2Q 2 H H L XXXX Q 0Q 0Q 1Q 2Q 2 H H H X X X X H Q0 Q1 Q2 Q 2 Parallel L X X L L L L L L L L H Entry Mode L X X H H H H H H H H L *tna1 e Indicates state after next LOW-to-HIGH clock transition. H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial

TL/F/9576–3

Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 93L00DMQB

93L00 4-Bit Universal Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 93L00FMQB LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (

a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.