93CS46

ST93CS46 STMICROELECTRONICS | Alldatasheet

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1K (64 x 16) SERIAL MICROWIRE EEPROM NOT FOR NEW DESIGN June 1997 1/16 This is information on a product still in production but not recommended for new designs. AI00884B D VCC ST93CS46 ST93CS47 VSS CQ PRE W S Figure 1. Logic Diagram

1 MILLION ERASE/WRITE CYCLES, with

40 YEARS DATA RETENTION

DESCRIPTION

The ST93CS46 and ST93CS47 are 1K bit Electri- cally Erasable Programmable Memory (EEPROM) fabricatedwith SGS-THOMSON’s High Endurance Single Polysilicon CMOS technology. The memory is accessed through a serial input D and output Q. The 1K bit memory is organized as 64 x 16 bit words.The memory is accessed by a set of instruc- tions which include Read, Write, Page Write, Write All and instructions used to set the memory protec- tion. A Read instruction loads the address of the first word to be read into an internal address pointer. S Chip Select Input D Serial Data Input Q Serial Data Output C Serial Clock PRE Protect Enable W Write Enable VCC Supply Voltage VSS Ground Table 1. Signal Names

Figure 3. AC Testing Input Output Waveforms Note: 1. Sampled only, not 100% tested. Table 3. Capacitance(1) Table 4. DC Characteristics(TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS46 and

Notes:1. Chip Select must be brought low for a minimum of 250 ns (tSLSH ) between consecutive instruction cycles.

1. The Clock frequency specification calls for a minimum clock period of 1µs, therefore the sum of the timings tCHCL +tCLCH

must be greater or equal to 1µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns. Table 5. DC Characteristics(TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS46 and Figure 4. Synchronous Timing, Start and Op-Code Input

Figure 5. Synchronous Timing, Read or Write

first followed by the 16 bit word with the MSB first. Table 6. Instruction Set

Output data changes are triggered by the Low to High transition of the Clock (C). The ST93CS46/47 will automatically increment the address and will clock out the next word as long as the Chip Select input (S) is held High. In this case the dummy ’0’ bit is NOT output between words and a continuous stream of data can be read. Write Enable and Write Disable The Write Enable instruction (WEN) authorizes the following Write instructions to be executed, the Write Disable instruction (WDS) disables the exe- cution of the following Erase/Write instructions. When power is first applied, the ST93CS46/47 enters the Disable mode. When the Write Enable instruction (WEN) is executed, Write instructions remain enabled until a Write Disable instruction (WDS) is executed or if the Power-on reset circuit becomes active due to a reduced V CC . To protect the memory contents from accidental corruption, it is advisable to issue the WDS instruction after every write cycle. The READ instruction is not affected by the WEN or WDS instructions. Write The Write instruction (WRITE) is followed by the address and the word to be written. The Write Enable signal (W) must be held high during the WRITE instruction. Data input D is sampled on the Low to High transition of the clock. After the last data bit has been sampled, Chip Select (S) must be brought Low before the next rising edge of the clock (C), in order to start the self-timed program- ming cycle, providing that the addressis NOT in the protected area. If the ST93CS46/47 is still per- forming the programming cycle, the Busy signal (Q = 0) will be returned if the Chip Select input (S) is driven high, and the ST93CS46/47 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93CS46/47 is ready to receive a new instruction. Page Write A Page Write instruction (PAWRITE) contains the first address to be written followed by up to 4 data words. The Write Enable signal (W) must be held High duringthe Write instruction.Input address and data are read on the Low to High transition of the clock. After the receipt of each data word, bits A1-A0 of the internal address register are incre- mented, the high order bits A5-A2 remaining un- changed. Users must take care by software to ensure that the last word address has the same four upper order address bits as the initial address transmitted to avoid address roll-over. After the LSB of the last data word, Chip Select (S) must be brought Low before the next rising edge of the Clock (C). The falling edge of Chip Select (S) initiates the internal, self-timed write cycle. The Page Write operation will not be performed if any of the 4 words is addressing the protected area. If the ST93CS46/47 is still performing the program- ming cycle, the Busy signal (Q = 0) will be returned if the Chip Select input (S) is driven high, and the ST93CS46/47 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93CS46/47is ready to receive a newinstruc- tion. Write All The Write All instruction (WRALL) is valid only after the ProtectRegisterhas been cleared byexecuting a PRCLEAR (Protect Register Clear) instruction. The Write All instruction simultaneously writes the whole memory with the same data word included in the instruction. The Write Enablesignal (W) must be held High before and during the Write instruc- tion. Input address and data are read on the Low to High transition of the clock. If the ST93CS46/47 is still performing the programming cycle, the Busy signal (Q = 0) will be returned if the Chip Select input (S) is driven high, and the ST93CS46/47 will ignore any data on the bus. When the write cycle is completed,the Ready signal (Q = 1) will indicate (if S is driven high) that the ST93CS46/47 is ready to receive a new instruction. MEMORY WRITE PROTECTION AND PROTECT REGISTER The ST93CS46/47 offers a Protect Register con- taining the bottom address of the memory area which has to be protected against write instruc- tions. In addition to this Protect Register, two flag bits are used to indicatethe Protect Registerstatus: the Protect Flag enabling/disabling the protection of theProtect Register andthe OTPbit which, when set, disables access to the Protect Register and thus prevents any further modifications of this Pro- tect Register value. The content of the Protect Register is defined when using the PRWRITE in- struction, it may be read when using the PRREAD instruction. A specific instruction PREN (Protect Register Enable) allows the user to execute the protect instructions PRCLEAR, PRWRITE and PRDS; this PREN instruction being used together with the signals applied on the input pins PRE (Protect Register Enable pin) and W (Write En- able). ST93CS46, ST93CS47

Figure 6. READ, WRITE, WEN, WDS Sequences

Figure 7. PAWRITE, WRALL Sequences

Accessing the Protect Register is done by execut- ing the following sequence: – WEN: execute the Write Enable instruction, – PREN: execute the PREN instruction, – PRWRITE, PRCLEAR or PRDS: the protection then may be defined, in terms of size of the protected area (PRWRITE, PRCLEAR) and may be set permanently (PRDS instruction). Protect Register Read The Protect Register Read instruction (PRREAD) outputs on the Data Output Q the content of the Protect Register, followed by the Protect Flag bit. The Protect Register Enable pin (PRE) must be driven High before and during the instruction. As in the Read instruction a dummy ’0’ bit is output first. Since it is not possible to distinguish if the Protect Register is cleared (all 1’s) or if it is written with all 1’s, user must check the Protect Flag status (and not the Protect Register content) to ascertain the setting of the memory protection. Protect Register Enable The Protect Register Enable instruction (PREN) is used to authorize the use of further PRCLEAR, PRWRITE and PRDS instructions. The PREN insruction does not modify the Protect Flag bit value. Note: A Write Enable (WEN) instruction must be executed before the Protect Enable instruction. Both the Protect Enable (PRE) and Write Enable (W) input pins must be held High during the instruc- tion execution. Protect Register Clear The Protect Register Clear instruction (PRCLEAR) clears the address stored in the Protect Register to all 1’s, and thus enables the execution of WRITE and WRALL instructions. The Protect Register Clear execution clears the Protect Flag to ’1’. Both the Protect Enable (PRE) and Write Enable (W) input pins must be driven High during the instruc- tion execution. Note: A PREN instruction must immediately pre- cede the PRCLEAR instruction. Protect Register Write The Protect Register Write instruction (PRWRITE) is used to write into the Protect Register the ad- dress of the first word to be protected. After the PRWRITE instruction execution, all memory loca- tions equal to and above the specified address, are protected from writing. The Protect Flag bit is set to ’0’, it can be read with Protect Register Read instruction. Both the Protect Enable (PRE) and Write Enable (W) input pins must be driven High during the instruction execution. Note: A PREN instruction must immediately pre- cede the PRWRITE instruction, but it is not neces- sary to execute first a PRCLEAR. Protect Register Disable The Protect Register Disable instruction sets the One Time Programmable bit (OTP bit). The Protect RegisterDisable instruction(PRDS) is a ONETIME ONLY instruction which latches the Protect Regis- ter content, this content is therefore unalterable in the future.Boththe ProtectEnable (PRE) and Write Enable (W) input pins must be driven High during the instruction execution. The OTP bit cannot be directly read, it can be checked by reading the content of the Protect Register (PRREAD instruc- tion), then by writing this same value into the Pro- tect Register (PRWRITE instruction): when the OTP bit is set, the Ready/Busy status cannot ap- pear on the Data output (Q); when the OTP bit is not set, the Busy status appear on the Data output (Q). A PREN instruction must immediately precede the PRDS instruction. READY/BUSY Status When the ST93CS46/47 is performing the write cycle, the Busy signal (Q = 0) is returned if S is driven high, and the ST93CS46/47 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate, if S is driven high, that the ST93CS46/47 is ready to receive a new instruction. Once the ST93CS46/47 is Ready, the Data Output Q is set to ’1’ until a new Start bit is decoded or the Chip Select is brought Low. COMMON I/O OPERATION The Data Output (Q)and Data Input(D) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. Some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (A0) and the first data bit output by Q. The reader should refer to the SGS-THOMSON application note ”MICROWIRE EEPROM Common I/O Opera- tion”. MEMORY WRITE PROTECTION (cont’d) ST93CS46, ST93CS47

110 X n X 0

Figure 8. PRREAD, PRWRITE, PREN Sequences

Figure 9. PRCLEAR, PRDS Sequences

ORDERING INFORMATION SCHEME Operating Voltage 46 3V to 5.5V 47 2.5V to 5.5V Package B PSDIP8 0.4 mm Frame M SO8 150mil Width Temp. Range 1 0 to 70 °C 6 –40 to 85 °C 3 (1) –40 to 125°C Option 013TR Tape & Reel Packing Example: ST93CS46 M 1 013TR Note: 1. Temperature range on request only. Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh). For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. ST93CS46, ST93CS47

A L D E1 E N C eA eB B Symb mm inches Typ Min Max Typ Min Max A 4.80 0.189 A1 0.70 – 0.028 – A2 3.10 3.60 0.122 0.142 B 0.38 0.58 0.015 0.023 B1 1.15 1.65 0.045 0.065 C 0.38 0.52 0.015 0.020 D 9.20 9.90 0.362 0.390 E1 6.30 7.10 0.248 0.280 eA 8.40 – 0.331 – eB 9.20 0.362 L 3.00 3.80 0.118 0.150 N8 8 CP 0.10 0.004 PSDIP8 Drawing is not to scale PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame ST93CS46, ST93CS47

E N CPB e A D C LA1 α H hx4 5° Symb mm inches Typ Min Max Typ Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N8 8 CP 0.10 0.004 SO8 Drawing is not to scale SO8 - 8 lead Plastic Small Outline, 150 mils body width ST93CS46, ST93CS47

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.  1997 SGS-THOMSON Microelectronics - All Rights Reserved  MICROWIRE is a registered trademark of National Semiconductor Corp. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. ST93CS46, ST93CS47