93C66 | DigiCamel IC Datasheet

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93C56 MICROCHIP | Alldatasheet

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2K/4K 5.0V CMOS Serial EEPROM FEATURES PACKAGE TYPE * Low power CMOS technology DIP * ORG pin selectable memory organization S ~ 256 x8 or 128 x 16 bit organization (93056) ~ 512 x8 oF 256 x 16 bit organization (93066) esU1 8H vee * Single 5 volts only operation cukO2 ee 70m + Max clock at 2 MHz 88 ; * Self-timed ERASE and WRITE cycles os 8 3 6(lore * Automatic ERASE before WRITE * Power on/off data protection circuitry vo (4 5] vss + Industry standard 3-wire serial YO * Device status signal during ERASEWRITE, solic cycles * Sequential READ function oT * 1,000,000 ERASE/WRITE cycles guaranteed cst 814 Veo * Data retention > 40 years * 8-pin PDIP/SOIC packages oxC2 gg 7orest {SOIC in JEDEC and EIAJ standards) g 3 * Available for extended temperature ranges: oc ° 6 EJ ore + Commercial: 0°C to +70°C ~ Industrial: -40°C to +85°C vo C4 5h vss = Automotive: -40°C to +125°C * 1ms byte write time BLOCK DIAGRAM

DESCRIPTION

The Mictochip Technology inc. 93C56/66 family of Serial EEPROM are configurable to either x16 or x8 organization. The ORG pin is used to select the teuony 7] avoness desired configuration. Advanced CMOS technology ARRAY DECODER makes this device ideal for low-power non-volatile memory applications. The 93C56/6 are available in the standard 8-pin DIP and 8-pin surface mount SOIC. ‘sooness package, SR This device offers fast (1 ms) byte write and extended (-40°C to +125°C) temperature operation. It is recom- 0 mended that all other applications use Microchip's _ 93LC56/93LC66, a cs | toate ox OMe Meche Technology ie mg 40320) OOL2277 Th? MM — S11180Rpace4-39

a

1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: _ PIN FUNCTION TABLE

14 Maximum Ratings* [Nene [Function

VeC.nmsninnrimnnrtnemsnnnennnnrnnnnnneT OM os Grip Select Storage tomPETAtUrE unsere 65°C 10 4150°C DI Serial Data Input Ambient temp. with power applied... -65°C to +125°C bo Serial Data Output Soldering temperature of leads (10 seconds) ..+300°C Vss Ground entcarage © he cng, Te a ee an aad tite pore) Tost Connect to Vss or Veo (Soberdrs pesoienayntos anton whose nm muro constons Vee Power Supply +5V TABLE 1-2: _ DC CHARACTERISTICS Industrial) Tamb=-40°C to +86°C Veo = +8V (10%) ‘Automotive (E):_ Tamb = -40°C to +125°C Voc = +5V (+10%) (Note 2) [Parameter [_Symbot_[ min [ Max [Unite [Conditions | [Vecdetectorthresnod S| vim | 2s | a8 fv Tak vipa vtege [vw | 20ers vf [twioetrpuvoiege [we | 03 08 |v [ich ode vctags [vow [24 [| __v _forecaoopme [cote ouparwtage [va | =| ea | ¥fn=aima [Inputteakage curent | tw | | 10 [A [Wu=ovtovec [ouputeslap cured [to [=~] | va _[veur=ov ove Inpteaasinnes | ~ en [=| 7] oF enour nate | [Operating current(allmodes) | iecwrte | — [4 | ma [Fekk=2MHzVoo=s8v_ | eee PE See | [=| =f t00 [a Jes = Ovi Veo S8Vixi6ora | [Giocktrequeney | Fo [| Me PO [Clockhigntime | Town | aso | [ons [Giockiowtime | Tome | 260 | [nsf [Chip selectsetuptime =| ‘toss | 60 | — | ns [RelatvetoGik [Chip setecthoidtime =| Tos | 0 | ~— [ns [RelaivetoGiK [Soest twine [tex [f= foe [Datainputseuptime | tos | too | — | ns [RelatvetoGik [Datainputhotdtime | ton | 100 | — | ns [Relatvetocik [ai ot cay ira [two [=| we [rw [eee tooer | [Data outpatdsabietime | Tez [= [100 [ns [cl=toopr [Subsidies [tw [eo] te fet tooer Program cycle time | ES ee (auto ERASE and WRITE) [2 | ms [(et6 organization) | [ee [Sse ema a ne Note 1 This parameter is tesied at Tamb = 25°C and FOLK = 1 MHz, It is periodically sampled and not 100% tested Note 2: For operation above 85°C, endurance is rated at 10,000 ERASE/WAITE cycles. DS11180B-page 4-40 © 1995 Microchip Technology Inc. @ 6103201 0012298 973 me

2.0 FUNCTIONAL DESCRIPTION After power-up, the device is automatically in the

; f EWDS mode, Therefore, an EWEN instruction must be The 93C56/66 family can be organized x16 or x8. performed before any ERASE or WRITE instruction When the ORG pin is connected to Vcc, the (x16) orga- can be executed. After programming is completed, the nization is selected. When it is connected to ground, EWDS instruction offers added protection against unin- the (x8) organization is selected. If the ORG pin is left tended data changes. unconnected, then an intemal pullup device will select the (x16) organization. Instructions, addresses and 3.0 READ write data are clocked into the DI pin on the rising edge The READ instruction outputs the serial data of the of the clock (CLK). The DO pin is normally held in a addressed memory location on the DO pin. A dummy high-Z state except when reading data from the device, Zoro bit precedes the 16 bit (x16 organization) or 8 bit or when checking the ready/busy status during @ pro- (8 organization) output string. The output data bits will gramming operation. |The ready/ousy status can be toggle on the rising edge of the CLK and are stable Verified during an Erase/Write operation by polling the after the specified time delay (TPD). Sequential read is DO pin; DO low indicates that programming is stil in possible when CS is held high. The memory data will progress, while DO high indicates the device is ready. cutoratically cycle to the next register and output ‘The DO will enter the high-Z state on the falling edge of Sequentialy the CLK. :

4.0 ERASE/WRITE ENABLE AND

24 START Condition DISABLE

The START bit is detected by the device if CS and DI The 98C56/66 powers up in the Erase/Write Disable are both HIGH with respect to the positive edge of CLK (EWDS) state. All programming modes must be pre- for the first time. coded by an Erase/Write Enable (EWEN) instruction. Before a START condition is detected, CS, CLK, and DI ‘Once the EWEN instruction is executed, programming may change in any combination (except to that of a remains enabled uni an EWDS instruction is executed START codon. witout resulting inary device per dora ata changes, the EWOS intucton ean be ation (READ, 4 , EWEN, EWDS, ERAL, ! nee end WRAL). As soon as CS is HIGH, the device is no beh he ae aie opera functions and should in the standby mode. . oer , 7 READ instruction is independent of both the EWEN An instruction following a START condition will only be and EWDS instructions. executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. 5.0 ERASE After execution of an instruction (i.e., clock in or out of The ERASE instruction forces all data bits of the spec- the last required address or data bit) CLK and DI ified address to the logical "1" state. CS is brought low become don't care bits until a new start condition is following the loading of the last address bit. This falling detected. ‘edge of the CS pin initiates the self-timed programming cycle. 22 pypo The DO pin indicates the READY/BUSY status of the Itis possible to connect the Data in and Data Out pins device it CS is brought high after a minimum of 100 ns together. However, with this configuration it is possible low (Tost). DO at logical “O" indicates that program- for a “bus conflict’ to occur during the “dummy zero” ming is stil in progress. DO at logical "1" indicates that that precedes the READ operation, if AO is a logic HIGH the register at the specified address has been erased level. Under such a condition the voltage level seen at and the device Is ready for another instruction. Data Out is undefined and will depend upon the relative ‘The ERASE cycle takes 1 ms per byte maximum. impedances of Data Out and the signal source driving Wri ‘AO. The higher the current sourcing capability of AO, 6.0 ITE the higher the voltage at the Data Out pin The WRITE instruction is followed by 16 bits (or by 8 23 5, bits) of data which are written into the specified : Data Protection address, After the last data bit is put on the DI pin, CS ‘ ion are inhi be brought low before the next rising edge of the During power-up, all modes of operation are inhibited must ntlowt " until Voc has reached 2.3 V. During power-down, the CLK clock. This falling edge of CS inilates the sol source data protection circuitry acts to inhibit all modes timed auto-erase and programming cycle. when Vc has fallen below 2.3 V. ‘The DO pin indicates the READY/BUSY status of the ive acid device it CS is brought high after a minimum of 100 ns The EWEN and EWDS commands give additional pro- h after tection against accidentally programming during nor- Cosy rato ieleates that pee is rene mal operation. progress. DO at logical "1" indicates that the register at Inc. OsiiteeSrase+2 wg 4103201 0012300 381 Mm © 1998 Mirochip Teennolgy ne

the specified address has been written with the data CLK can be stopped anywhere in the transmission specified and the device is ready for another instruc- sequence (at HIGH or LOW level) and can be contin- tion. ued anytime with respect to clock HIGH time (TckH) , and clock LOW time (TcxL). This gives the controlling ‘The WRITE cycle takes 1 ms per byte maximum. vel er byt master freedom in preparing opcode, address, and 7.0 ERASE ALL data. The ERAL instruction will erase the entire memory CLK is. “Don't Care” if CS is LOW (device deselected). array to the logical "1", The ERAL cycle is identical to 1 CS is HIGH, but START condition has not been the ERASE cycle except for the different opcode. The detected, any number of clock cycles can be received ERAL cycle is completely self-timed and commences by the device without changing its status (Le., waiting at the falling edge of the CS. Clocking of the CLK pin for START condition), is not necessary after the device has entered the self CLK cycles are not required during the sel-timed clocking mode. WRITE (ie., auto ERASEMRITE) cycle. The DO pin indicates the READY/BUSY status of the ‘Altordotection of a start condition the spect BO pin I 8 JS’ ecified number device it CS is brought high after a minimum of 100 ns of clock cycles (respectively LOW to HIGH transitions low (Tost) and before the entire write cycle is com- of CLK) must be provided. These clock cycles are plete. required to clock in all required opcode, address, and The ERAL cycle takes 15 ms maximum. data bits before an instruction is executed (see instruc- tion set truth table). CLK and DI then become don't

8.0 WRITE ALL care inputs waiting for a new start condition to be

‘The WRAL instruction will write the entire memory detected. array with the data specified in the command. The ae “netwaen consees WRAL cycle is completely self-limed and commences ~~ at the falling edge of the CS. Clocking of the CLK pin oe Be is not necessary after the device has entered the self clocking mode. The WRAL command does not include 93 Data in (DD an automatic ERASE cycle for the device. Therefore, Data In is used to clock in a START bit, opcode, the WRAL instruction must be preceded by an ERAL. address, and data synchronously with the CLK input. instruction and the chip must be in the EWEN status in both cases. 9.4 Data Out (D The DO pin indicates the READY/BUSY status of the Data Out is used in the READ mode to output data syn- device if CS is brought high after a minimum of 100 ns chronously with the CLK input (TPo after the positive low (Test). edge of CLK). The WRAL cycle takes 15 ms maximum. This pin also provides READY/BUSY status informa- . 9.0 PIN DESCRIPTION tion during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is . 9.1 Chip Select (CS) brought HIGH after being LOW tor minimum chip select : LOW time (Tost) and an ERASE or WRITE operation AHIGH level selects the device. A LOW level dese- has been initiated. ' fects the device and forces it into standby mode. How- The status signal is not available on DO, if CS is held ever, a programming cycle which ie already inklated LOW or HIGH during the entire WRITE or ERASE and/or in progress wil be completed, regardiess of the cycle. In all other cases DO is in the HIGH-Z mode. If CS input signal. if CS is brought LOW during a pro- status is checked after the WRITE/ERASE cycle, a gram cycle, the device will go Into standby mode es pull-up resistor on DO is required to read the READY soon as the programming cycle is completed, oral CS must be LOW for 100 ns minimum (Test) between oe consecutive instructions. If CS is LOW, the intemal 9.5 Organization (ORG) trol logic is held in a RESET status. sontrollogés §5 neki'n When ORG is connected to Veo, the (x16) memory 9.2 Serial Clock (CLK) organization is selected. When ORG is tied to Vs, the ; (x8) memory organization is selected. When ORG is. The Serial Clock Is used to synchronize the communt- left floating, an intemal pullup device will select the cation between a master device and the 93C56/68. device in (x16) organization. : Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits ara also clocked out on 9.6 Test ; the positive edge of CLK. This pin is used for test mode only. It is recommended ; to connect to Voc or Vss for normal operation. © tees Mecrocnip Technolesy re. Wa L1O320) 0012301 218 me 08111006-page 4-49

93C56/66 Product Identification System Jo order or to obtain information, .g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 93C56/66 - /P Package: P= Plastic DIP (300 mil Body) SN = Plastic SOIC (150 mil Body) SM = Plastic SOIC (207 mil Body) Temperature Blank = 0°C to +70°C Range: 1 = -40°C to +85°C E = -40°C to+125°C Device: 93056 2K CMOS Serial EEPROM 93C56T 2K CMOS Serial EEPROM (Tape and Reel) 93C66 4K CMOS Serial EEPROM 93c66T 4K CMOS Serial EEPROM (Tape and Reel) Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1.Your local Microchip sales office 2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 2.The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required) Please specify which device, revision of silicon and Data Sheet (include Literature +#) you are using. For latest version information and upgrade kits for Microchip t Tools, please call 1-800-755-2345 or 1-602-786-7302. DS11180B-page 4-48 7 © 1995 Microchip Technology Inc. MH 6103201 0012305 963 a

Product Information

93C66 specifications and overview.

Summary

2K/4K 5.0V CMOS Serial EEPROM

Description

2K/4K 5.0V CMOS Serial EEPROM

Source title 93C66 Datasheet(PDF) - Microchip Technology

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