93C56AT-E/ST

93AA56A_07 MICROCHIP | Alldatasheet

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© 2007 Microchip Technology Inc. DS21794E-page 1 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C Device Selection Table Features:

• Low-power CMOS technology
• ORG pin to select word size for ‘56C’ version
• 256 x 8-bit organization ‘A’ ver. devices (no ORG)
• 128 x 16-bit organization ‘B’ ver. devices (no ORG)
• Self-timed erase/write cycles (including auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential read function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Pb-free and RoHS compliant
• Temperature ranges supported: Pin Function Table Description: The Microchip Technology Inc. 93XX56A/B/C devices are 2K bit low-voltage serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as the 93AA56C, 93LC56C or 93C56C are dependent upon external logic levels driving the ORG pin to set word size. For dedicated 8-bit communication, the 93XX56A devices are available, while the 93XX56B devices provide dedicated 16-bit communication. Advanced CMOS technology makes these devices ideal for low-power, nonvolatile memory applications. The entire 93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. All packages are Pb-free and RoHS compliant. Part Number VCC Range ORG Pin Word Size Temp Ranges Packages 93AA56A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT, MC 93AA56B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT, MC 93LC56A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC 93LC56B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC 93C56A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC 93C56B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC 93AA56C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST, MS, MC 93LC56C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS, MC 93C56C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS, MC - Industrial (I) -40°C to +85°C - Automotive (E) -40°C to +125°C Name Function CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output VSS Ground NC No internal connection ORG Memory Configuration VCC Power Supply 2K Microwire Compatible Serial EEPROM

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 2 © 2007 Microchip Technology Inc. Package Types (not to scale) CS CLK DI DO VCC NC ORG* VSS PDIP/SOIC (P, SN) CS CLK DI DO VCC NC ORG* VSS ROTATED SOIC (ex: 93LC46BX) TSSOP/MSOP CS CLK DI DO VCC NC ORG* VSS (ST, MS) SOT-23 DO VSS DI VCC CS CLK (OT) * ORG pin is NC on A/B devices DFN CS CLK DI DO NC ORG* VSS VCC

© 2007 Microchip Technology Inc. DS21794E-page 3 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†) TABLE 1-1: DC CHARACTERISTICS †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All parameters apply over the specified ranges unless otherwise noted. Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V Param. No. Symbol Parameter Min Typ Max Units Conditions VIH1 VIH2 High-level input voltage 2.0

0.7 VCC

V V VCC ≥ 2.7V VCC < 2.7V VIL1 VIL2 Low-level input voltage -0.3 -0.3 0.8

0.2 VCC

V V VCC ≥ 2.7V VCC < 2.7V Vol1 Vol2 Low-level output voltage 0.4 0.2 V V IOL = 2.1 mA, VCC = 4.5V IOL = 100 μA, VCC = 2.5V VOH1 VOH2 High-level output voltage 2.4 VCC - 0.2 V V IOH = -400 μA, VCC = 4.5V IOH = -100 μA, VCC = 2.5V ILI Input leakage current μA VIN = VSS or VCC ILO Output leakage current μA VOUT = VSS or VCC CIN, COUT Pin capacitance (all inputs/ outputs) pF VIN/VOUT = 0V (Note 1) TA = 25°C, FCLK = 1 MHz ICC write Write current 500 mA μA FCLK = 3 MHz, Vcc = 5.5V FCLK = 2 MHz, Vcc = 2.5V ICC read Read current 100 500 mA μA μA FCLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 3.0V FCLK = 2 MHz, VCC = 2.5V D10 ICCS Standby current μA μA I – Temp E – Temp CLK = CS = 0V ORG = DI = VSS or VCC (Note 2) (Note 3) D11 VPOR VCC voltage detect 1.5 3.8 V V 93AA56A/B/C, 93LC56A/B/C (Note 1) 93C56A/B/C Note 1: This parameter is periodically sampled and not 100% tested. ORG pin not available on ‘A’ or ‘B’ versions. Ready/Busy status must be cleared from DO, see Section 3.4 "Data Out (DO)".

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 4 © 2007 Microchip Technology Inc. TABLE 1-2: AC CHARACTERISTICS All parameters apply over the specified ranges unless otherwise noted. Industrial (I): TA = -40°C to +85°C, VCC = +1.8V TO +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V Param. No. Symbol Parameter Min Max Units Conditions FCLK Clock frequency MHz MHz MHz 4.5V ≤ VCC < 5.5V, 93XX56C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V TCKH Clock high time 200 250 450 ns ns ns 4.5V ≤ VCC < 5.5V, 93XX56C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V TCKL Clock low time 100 200 450 ns ns ns 4.5V ≤ VCC < 5.5V, 93XX56C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V TCSS Chip Select setup time 100 250 ns ns ns 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V TCSH Chip Select hold time ns 1.8V ≤ VCC < 5.5V TCSL Chip Select low time 250 ns 1.8V ≤ VCC < 5.5V TDIS Data input setup time 100 250 ns ns ns 4.5V ≤ VCC < 5.5V, 93XX56C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V TDIH Data input hold time 100 250 ns ns ns 4.5V ≤ VCC < 5.5V, 93XX56C only 2.5V ≤ VCC < 5.5V 1.8V ≤ VCC < 2.5V TPD Data output delay time 200 250 400 ns ns ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 2.5V ≤ VCC < 4.5V, CL = 100 pF 1.8V ≤ VCC < 2.5V, CL = 100 pF A10 TCZ Data output disable time 100 200 ns ns 4.5V ≤ VCC < 5.5V, (Note 1) 1.8V ≤ VCC < 4.5V, (Note 1) A11 TSV Status valid time 200 300 500 ns ns ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 2.5V ≤ VCC < 4.5V, CL = 100 pF 1.8V ≤ VCC < 2.5V, CL = 100 pF A12 TWC Program cycle time ms Erase/Write mode (AA and LC versions) A13 TWC ms Erase/Write mode (93C versions) A14 TEC ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V A15 TWL ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V A16 Endurance cycles 25°C, VCC = 5.0V, (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. This application is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which may be obtained from Microchip’s web site at www.microchip.com.

© 2007 Microchip Technology Inc. DS21794E-page 5 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C FIGURE 1-1: SYNCHRONOUS DATA TIMING TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX56B OR 93XX56C WITH ORG = 1) TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX56A OR 93XX56C WITH ORG = 0) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE X (RDY/BSY) ERAL X X X X X X (RDY/BSY) EWDS X X X X X X High-Z EWEN X X X X X X High-Z READ X D15 – D0 WRITE X D15 – D0 (RDY/BSY) WRAL X X X X X X D15 – D0 (RDY/BSY) Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE X A7 A6 A5 A4 A3 A2 A1 A0 (RDY/BSY) ERAL X X X X X X X (RDY/BSY) EWDS X X X X X X X High-Z EWEN X X X X X X X High-Z READ X A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 WRITE X A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY) WRAL X X X X X X X D7 – D0 (RDY/BSY) CS VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL CLK DI DO (Read) DO (Program) TCSS TDIS TCKH TCKL TDIH TPD TCSH TPD TCZ Status Valid TSV TCZ Note: TSV is relative to CS.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 6 © 2007 Microchip Technology Inc. 2.0 FUNCTIONAL DESCRIPTION When the ORG pin (93XX56C) pin is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a High-Z state except when read- ing data from the device, or when checking the Ready/ Busy status during a programming operation. The Ready/Busy status can be verified during an Erase/ Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. DO will enter the High-Z state on the falling edge of CS. 2.1 START Condition The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (Read, Write, Erase, EWEN, EWDS, ERAL or WRAL). As soon as CS is high, the device is no longer in Standby mode. An instruction following a Start condition will only be executed if the required opcode, address and data bits for any particular instruction are clocked in. 2.2 Data In/Data Out (DI/DO) It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO. 2.3 Data Protection All modes of operation are inhibited when VCC is below a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices or 3.8V for ‘93C’ devices. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before the initial ERASE or WRITE instruction can be executed. Block Diagram Note: When preparing to transmit an instruction, either the CLK or DI signal levels must be at a logic low as CS is toggled active high. Note: For added protection, an EWDS command should be performed after every write operation and an external 10 kΩ pull-down protection resistor should be added to the CS pin. Memory Array Data Register Mode Decode Logic Clock Register Address Decoder Address Counter Output Buffer DO DI ORG* CS CLK VCC VSS *ORG input is not available on A/B devices

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 12 © 2007 Microchip Technology Inc. 3.0 PIN DESCRIPTIONS TABLE 3-1: PIN DESCRIPTIONS 3.1 Chip Select (CS) A high level selects the device; a low level deselects the device and forces it into Standby mode. However, a programming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. 3.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communi- cation between a master device and the 93XX series device. Opcodes, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to Clock High Time (TCKH) and Clock Low Time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “don’t care” if CS is low (device deselected). If CS is high, but the Start condition has not been detected (DI = 0), any number of clock cycles can be received by the device without changing its status (i.e., waiting for a Start condition). CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle. After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed. CLK and DI then become “don’t care” inputs waiting for a new Start condition to be detected. 3.3 Data In (DI) Data In (DI) is used to clock in a Start bit, opcode, address and data synchronously with the CLK input. 3.4 Data Out (DO) Data Out (DO) is used in the Read mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status infor- mation is available on the DO pin if CS is brought high after being low for minimum Chip Select low time (TCSL) and an erase or write operation has been initiated. The Status signal is not available on DO, if CS is held low during the entire erase or write cycle. In this case, DO is in the High-Z mode. If status is checked after the erase/write cycle, the data line will be high to indicate the device is ready. 3.5 Organization (ORG) When the ORG pin is connected to VCC or Logic HI, the (x16) memory organization is selected. When the ORG pin is tied to VSS or Logic LO, the (x8) memory organization is selected. For proper operation, ORG must be tied to a valid logic level. 93XX56A devices are always x8 organization and 93XX56B devices are always x16 organization. Name SOIC/PDIP/ MSOP/TSSOP/ DFN SOT-23 Rotated SOIC Function CS Chip Select CLK Serial Clock DI Data In DO Data Out VSS Ground ORG/NC Organization / 93XX56C No Internal Connection / 93XX56A/B NC No Internal Connection VCC Power Supply Note: After a programming cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO.

© 2007 Microchip Technology Inc. DS21794E-page 13 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 4.0 PACKAGING INFORMATION 4.1 Package Marking Information Example: 6-Lead SOT-23 8-Lead MSOP (150 mil) Example: XXXXXXT YWWNNN 3L56BI 5281L7 XXNN 2EL7 T/XXXNNN XXXXXXXX YYWW 8-Lead PDIP 8-Lead SOIC XXXXYYWW XXXXXXXT NNN XXXX TYWW 8-Lead TSSOP NNN I/P 1L7 93LC56B 0528 Example: Example: SN 0528 93LC56BI 1L7 1L7 L56B I528 Example: 8-Lead 2x3 DFN Example: 344 528 XXX YWW NN e e

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 14 © 2007 Microchip Technology Inc. Note: T = Temperature grade (I, E) NN = Alphanumeric traceability code Part Number 1st Line Marking Codes TSSOP MSOP SOT-23 DFN I Temp. E Temp. I Temp. E Temp. 93AA56A A56A 3A56AT 2BNN 331 93AA56B A56B 3A56BT 2LNN 341 93AA56C A56C 3A56CT 351 93LC56A L56A 3L56AT 2ENN 2FNN 334 335 93LC56B L56B 3L56BT 2PNN 2RNN 344 345 93LC56C L56C 3L56CT 354 355 93C56A C56A 3C56AT 2HNN 2JNN 337 338 93C56B C56B 3C56BT 2TNN 2UNN 347 348 93C56C C56C 3C56CT 357 358 Legend: XX...X Part number or part number code T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e e

© 2007 Microchip Technology Inc. DS21794E-page 15 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e

0.65 BSC

A 1.10 Molded Package Thickness 0.75 0.85 0.95 Standoff 0.00 0.15 Overall Width E

4.90 BSC

3.00 BSC

D L 0.40 0.60 0.80 Footprint

0.95 REF

φ Lead Thickness c 0.08 0.23 Lead Width b 0.22 0.40 D N E NOTE 1 e b A c L φ Microchip Technology Drawing C04-111B

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 16 © 2007 Microchip Technology Inc. 6-Lead Plastic Small Outline Transistor (CH or OT) [SOT-23] Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e

0.95 BSC

1.90 BSC

A 0.90 1.45 Molded Package Thickness 0.89 1.30 Standoff 0.00 0.15 Overall Width E 2.20 3.20 Molded Package Width 1.30 1.80 Overall Length D 2.70 3.10 Foot Length L 0.10 0.60 Footprint 0.35 0.80 Foot Angle φ 30° Lead Thickness c 0.08 0.26 Lead Width b 0.20 0.51 b E N PIN 1 ID BY LASER MARK D e A c L φ Microchip Technology Drawing C04-028B

© 2007 Microchip Technology Inc. DS21794E-page 17 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N Pitch e .100 BSC Top to Seating Plane A .210 Molded Package Thickness .115 .130 .195 Base to Seating Plane .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB .430 N NOTE 1 D A L b e E eB c Microchip Technology Drawing C04-018B

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 18 © 2007 Microchip Technology Inc. 8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e

1.27 BSC

A 1.75 Molded Package Thickness 1.25 Standoff § 0.10 0.25 Overall Width E

6.00 BSC

3.90 BSC

D Chamfer (optional) h 0.25 0.50 Foot Length L 0.40 1.27 Footprint

1.04 REF

φ Lead Thickness c 0.17 0.25 Lead Width b 0.31 0.51 Mold Draft Angle Top α 15° Mold Draft Angle Bottom β 15° D N e E NOTE 1 b A L c h h φ β α Microchip Technology Drawing C04-057B

© 2007 Microchip Technology Inc. DS21794E-page 19 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e A 1.20 Molded Package Thickness 0.80 1.00 1.05 Standoff 0.05 0.15 Overall Width E

6.40 BSC

4.30 4.40 4.50 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint

1.00 REF

φ Lead Thickness c 0.09 0.20 Lead Width b 0.19 0.30 D N E NOTE 1 b e c A L φ Microchip Technology Drawing C04-086B

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 20 © 2007 Microchip Technology Inc. 8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e

0.50 BSC

A 0.80 0.90 1.00 Standoff 0.00 0.02 0.05 Contact Thickness

0.20 REF

D

2.00 BSC

E 1.30 1.75 Exposed Pad Width 1.50 1.90 Contact Width b 0.18 0.25 0.30 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 D N E NOTE 1 EXPOSED PAD NOTE 1 K L N e b A NOTE 2 BOTTOM VIEW TOP VIEW Microchip Technology Drawing C04-123B

© 2007 Microchip Technology Inc. DS21794E-page 21 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C APPENDIX A:

REVISION HISTORY

Corrections to Section 1.0, Electrical Characteristics. Section 4.1, 6-Lead SOT-23 package to OT. Revision C Added DFN package. Revision D (11/2006) Updated Package Drawings and Product ID System Revision E (3/2007) Replaced Package Drawings; Revised Product ID System (SOIC-SN package).

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 22 © 2007 Microchip Technology Inc. NOTES:

© 2007 Microchip Technology Inc. DS21794E-page 23 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

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• Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 24 © 2007 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response From: Name Company Address City / State / ZIP / Country Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: DS21794E 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C What are the best features of this document? How does this document meet your hardware and software development needs? Do you find the organization of this document easy to follow? If not, why? What additions to the document do you think would enhance the structure and subject? What deletions from the document could be made without affecting the overall usefulness? Is there any incorrect or misleading information (what and where)? How would you improve this document?

© 2007 Microchip Technology Inc. DS21794E-page 25 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: 93AA56A: 2K 1.8V Microwire Serial EEPROM 93AA56B: 2K 1.8V Microwire Serial EEPROM 93AA56C: 2K 1.8V Microwire Serial EEPROM w/ORG 93LC56A: 2K 2.5V Microwire Serial EEPROM 93LC56B: 2K 2.5V Microwire Serial EEPROM 93LC56C: 2K 2.5V Microwire Serial EEPROM w/ORG 93C56A: 2K 5.0V Microwire Serial EEPROM 93C56B: 2K 5.0V Microwire Serial EEPROM 93C56C: 2K 5.0V Microwire Serial EEPROM w/ORG Pinout: Blank Standard pinout X Rotated pinout Tape & Reel: Blank Standard packaging T Tape & Reel Temperature Range: I -40°C to +85°C E -40°C to +125°C Package: MS Plastic MSOP (Micro Small outline, 8-lead) OT SOT-23, 6-lead (Tape & Reel only) P Plastic DIP (300 mil body), 8-lead SN Plastic SOIC (3.90 mm body), 8-lead ST TSSOP, 8-lead MC 2x3 DFN, 8-lead Examples: 93AA56C-I/MS: 2K, 256x8 or 128x16 Serial EEPROM, MSOP package, 1.8V 93AA56B-I/MS: 2K, 128x16 Serial EEPROM, MSOP package, 1.8V 93AA56AT-I/OT: 2K, 256x8 Serial EEPROM, SOT-23 package, tape and reel, 1.8V 93AA56CT-I/MS: 2K, 256x8 or 128x16 Serial EEPROM, MSOP package, tape and reel, 1.8V 93LC56A-I/MS: 2K, 256x8 Serial EEPROM, MSOP package, 2.5V 93LC56BT-I/OT: 2K, 128x16 Serial EEPROM, SOT-23 package, tape and reel, 2.5V 93LC56B-I/MS: 2K, 128x16 Serial EEPROM, MSOP package, 2.5V 93C56B-I/MS: 2K, 128x16 Serial EEPROM, MSOP package, 5.0V 93C56C-I/MS: 2K, 256x8 or 128x16 Serial EEPROM, MSOP package, 5.0V 93C56AT-I/OT: 2K, 256x8 Serial EEPROM, SOT-23 package, tape and reel, 5.0V PART NO. X /XX Package Temperature Range Device X Tape & Reel X Pinout

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C DS21794E-page 26 © 2007 Microchip Technology Inc. NOTES:

© 2007 Microchip Technology Inc. DS21794E-page 27 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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