NMC93C56 NSC | Alldatasheet
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. 4 NMC93C56/C66 2048-Bit/4096-Bit Serial z Electrically Erasable Programmable Memories g General Description Compatibility with Other Devices 2 The NMC93C56/NMC93C66 are 2048/4096 bits of CMOS These memories are pin compatible to National Semicon- electrically erasable memory divided into 128/256 16-bit ductor’s NMOS EEPROMs, NMC8306 and NMC9346 and registers. They are fabricated using National Semiconduc- | CMOS EEPROMs NMC93C06/46. The NMC93C56/66 are tor's floating-gate CMOS process for high speed and low _ both pin and function compatible with the NMC93C06/46, power. They operate from a single 5V supply since Vpp is 256/1024-bit EEPROM with the one exception that the generated on-board. The serial organization allow the © NMC93C56/66 require 2 additional address bits. NMC93C56/66 to be packaged in an 8-pin DIP or 14-pin SO Package to save board space. Features The memories feature a serial interface with the instruction, ™ Typical active current 400 HA; Typical standby current address, and write data, input on the Data-In (Dl) pin. All 25 pA read data and device status come out on the Data-Out (D0) '® Reliable CMOS floating gate technology pin. A low-to-high transition of shift clock (SK) shifts all data 5V only operation in all modes in and out. This serial interface is MICROWIRE™ compati- gs MICROWIRE compatible serial 1/0 ble tor simple interface to standard microcontrollers and mi- m Self-timed programmi le croprocessors. There are 7 instructions: Read, Erase/Write elt Progra ung Cyc! Enable, Erase, Erase All, Write, Write All, and Erase/Write Device status signal during programming mode Disable. The NMC93C56/66 do not require an erase cycle ™ Sequential register read prior to the Write and Write All instructions. The Erase and ™ Over 40 years data retention Erase All instructions are available to maintain complete = Designed for 100,000 write cycles read and programming capability with the NMOS NMC9346. All programming cycles are completely self-timed for simpli- fied operation. The busy status is available on the DO pin to . indicate the completion of a programming cycle. EEPROMs are shipped in the erased state where alll bits are logical 1’s. Sees Block Diagram cs INSTRUCTION Ye sk DECODER, CONTROL LOGIC, GENERATORS, ‘ADORESS HIGH VOLTAGE REGISTER GENERATOR AND PROGRAM TMER EEPROM ARRAY DECODER 2048/4096 BITS trze/ass x 16) —\\s
16 BITS BIT
TL/D/9617~1 2-53 www.chipdocs.com Be sure to visit ChipDocs web site for more information.
9| Connection Diagrams a
3 Dual-in-Line Package (N) Pin Names SO Package (M)
< ay, Chip Select ay, 8 cs i cd [sk | Serial Data Clock Nom ‘arene g sk—]2 TNC lo | Serial Data Input cs—42 13F-Vo g ots s-Nc ~ sks 12E-NC = pos fon |_Do | Serial Data Output nea 1 NC = [eno | Ground | os 10f-ne TUD 2 Topview Powor Supply po~ls sone nc7 8i-nc See NS Package Number NOSE TU/e617-3 Top View See NS Package Number M14A
Ordering Information
Commercial Temp. Range (0°C to + 70°C) NMC93C56N/NMC93C66N NMC93C56M/NMC93C66M Extended Temp. Range (— 40°C to +85°C) NMC93C56EN/NMCS3C66EN - NMC93C56EM/NMC93C66EM Military Temp. Range (—55°C to + 125°C) NMC93C56MN/NMC93C86MN NMC93C56MM/NMC93C66MM 2-54 www.chipdocs.com Be sure to visit ChipDocs web site for more information.
z . ., = Absolute Maximum Ratings (note 1) Operating Conditions Oo If Milltary/Aerospace specified devices are required, Ambient Operating Temperature 3 please contact the National Semiconductor Sales NMC93C56/NMC93C66 OC to + 10°C Office/Distributors for availability and specifications. NMC93C56E/NMC93C66E ~40°C to +85°C $ Ambient Storage Temperature ~65°C to + 150°C NMC93C56M/NMC93C66M 7 2 All Input or Output Voltages +6.5V to —0.3V (Mil. Temp.) TSEC to 125°C FS with Respect to Ground Positive Power Supply 4svto55v |B Lead Temp. (Soldering, 10 sec.) +300°C 8 ESD Rating 2000V 3 DC and AC Electrical Characteristics vc = sv + 10% (unless otherwise specified) loci Operating Current | NMC93C56/NMC93C66 CS = Vin, SK = 1 MHz CMOS Input Levels | NMC93C56E/NMC93C66E SK = 0.5 MHz mA NMC93C56M/NMC93C66M" | SK = 0.5 MHz loce Operating Current | NMC93C56/NMC93C66 CS = Vy, SK = 1 MHz TTL Input Levels NMC93C56E/NMC93C66E SK = 0.5 MHz mA NNMC93C56M/NMC93C66M_—_| SK = 0.5 MHz loca Standby Current NMC93C56/NMC93C66 cs = ov 50 NMC93C56E/NMC93C66E 100 pA NMC93C56M/NMC83C66M 100 te Input Leakage NMC93C56/NMC93C66 Vin = OV to Veg -25 25 NMC93C56E/NMC93C66E -10 10 mn NMC93C56M/NMC93C66M =10 10 lou Output Leakage NMC98C56/NMC93C86 Vin = OV to Veg -25 A NMC93C56E/NMC93C66E =10 _* ‘A NMC93C56M/NMC93C66M —10 MV Viv Input Low Voltage 0.8 v Vin Input High Voltage Veot1 | ov Vou Output Low NMC93CS56/NMC93C566 lo, = 2.1mA 04 Voltage NMC93CS56E/NMC93C566E | Io, = 2.1mA 04 v NMC93CS56M/NMC93C566M | Io. = 1.8 mA 04 Vous Output High low = 400 pA v Voltage Voie | Output Low Voltage lot = 10 pA 7 Vox2 _| Output High Voltage lon = —10 yA Voc - 0.2 v tsk SK Clock Frequency | NMC93C56/NMC93C66 NMC93C56E/NMC93C66E MHz NMC93C56M/NMC93C66M tskH SK High Time NMC93C56/NMC93C66 (Note 2) 250 NMC93C56E/NMC93C66E (Note 3) 500 ns NMC93C56M/NMC93C66M _| (Note 3) 500 tsk SK Low Time NMC93C56/NMC93C66 (Note 2) 250 2 NMC93C56E/NMC93C66E (Note 3) 500 ns NMCS3C56M/NMC93C66M__| (Note 3) 500 tes Minimum CS NMC93C56/NMC93C66 (Note 4) 250 Low Time NMC93C56E/NMC9SC66E (Note 5) 500 ns NMC93C56M/NMC93C66M | (Note 5) 500 tess CS Setup Time NMC93C56/NMC93C66 Relative to SK 50 NMC93C56E/NMC93C66E 100 ns NMC83C56M/NMC93C66M 100 “Note: Throughout this table “M’" refers to temperature range {(—55°C to + 125°C), not package type. 2-55, www.chipdocs.com Be sure to visit ChipDocs web site for more information.
9 |_ DC and AC Electrical Characteristics voc = sv + 10% (unless otherwise specified) (Continued) oo &|__symbot_[ Parameter | Part Number Conditions [| Min | Max | unite 31 tos 01 Setup Time NMC93C56/NMC93C66 Relative to SK 100 $ NMC93C56E/NMC93C66E 200 ns oO NMC93C56M/NMC93C66M 200 | _tos csHodtime | | olatvotosk | co | | as =! tow DI Hold Time NMG93C56/NMC9SC66 Relative to SK 100 z NMC93C56E/NMC93C66E 200 ns NMC93C56M/NMC93C66M 200 tos Output Delay to “1” NMC93C56/NMC83C86 AC Test 500 NMC93C56E/NMC93C66E 1000 ns NMC93C56M/NMC93C66M 1000 tepo Output Delay to “0” NMC93C56/NMC93C66 AC Test 500 NMC93CS56E/NMC93C66E 1000 ns NMC93C56M/NMC93C66M 1000 tev CS to Status Valid NMC93C56/NMC93C66 AC Test 500 NMC93C56E/NMC93C66E 1000 ns NMC93C56M/NMC83C66M 1000 tor CS to DO in NMC93C56/NMC93C66 AC Test 100 TRI-STATE® NMC93C56E/NMC93C66E cS = Vit 200 ns NMC93C56M/NMC93C66M 200 we |_wrtecyietime [Tt Ts Note 1; Stress above those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maxamum rating conditions for extended periods may affect device reliability. Note 2: The SK frequency specification for Commercial parts specifies a minimum SK clock period of 1 4s, therefore in an SK clock cycle tga + tgxi must be greater than or equal to 1 1s. For example if tex, = 250 ns then the minimum tex = 750 ns in order to meet the SK frequency specification. Note 3: The SK frequency speciication for Extended Temperature and Military parts specifies a minimum SK clock period of 2 48, theratore in an SK clock cycle tskH + texi must be greater than or equal to 2 us. For example, if the tsk, = 500 ns then the minimum tx} = 1.5 us in order to meet the SK frequency ‘specification. Note 4: For Commercial parts CS must be brought low for a minimum of 250 ns (tos) between consecutive instruction cycles. Note 5: For Extended Temperature and Military parts CS must be brought low for a minimum of 500 ns (ics) between consecutive instruction cycles. Note 6: This parameter is periodically sampled and not 100% tested. Capacitance (note 6) AC Test Conditions Ta = 25°C f = 1 MHz Output Load 1 TTL Gate and C, = 100 pF | Cour | Output Capacitance | | pF | Timing Measurement Reference Level Cour | Outpurcapacitance | | 5 | oF Input Vand 2V ImpurCapacitnce | | 5 | oF | Output o.8V and 2v 2-56 www.chipdocs.com Be sure to visit ChipDocs web site for more information.
z Functional Description 5 ‘The NMC93C56 and NMC93C686 have 7 instructions as de- Write (WRITE): FS scribed below. Note that the MSB of any instruction is a ‘“1" The Write (WRITE) instruction is followed by 16 bits of data and is viewed as a start bit in the interface sequence. The to be written into the specified address. After the last bit of Ea next 10-bits carry the op code and the 8-bit address for data is put on the data-in (Dl) pin, CS must be brought low | & register selection. before the next rising edge of the SK clock. This falling edge = Read (READ): Of CS initiates the self-timed programming cycle. The DO | Q The Read (READ) instruction outputs serial data on the DO pin indicates the READY/BUSY status of the chip if CS is 8 pin. After a READ instruction is received, the instruction and brought high after a minimum of 250 ns (ts). 00 = logical g address are decoded, followed by data transfer from the 0 indicates that programming is still in progress. DO = logi- selected memory register into a 16-bit serial-out shift regis- cal 1 indicates that the register at the address specified in ter. A dummy bit (logical 0) precedes the 16-bit data output the instruction has been written with the data pattern speci- string. Output data changes are initiated by a low to high fied in the instruction and the part is ready for another in- transition of the SK clock. struction, Erase/Write Enable (EWEN): Erase All (ERAL): When Vcc is applied to the part, it powers up in the Erase/ The ERAL instruction will simultaneously program all regis- Write Disable (EWDS) state. Therefore, all programming ters in the memory array and set each bit to the logical ‘1’ modes must be preceded by an Erase/Write Enable State. The Erase All cycle is identical to the ERASE cycle (EWEN) instruction. Once an Erase/Write Enable instruc- except for the different op-code. As in the ERASE mode, tion is executed, programming remains enabled until an the DO pin indicates the READY/BUSY status of the chip if Erase/Write Disable (EWDS) instruction is executed or Voc CS is brought high after a minimum of 250 ns (tes) is removed from the part. Write All (WRAL): Erase (ERASE): The (WRAL) instruction will simultaneously program all reg- The ERASE instruction will program all bits in the specified isters with the data pattern specified in the instruction. As in register to the logical ‘1’ state. CS is brought low following the WRITE mode, the DO pin indicates the READY/BUSY the loading of the last address bit. This falling edge of the Status of the chip if CS is brought high after a minimum of CS pin initiates the self-timed programming cycle. 250 ns (tcs). The DO pin indicates the READY/BUSY status of the chip if Erase/Write Disable (EWDS): CS is brought high after a minimum of 250 ns (tes). To protect against accidental data disturb, the Erase/Write DO = logical ‘0’ indicates that programming is still in prog- Disable (EWDS) instruction disables all programming modes ress. DO = logical ‘1’ indicates that the register, at the and should follow ali programming operations. Execution of address specified in the instruction, has been erased, and a READ instruction is independent of both the EWEN and the part is ready for another instruction. EWDS instructions. Instruction Set for the NMC93C56 and NMC93C66 instruction | 8B | opcode [Address | Data _| Comments mead | 1 [io | arao [| Reais data storedin memory ewen | 1 [00 | six00000 [| Wit enabe must precede al programming modes erase | 1 | 1 | a7-A0_ |__| _ Erase rogister A7AGASA4ASAZAIA0, ; ERAL [1 [00 | toxxxxxx |__| erases all registers, wae | 1 | ot | A7-a0__| _D15-D0_| _ Whites registerif address is unprotected WRAL O1XXXXXX Writes all registers. Valid only when Protect Register is cleared. EWDS [1 | 00 coxxxxxx |__| isabies ait programming instructions, 2.57 www.chipdocs.com Be sure to visit ChipDocs web site for more information.
3 Timing Diagrams
3 Synchronous Data Timing
9 y, tess tes oJ w oO SK Vb 3 4 ‘DS: i i a > Ci SD tor A DO (READ), tsy tor Vou DO (PROGRAM) , STATUS VALID OL Tu0/9617-4 ‘This is the minimum SK period (Note 2). READ: cs / kes, 01 1 ao ne © fF \\VAREX Tu/D/9617-5 “Address bit A7 becomes a “don't care” for NMC93C56._ EWEN: * TUUUUU UU UU UU oO /1\\o oft Nex + Xx\\ TL/D/9617-6 2-58 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.
z Timing Diagrams (continues) 5 . ao Ewps: oO < a g ro} oa JUUUUUUUAUUUU SK a a o /1\\o 0 0 LK KN ‘TL/D/9617-7 WRITE: | ee ( “TU _/\\-POGQOOA ee Busy READY ‘wp TU0/8617-8 *Address bit A7 becomes a “don't cara” for NMC93C56. WRAL: cs / \\ kes / » UU UU ee BusY V7 READY ‘we TuD/9617-9 2-59 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.
: Timing Diagrams (Continued) = ERASE: z 8 « TULL LL, FLA. 8 ‘es 8 ——— cs CHECK STATUS *_STANDBY z tey tH
00 TRI@STATE 5 5 BUSY READY TRISTATE
‘ew TU0/9617-10 ERAL: « TULL LLL, ALP es: cs / ‘CHECK STATUS ‘STANDBY t5y 1H 19 —_ RESTATE 5 pusy READY RIRESIATE tey~w . Tip/9617-11 2-60 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.