93C56

93C56A MICROCHIP | Alldatasheet

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Technical content

ª 1998 Microchip Technology Inc. Preliminary DS21206B-page 1 M 93C56A/B

FEATURES

• Single supply 5.0V operation
• Low power CMOS technology - 1 mA active current (typical) m A standby current (maximum)
• 256 x 8 bit organization (93C56A)
• 128 x 16 bit organization (93C56B)
• Self-timed ERASE and WRITE cycles (including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 100,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Available for the following temperature ranges:

DESCRIPTION

The Microchip Technology Inc. 93C56A/B is a 2K-bit, low-voltage serial Electrically Erasable PROM. The device memory is configured as 256 x 8 bits (93C56A) or 128 x 16 bits (93C56B). Advanced CMOS technol- ogy makes this device ideal for low-power, nonvolatile memory applications. The 93C56A/B is available in standard 8-pin DIP and surface mount SOIC packages. This device is only recommeded for 5V automotive temperature applications. For all commercial and industrial applications, the 93LC56A/B is recom- mended. PACKAGE TYPE BLOCK DIAGRAM - Automotive (E): -40 C to +125 C 93C56A/B CS CLK DI DO VCC NC NC VSS CS CLK DI DO VCC NC NC VSS 93C56A/B SOIC PDIP VCC VSS DI CS CLK DO MEMORY ARRAY ADDRESS DECODER ADDRESS COUNTER DATA REGISTER OUTPUT BUFFER MEMORY DECODE LOGIC CLOCK GENERATOR 2K 5.0V Automotive Temperature Microwire Serial EEPROM Microwire is a registered trademark of National Semiconductor.

ª 1998 Microchip Technology Inc.

1.0 ELECTRICAL

1.1 Maxim um Ratings*

V CC All inputs and outputs w.r.t. V SS C to +150 C C to +125 C C *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may affect device reliability. TABLE 1-1: PIN FUNCTION TABLE Name Function CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output V SS Ground NC No Connect V CC Power Supply TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS All parameters apply over the specified operating ranges unless otherwise noted Automotive (E)V CC = +4.5V to +5.5VTamb = -40 C to +125 C Parameter Symbol Min. Max. Units Conditions High level input voltage V IH 2.0 V CC +1 V (Note 2) Low level input voltage V IL -0.3 0.8 V Low level output voltage V OL — 0.4 V I OL = 2.1 mA; V CC = 4.5V High level output voltage V OH 2.4 — V I OH = -400 m A; V CC = 4.5V Input leakage current I LI -10 10 m AV IN = V SS to V CC Output leakage current I LO -10 10 m AV OUT = V SS to V CC Pin capacitance (all inputs/outputs) C IN , C OUT —7p F V IN OUT = 0 V (Notes 1 & 2) Tamb = +25 C, F CLK = 1 MHz Operating current I CC write — 1.5 mA I CC read — 1 mA Standby current I CCS m A CS = V SS Clock frequency F CLK — 2 MHz Clock high time T CKH 250 — ns Clock low time T CKL 250 — ns Chip select setup time T CSS 50 — ns Relative to CLK Chip select hold time T CSH 0 — ns Relative to CLK Chip select low time T CSL 250 — ns Data input setup time T DIS 100 — ns Relative to CLK Data input hold time T DIH 100 — ns Relative to CLK Data output delay time T PD — 400 ns C L = 100 pF Data output disable time T CZ — 100 ns C L = 100 pF (Note 2) Status valid time T SV — 500 ns C L = 100 pF Program cycle time T WC — 2 ms ERASE/WRITE mode T EC — 6 ms ERAL mode T WL — 15 ms WRAL mode Endurance — 100K — cycles 25 C, V CC = 5.0V, Block Mode (Note 3) Note 1: This parameter is tested at Tamb = 25 C and F CLK = 1 MHz. This parameter is periodically sampled and not 100% tested. This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or web- site.

ª 1998 Microchip Technology Inc. Preliminary DS21206B-page 4-3 93C56A/B

2.0 PIN DESCRIPTION

2.1 Chip Select (CS)

A high level selects the device. A low level deselects the device and forces it into standby mode. However, a programming cycle which is already in progress will be completed, regardless of the CS input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (T CSL ) between consecutive instructions. If CS is low, the internal con- trol logic is held in a RESET status.

2.2 Serial Cloc k (CLK)

The Serial Clock is used to synchronize the communi- cation between a master device and the 93C56A/B. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T CKH ) and clock low time (T CKL ). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a “Don't Care” if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detecting a START condition, the specified num- ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected.

2.3 Data In (DI)

Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.

2.4 Data Out (DO)

Data Out is used in the READ mode to output data syn- chronously with the CLK input (T PD after the positive edge of CLK). This pin also provides READY/BUSY status informa- tion during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (T CSL ) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready. Note: CS must go low between consecutive instructions. TABLE 2-1: INSTRUCTION SET FOR 93C56A Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY )1 2 ERAL 1 0 0 10XXXXXXX — ( R D Y/BSY )1 2 EWDS 1 0 0 00XXXXXXX — HIGH-Z 12 EWEN 1 0 0 11XXXXXXX — HIGH-Z 12 READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 20 WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY )2 0 WRAL 1 0 0 01XXXXXXXD 7 - D 0 ( R D Y/BSY )2 0 TABLE 2-2: INSTRUCTION SET FOR 93C56B Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY )1 1 ERAL 1 0 0 10XXXXXX — ( R D Y/BSY )1 1 EWDS 1 0 0 00XXXXXX — HIGH-Z 11 EWEN 1 0 0 11XXXXXX — HIGH-Z 11 READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27 WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY )2 7 WRAL 1 0 0 01XXXXXX D15 - D0 (RDY/BSY )2 7

DS21206B-page 4 Preliminary ª 1998 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/B USY status during a programming operation. The READY/B USY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS.

3.1 ST AR T Condition

The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device oper- ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected.

3.2 Data IN (DI) and Data Out (DO)

It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation. Under such a condition, the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driv- ing A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin.

3.3 Data Pr otection

During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 3.8V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 3.8V at nominal conditions. The ERASE/WRITE Disable (EWDS) and ERASE WRTE Enable (EWEN) commands give additional pro- tection against accidentally programming during nor- mal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. FIGURE 3-1: SYNCHRONOUS DATA TIMING CS VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL CLK DI DO (READ) DO (PROGRAM) TCSS TDIS TCKH TCKL TDIH TPD TCSH TPD TCZ STATUS VALID TSV TCZ Note: AC Test Conditions: VIL = 0.4V, VIH = 2.4V.

ª 1998 Microchip Technology Inc. Preliminary DS21206B-page 5 93C56A/B

3.4 ERASE

The ERASE instruction forces all data bits of the spec- ified address to the logical “1” state. This cycle begins on the rising clock edge of the last address bit. The DO pin indicates the READY/B USY status of the device if CS is brought high after a minimum of 250 ns low (T CSL ). DO at logical “0” indicates that program- ming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction.

3.5 Erase All (ERAL)

The ERAL instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and com- mences at the rising clock edge of the last address bit. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/B USY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL ) and before the entire ERAL cycle is com- plete. FIGURE 3-2: ERASE TIMING FIGURE 3-3: ERAL TIMING CS CLK DI DO TCSL CHECK STATUS 1 1 1A N AN -1 A N -2 ••• A0 TSV TCZ BUSY READY HIGH-Z TWC HIGH-Z CS CLK DI DO TCSL CHECK STATUS 10 0 1 0X ••• X TSV TCZ BUSY READY HIGH-Z TEC HIGH-Z

DS21206B-page 6 Preliminary ª 1998 Microchip Technology Inc.

3.6 ERASE/WRITE Disab le and Enable

(EWDS/EWEN) The device powers up in the ERASE/WRITE Disable (EWDS) state. All programming modes must be pre- ceded by an ERASE/WRITE Enable (EWEN) instruc- tion. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruc- tion is executed or V CC is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming opera- tions. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.

3.7 READ

The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (93C56A) or 16-bit (93C56B) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (T PD ). Sequential read is possible when CS is held high. The memory data will automati- cally cycle to the next register and output sequentially. FIGURE 3-4: READ TIMING FIGURE 3-5: EWDS TIMING FIGURE 3-6: EWEN TIMING CS CLK DI DO 11 0 An ••• A0 CS CLK DI 10 00 0 X ••• X TCSL CS CLK DI 00 1 1X TCSL

• ••

ª 1998 Microchip Technology Inc. Preliminary DS21206B-page 7 93C56A/B

3.8 WRITE

The WRITE instruction is followed by 8-bits (93C56A) 16-bits (93C56B) of data which are written into the specified address. After the last data bit is clocked into the DI pin, the self-timed auto-erase and programming cycle begins. The DO pin indicates the READY/B USY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL ) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruc- tion.

3.9 Write All (WRAL)

The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and com- mences at the rising clock edge of the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL com- mand does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/B USY status of the device if CS is brought high after a minimum of 250 ns low (T CSL ). FIGURE 3-7: WRITE TIMING FIGURE 3-8: WRAL TIMING CS CLK DI DO BUSY READY HIGH-Z HIGH-Z Twc TCSL TCZTSV CS CLK DI DO HIGH-Z HIGH-Z BUSY READY TWL TCSL TSV TCZ

DS21206B-page 8 Preliminary ª 1998 Microchip Technology Inc. NOTES:

ª 1998 Microchip Technology Inc. Preliminary DS21206B-page 9 93C56A/B NOTES:

DS21206B-page 10 Preliminary ª 1998 Microchip Technology Inc. NOTES:

ª 1998 Microchip Technology Inc. Preliminary DS21206B-page 11 93C56A/B 93C56A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support Package: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead Temperature Range: E = -40 °C to +125°C Device: 93C56A 2K Microwire Serial EEPROM (x8) 93C56AT 2K Microwire Serial EEPROM (x8) Tape and Reel 93C56B 2K Microwire Serial EEPROM (x16) 93C56BT 2K Microwire Serial EEPROM (x16) Tape and Reel 93C56A/B /P Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Y our local Microchip sales office. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. 3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or trademarks mentioned herein are the property of their respective companies. DS21206B-page 12 Preliminary ª 1998 Microchip Technology Inc. All rights reserved. © 1998, Microchip Technology Incorporated, USA. 1/98 Printed on recycled paper. M AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc.

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