93C06 MICROCHIP | Alldatasheet
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\\ 256 Bit/1K 5.0V CMOS Serial EEPROM FEATURES PACKAGE TYPE * Low power CMOS technology DIP 0 + 16 bit memory organization sth 8D Vee . = 6x 16 bit organization (93C06) = 64x 16 bit organization (93C46) cux Cf2 83 7LI Ne * Single 5 volt only operation 8 + Selfstimed ERASE and WRITE cycles ots Ss shyN + Automatic ERASE before WRITE oo Os 50 ves + Power on/off data protection circuitry | * 1,000,000 ERASE/WRITE cycles guaranteed soic oO , | * Data Retention > 40 years | + 8:pin DIP or SOIC package cesC|t BL Vee * Available for extended temperature ranges: CLK 2 7 = Commercial: 0°C to +70°C C4 Fy 8 Fo xe = Industrial: 40°C to +85°C ocds 88 sone + Automotive: -40°C to +125°C + 2ms program cycle time porns 514 ves DESCRIPTION = The Microchip Technology Inc. 93C06/46 family of nocot sync Serial Electrically Erasable PROMS are configured in a . x16 organization. Advanced CMOS technology makes Veot2 % 71 ves these devices ideal for low-power non-volatile memory 3 . applications. The 93C06/46 is available in the standard espa $8 e400 : 8-pin DIP and surface mount SOIC packages. The - 93C46X comes as SOIC only. cues st4o , These devices offer fast (1 ms) byte write and extended (-40°C to +125°C) temperature operation. Itis recom- : mended that all other applications use Microchip's BLOCK DIAGRAM 93LC46. Voc Vas sts aan econeR = ° . | oecone cs tosie Siok ox B 19S Microchip Technology inc. DS11179B-page 4-31 es
i
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE
11 Maximum Ratiogs* [rene [Function |
VCC snsnrnnnneneentnnnniinnnnsennintns TOV cs Chip Select All inputs and outputs Witt, VSS.an0.-0.6V to VEC +1.0V cx _| serial clock Storage temperature .sveceeenrrenmeeecemnene65°C tO +150°C. DI Data in Ambient temperature with power applied .-65°C to +125C Soldering temperature of leads (10 seconds) .e.n4300°C bo Data Out ESD protection on all INS rsnnnneeninnnsnne 4 KV Vss Ground ‘Notice: Stresses above those listed under “Maximum ratings” - ‘may cause permanent damage to the device. This Is a stress rat- No No Connect, No Internal ing only and functional operation of the device at those or any io other conditions above those Indicated in the operational listings of this specication is not implied. Exposure to maximum rating Veo +5V Power Supply Conditions for extended periods may affect device relablity. TABLE 1-2: DC CHARACTERISTICS . Veo = 45V (£10%) : Commercial: Tamb= 0°C to +70°C Industrial: Tamb = -40°C to 485°C Automotive: Tamb = ~40°C to +125°C (Note 3) Input leakage current [ow ff — | 10 [ pa [vm=ovto vec (Note 1) Output leakage current [wo [| — [| 10 | pA |[vour=ovto vec (Note 1) Intemal capacitance . int 7 pF | VinVour = OV (Note 2) {all inputs/outputs) s Tamb = +25°C, f= 1 MHz Operating current (all modes) [tccwrte | — | 4 | ma | Fouk = 1 MHz, Voc = 5.5V Note 1: Intemal resistor pull-up at Pin 6. Note 2: This parameter is periodically sampled and not 100% tested. Note 8: For operation above 85°C, endurance is rated at 10,000 ERASE/WRITE cycles. FIGURE 1-1: _ SYNCHRONOUS DATA TIMING Toot Toa | ftom . ‘ OX we XXXXXXXXMK lo XXKKK oO VALIO ‘VALID \\ XXX XXXXX a =] Tox cs Press Tee K we) = z meee eeeee—C“# ‘DS1479B-page 4-32 ‘© 1995 Microchip Technology Inc.
TABLE 1-3: | AC CHARACTERISTICS ; [___ Parameter [svmbot] win [ wax [units | conations —_| Clock Figh time | too [00 | [ns Glock low tine | toa | 00 [fe Chip select setup time [tess | so [ [ns Chip select iow time [ ten | oo [— [oe [od Data input hold time [tow [too [= [es Data output delay time | teo | — | 400 | ns |oL=100pF Data output disable time (from CS = low) | tz [| 0 [ 100] ns | CL= 100 pF Data output disable time (from tastclock) | Tooz | 0 | 400 | ns _|CL=100pF Status valid time | tev [=] t00 [ns feustoorr | Program cycle time (Auto Erase and Write) | Two For ERAL and WRAL [Ewseqewtine tee | [om |
2.0 PIN DESCRIPTION CLK cycles are not required during the self-timed
WRITE (ie., auto ERASEMWAITE) cycle.
2.1 Chip Select (CS) Atter detection of a start condition, the specified num-
ber of clock cycles (respectively LOW to HIGH transi- faate the declea ae far ace. A LOW level deso- tions of CLK) must be provided. These clock cycles are lects the device ai ing oyele which le ‘ahead initiated required to clock in all required opcode, address, and ever, @ Programming cycl y data bits before an instruction is executed (see instruc- and/or in progress will be completed, regardless of the tion set truth table). CLK and DI then become “Don't CS input signal. If CS is brought LOW during a pro- Care" inputs waiting for a new start condition to be gram cycle, the device will go into standby mode as Setocted ‘soon as the programming cycle is completed. I CS must be LOW for 100 ns minimum (Test) between Note: CS must go LOW between consecutive consecutive instructions. If CS is LOW, the intemal Instructions. control logic Is held in a RESET status. 23 Datain(D) 22° Serial Clock (CLK) Data In Is used to clock in a START bit, opcode, ‘The Serial Clock is used to synchronize the communi- ‘address, and data synchronously with the CLK input. cation between a master device and the 93C06/46. 24 — Data out(p0) Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on Data Out is used in the READ mode to output data the positive edge of CLK. synchronously with the CLK input (Tpo after the posi- CLK can be stopped anywhere in the transmission tive edge of CLK). sequence (at HIGH or LOW level) and can be contin- This pin also provides READY/BUSY status informa- ued anytime (with respect to clock HIGH time (TckH) tion during ERASE and WRITE cycles. READY/BUSY and clock LOW time (Text). This gives the controlling status information is available on the DO pin if CS is master freedom in preparing opcode, address and brought HIGH after being LOW for minimum chip select data, LOW time (Test) from the falling edge of the CLK which i tCare” i locked in the last DI bit (D0 for WRITE, AO for ERASE) CLKis a “Don't Care” if CS is LOW (device deselected). d V EF If CS Is HIGH, but START condition has not been andan ERASE or WRITE operation has been initiated, detected, any number of clock cycles can be received by the device without changing its status. (i.e., waiting for START condition). G 1995 Microchip Technology ine. DS11179B-page 4-33
# eee eee eee The status signal is not available on DO, if CS is held Care must be taken with the leading dummy zero which LOW or HIGH during the entire WRITE or ERASE is outputted after a READ command has been cycle. In all other cases DO is in the HIGH-Z mode. If detected. Also, the controlling device must not drive status is checked after the WRITE/ERASE cycle, a the DDO bus during Erase and Write cycles if the pull-up resistor on DO is required to read the READY READY/BUSY status information is outputted by the signal. 9306/46. DI and DO can be connected together to perform a 3- wire interface (CS, CLK, DV/DO). INSTRUCTION SET - 93006 ‘Opcode . OP1 OP2 [READ to TOC AS AZ AT ADT — SSS | 5 [ware [ot Too A az at Ao_| 015-00 | _(RDYASy)_| 25] [EWEN [oo x xX ighz 9 INSTRUCTION SET - 93046 ‘Opcode ‘Number of Req. CLK OP1 OP2 Data in Cycles jewen oo a xk x xx Cig [ewos Poo oo KX igh 2 [ena [ooo xX x x x vay |
3.0 FUNCTIONAL DESCRIPTION that precedes the READ operation, itAO is alogic HIGH *
level. Under such a condition the voltage level seen at 3.1 START Condition Data ut is undefined and will depend upon the relative. a ; impedances of Data Out and the signal source driving ‘The START bit is detected by the device if CS and DI AO. The higher the current sourcing capability of AO, are both HIGH with respect to the positive edge of CLK the higher the voltage at the Data Out pin. for the first time. ° Before a START condition is detected, CS, CLK, and DI 3.3 Data Protection. may change in any combination (except to that of a , ; pit START condition), without resulting n any device oper- Cn ee erage ooperation are inhibited tion (READ, WRITE, ERASE, EWEN, EWDS, ERAL, Section ce viin nd Power-down, the and WRAL), As soon CS ISHIGH, the device Is no source data protection circuitry acts to inhibit all modes be rim uy standby ‘node ‘s » the device is no when Vcc has fallen below 2.8V. gern a tion wit only b ‘The EWEN and EWDS commands give additional pro- covouted H fre teoueed erent ot open eres tection against accidentally programming during nor- q ration. and data bits for any particular instruction is clocked in. mal operation. ion of an instruction ( ‘i ‘ After power-up, the device is automatically in the fer orecution o are 2. cod Srna EWDS mode, Therefore, an EWEN instruction must be can be executed. After programming is completed, the detected. EWDS instruction offers added protection against unin- 32 pio : tended data changes. Itis possible to connect the Data In and Data Out pins together. However, with this configuration itis possible for a “bus conflict” to occur during the ‘dummy zero" ee DSI1179B-page 4-34 . © 1995 Microchip Technology Inc.
eeSSSSSSSSSsSSSSSSSSSSSSSSSSSSSSSSSSSFE eatin 3.4 READ Mode 3.5 WRITE Mode ‘The READ instruction outputs the serial data of the ‘The WRITE instruction is followed by 16 bits of data addressed memory location on the DO pin. A dummy which are written into the specified address. The most bit (logical 0) precedes the 16-bit output string. The significant data bit (D15) has to be clockad in first, fol- output data changes during the HIGH state of the sys- lowed by the lower significant data bits (D14 - D0). If tem clock (CLK). The dummy bit is output TPO after a WAITE instruction is recognized by the device and all the positive edge of CLK, which was used to clock in data bits have been clocked in, the device performs an the last address bit (AO). Therefore, care must be automatic ERASE cycle on the specified address taken if DI and DO are connected together as a bus before the data are written. The WRITE cycle is com- contention will occur for one clock cycle if AO has been pletely self-timed and commences automatically after aone. the rising edge of the CLK for the last data bit (D0). DO will go into HIGH-Z mode with the positive edge of ‘The WRITE cycle takes 2 ms maximum. the next CLK cycle. This follows the output of the last data bit DO or the low going edge of CS, which ever occurs first. DO remains stable between CLK cycles for an unlim- ited time as long as CS stays HIGH. The most significant data bit (D15) is always output first, followed by the lower significant bits (D14 - Do). | FIGURE 3-1: READ MODE fa | ox | 1 ' ‘$e!
4 Tost,
LL “4 ——
8 Opt OP2 AS A 3 ‘a0 1
1 40 T “| Tor . Toot ee i fj - NEW INSTRUCTION . STANDBY (C5 = 0) FIGURE 3-2: | WRITE MODE i D s_L77 _ I \\ A srans \\_7 1 ' cHeck ! SB. OP! OP2 5 A A os P) H \\ or 7 7 het | = et 1 oe 1 1 Hl eg he ey NEW INSTRUCTION TaN = Sa
9.1995 Microchip Technology tne, DS11179B-page 4-35
3.6 ERASE Mode ee
The ERASE instruction forces all the data bits of the specified address to logical “1s*, The ERASE cycle is completely self-timed and commences automatically after the last address bit has been clocked in. ‘The ERASE cycle takes 1 ms maximum. - FIGURE 3-3: ERASE MODE : ox Leet Tot ft pe To, Lg cs [77 mo F sams \\ Ff 1 { CHECK | . sof! oF A M A ‘fo H H . 1 / OK ROO toro \\ ! ee Toor H Tov pet Let t 4 H i 1 . NEW INSTRUCTION ‘OR STANDBY (CS = 0) (EWEN, EWDS) . The device Is automatically in the ERASEWRITE Disable mode (EWDS) after, power-up. Therefore, an EWEN instruction has to be performed before any ERASE, WRITE, ERAL, WRAL instruction is exe- cuted by the device. For added data protection, the device should be put in the ERASE/WRITE Disable mode (EWDS) alter programming operations are completed. FIGURE 3-4: ERASE/WRITE ENABLE/DISABLE ox RR LLL ae rt Tor mt $8 OP! = OP2 3 o 1 o 0 o o 1S) 1 1 xX xX xX xX ewes | NEW INSTRUCTION, OR STANDBY (CS = 0) meee OOOO DSHMIBB-pago 4.36 ‘© 1985 Microchip Technology Inc. eee a a a
9306/46 Product Identification System . To order or to obtain information, @.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. : 93C06/46 - IP Package: J = CERDIP (300 mil Body) P= Plastic DIP (800 mil Body) SN = Plastic SOIC (150 mil Body) SM = Plastic SOIC (207 mil Body) ‘Temperature Blank = 0°C 10 +70°C Range: 1 = 40°C to 485°C E = 40°C to +125°C . Device: Configuration —wacos 258 bt HOS Seral EEPROM —————— 93C45 1K CMOS Serial EEPROM 93C48X 1K CMOS Serial EEPROM in altemate pinouts (SN package only) 93C08T CMOS Serial EEPROM (Tape and Reel) 93C46T _ CMOS Serlal EEPROM (Tape and Reel) 93C46XT CMOS Serfal EEPROM (Tapo and Reel) Sales and Support - Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational ferences and recom- mended workarounds. To determine i an errata sheet exists for a particular device, please contact one of the following: 1.Your local Microchip sales office 2.The Microchip Corporate Literature Center U.S, FAX: (602) 786-7277 3.The Microchip's Bullain Board, ia your local CompuServe number (CompuServe membership NOT required). Please specity which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. OSHWISBpage 4-36 © 1995 Microchip Technology Inc. . a — = = a a