93479

93479 NSC | Alldatasheet

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Technical content

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3 GA National

256 x 9-Bit Static Random Access Memory General Description Features The 93479 is a 2304-bit read/write Random Access Memo- ™ Commercial address time ry (RAM), organized as 256 words by nine bits per word. It is. 93479—45 ns max ideally suited for scratchpad, small buffer and other applica- 93479A—35 ns max tions where the number of required words is small and ™ Military address access time where the number of required bits per word is relatively 93479—60 ns max large. The ninth bit can be used to provide parity for 8-bit 93479A—45 ns max word systems. ™ Common data input/output @ Features TRI-STATE® output Connection Diagrams 22-Pin Ceramic DIP 28-Pin LCC wd: 7 abi, e822 822 bar —|2 2 a7 43 2 1 2827 26 pos—43 20-6 poss 2s as pos—}4 19s Pye reas days Ld mead 03-47 23; a4 Dos] 6 17 Fas poz—43 TOP zea voz7 16}-a2 para Py a pais 1st poo 410 20/- a1 Doo—}9 14-40 No—fit 19 Ne Ero Bee 12.13 14 15 16 17 18 GND—AI1 12,- WE eisgewee TU/D/9675-1 Top View top View TL/0/9675-3 Order Number 93479DC, 93479ADC, Order Number 93479LMQB or 93479ALMQB 93479DMQB or 93479ADMQB See NS Package Number E28A* See NS Package Number J22A* “For most current package information, contact product marketing. “For most current package information, contact product marketing. Optional Processing QR = Burn In Optional Processing QR = Burn In 9 Pin Names Logic Symbol AO-A7 Address Inputs Data Input Outputs pee | OE __| _ Output Enable Input (Active LOW) Write Enable input (Active LOW) ty 40 Chip Select Input (Active LOW) Ws ssa Bois Voc = Pin 22 ois GND = Pin 11 = " 838232258 987654321 TLD /9675-2 5-32

o eo Absolute Maximum Ratings Guaranteed Operating Ranges s Above which the useful life may be impaired Supply Voltage (Voc) eo Storage Temperature —65°C to + 150°C. Commercial 5.0V +5% Supply Voltage Range —0.5V to +7.0V Military 5.0V +10% Input Voltage (DC) (Notes 1, 2) —0.5V to Voc (RAMs) Case Temperature (Tc) —1.5V to Voc (PROMs) Commercial O°C to +75°C Voltage Applied to Outputs Military —55°C to + 125°C (Notes 2, 3) —0.5V to +5.5V (RAMs) (Output HIGH) —1,5V to +5.5V (PROMs) Lead Temperature (Soldering, 10 seconds) 300°C Maximum Junction Temperature (Ty) +175°C Output Current +20 mA Input Current (DC) —12mAto +5.0mA Note 1: Either Input Voltage limit or Input Current limit is sufficient to protect the inputs. Note 2: Output current limit required. Note 3: Typical values are at Voc = 5.0V. To = +25°C and maximum loading. Note 4: Static condition only. ‘Note 5: Functional testing done at input levels Vi_ = Vor (Max) (0.45V), Vin = Vox (Min) (2.4V). Note 6: AC testing done at input levels Vix, = 3V, Vi. = OV. Note 7: Short circuit to ground not to exceed one second. Note 8: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern. Note 9: ty measured at twsa = Min. twsa measured at ty + Min. 5-33

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3 Logic Diagram

AO yr”? AL x 2 Az i DECODE eas oe MATRIX AS ‘ADDRESS: 1 OF 32 x8x9= 2304 “ a AG 8 iN F WE WE-CS a conan [7 «RAD wT ciRcurTS hd Logic ——_— Diy» Doyy BUFFERS OE: CS- WE Sees eeye 228882888 TL/0/9675~4 Functional Description The 93479 has TRI-STATE outputs which provide an active The 93479 is a fully decoded 2304-bit random access mem- pull-up or pull-down when enabled and a high impedance ory organized 256 words by nine bits. Word selection is (HIGH Z) state when disabled. The active pull-ups provide achieved by means of an 8-bit address AO-A7. drive capability for high capacitive loads while the high im- The Chip Select input provides for memory array expansion. pedance state allows optimization of word expansion in bus For larger memories the fast chip select access time per- organized systems. . mits decoding without an increase in overall memory access ° time. Truth Table The read and write operations are controlled by the state of the active LOW Write Enable (WE) input. With WE held [inputs | Data In/Out LOW, the chip selected and the output disabled, the data at | cs | oe | we | DaQo-pas DQ0-DQ8 is written into the addressed location. Since the - write function is level triggered, data must be held stable for x H x HIGH Z Output Disabled at least twsp(min) Plus twHD(min) to insure a valid write. To H | x x HIGHZ RW Disabled read, WE is held HIGH, the chip selected and the output L L H Data Out Read enabled. Non-inverted data is then presented at the outputs L H L Data In Write DQo-Das. H = HIGH Voltage Level 2.4V L = LOW Voltage Level 0.5V X = Don't Care HIGH or LOW HIGH Z = High Impedance State 5-34

o symbol [Parameter [Gonattons_—|_-Min_ | Typ | Max | Unite Vou Output LOW Voltage Voc = Min, Io. = 8.0 mA [ [| [ o | v Vou Output HIGH Voltage Voc=Minlow=-52ma | 24 | |v Vin Input HIGH Voltage Guaranteed Input HIGH Voltage ot V for All Inputs (Notes 4, 5 & 6) 7 Vit Input LOW Voltage Guaranteed Input LOW Voltage Vv for All Inputs (Notes 4, 5 & 6) i Input LOW Current Voc = Max, Vin = 0.4V [| _-250 | -400 | ya a Input HIGH Current Voc = Max, Vin = 4.5V [ [1 | 4 | ua thas Input Breakdown Current Voc = Max, Vin = Voc [ [| [10 =| om loz Output Current (HIGH Z) Voc = Max, Vout = 2.4V 50 pA lozi Voc = Max, Voyr = 0.5V ~400 BA Vo Input Diode Clamp Voltage | Voo=MaxVw=-1oma | «| 10 | -15 |v los Output Current Voc = Max, (Note 7) ~70 mA Short Circuit to Ground loc Power Supply Current Commercial | Vg = Max 185 mA Military All inputs GND 200 5-35

o t =| Commercial oa ort | team | cmt tet | READ TIMING tacs Chip Select Access Time ns tzRcs Chip Select to HIGH Z ns taos Output Enable Access Time (Figures 3a, 3b, 3d) ns tzRos Output Enable to HIGH Z ns taa Address Access Time (Note 8) ns WRITE TIMING tw Write Pulse Width to Guarantee Writing ns (Note 9) tso Output Enable Setup Time ns tHo Data Enable Hold Time ns twsp Data Setup Time Prior to Write ns twup Data Hold Time after Write (Figure 4) ns twsa Address Setup Time Prior to Write hs (Note 9) twa Address Hold Time after Write ns twscs Chip Select Setup Time Prior to Write ns twres Chip Select Hold Time after Write ns Military READ TIMING tacs Chip Select Access Time 30 40 ns tzAcs Chip Select to HIGH Z 30 40 ns taos Output Enable Access Time (Figures 3a, 3b, 3d) 30 40 ns tzRos Output Enable to HIGH Z 30 40 ns tan Address Access Time (Note 8) 45 60 ns WRITE TIMING tw Write Pulse Width to Guarantee Writing 40 40 ns (Note 9) tso Output Enable Setup Time 5 5 ns to Data Enable Hold Time 5 5 ns twsp Data Setup Time Prior to Write . 50 50 ns twHD Data Hold Time after Write (Figure 4) 10 10 ns twsa Address Setup Time Prior to Write 10 10 1s (Note 9) tWHA Address Hold Time after Write 10 10 ns twscs Chip Select Setup Time Prior to Write 10 10 ns twHcs Chip Select Hold Time after Write 10 10 ns 5-36

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FIGURE 1. AC Test Load Output Load FIGURE 2. AC Test Input Levels a. Read Mode Propagation Delay from Chip Select to Output . FIGURE 3. Read Mode Timing

7 HGH Zone ee oeHIGH Z--

FIGURE 3. Read Mode Timing (Continued) *These timing parameters are only necessary to guarantee High Z state during the entire write cycle. FIGURE 4. Write Mode Timing case limits are not violated. Note 2: Input voltage levels for worst case AC test are 3.0/0.0V.