932SQL456AKILF

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932SQL456 REVISION B 09/29/15 1 ©2015 Integrated Device Technology, Inc. Low-Power CK420BQ Derivative for PCIe Separate Clock Architectures 932SQL456 General Description The 932SQL456 is a low power version of the CK420BQ synthesizer for Intel-based server platforms. It has 85 ohm Low-Power (LP) HCSL outputs that save 48 resistors and reduce power consumption by 50% compared to the standard CK420BQ. The 932SQL456 is driven with a 25MHz crystal for maximum performance. It generates CPU outputs of 100MHz. This device meets Separate- Reference-no-Spread (SRnS) PCIe requirements making it ideal for use in systems that need to communicate “outside the box”. Recommended Application Low-Power CK420BQ for SRnS PCIe Applications Key Specifications

• CPU, SRC, NS_SRC and NS_SAS cycle-cycle jitter <50ps
• Output to output skew <50ps
• Phase jitter: PCIe Gen2 SRnS <2.2ps rms
• Phase jitter: PCIe Gen3 SRnS <0.7ps rms
• Phase jitter: QPI <0.3ps rms
• Phase jitter: NS-SAS <1.3ps rms using long period phase jitter method Features/Benefits
• Integrated 85-ohm differential terminations; saves 48 resistors compared to CK420BQ
• LP-HCSL outputs; up to 50% power savings compared to standard CK420BQ
• 64-pin TSSOP and VFQFPN packages; smallest board footprint
• Available in -40° to +85°C industrial temperature range version; supports demanding operating environments Output Features
• Differential outputs are LP-HCSL with integrated 85Ω terminations
• 11 – non-spreading interchangeable 100MHz differential outputs
• 4 – “CPU” outputs
• 3 – “SRC” outputs
• 1 – DOT96 96MHz output
• 1 – 3.3V 48M output
• 5 – 3.3V PCI outputs
• 1 – 3.3V 14.318M output Pin Configurations SMBCLK 1 64 SMBDAT GND14 2 63 VDDCPU AVDD14 3 62 CPU3_Z85T VDD14 4 61 CPU3_Z85C vREF14_2x/TEST_SELLV 5 60 CPU2_Z85T GND14 6 59 CPU2_Z85C GNDXTAL 7 58 GNDCPU X1_25 8 57 VDDCPU X2_25 9 56 CPU1_Z85T VDDXTAL 10 55 CPU1_Z85C GNDPCI 11 54 CPU0_Z85T VDDPCI 12 53 CPU0_Z85C PCI4_2x 13 52 GNDNS PCI3_2x 14 51 AVDD_NS_SAS PCI2_2x 15 50 NS_SAS1_Z85T PCI1_2x 16 49 NS_SAS1_Z85C PCI0_2x 17 48 NS_SAS0_Z85T GNDPCI 18 47 NS_SAS0_Z85C VDDPCI 19 46 GNDNS VDD48 20 45 VDDNS 48M_2x 21 44 NS_SRC1_Z85T GND48 22 43 NS_SRC1_Z85C GND96 23 42 NS_SRC0_Z85T DOT96_Z85T 24 41 NS_SRC0_Z85C DOT96_Z85C 25 40 NC AVDD96 26 39 GNDSRC TEST_MODE 27 38 AVDD_SRC CKPWRGD#/PD 28 37 VDDSRC VDDSRC 29 36 SRC2_Z85T SRC0_Z85T 30 35 SRC2_Z85C SRC0_Z85C 31 34 SRC1_Z85T GNDSRC 32 33 SRC1_Z85C 64-TSSOP Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown 932SQL456 VDDXTAL X2_25 X1_25 GNDXTAL GND14 vREF14_2x/TEST_SELLV VDD14 AVDD14 GND14 SMBCLK SMBDAT VDDCPU CPU3_Z85T CPU3_Z85C CPU2_Z85T CPU2_Z85C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GNDPCI 1 48 GNDCPU VDDPCI 2 47 VDDCPU PCI4_2x 3 46 CPU1_Z85T PCI3_2x 4 45 CPU1_Z85C PCI2_2x 5 44 CPU0_Z85T PCI1_2x 6 43 CPU0_Z85C PCI0_2x 7 42 GNDNS GNDPCI 8 41 AVDD_NS_SAS VDDPCI 9 40 NS_SAS1_Z85T VDD48 10 39 NS_SAS1_Z85C 48M_2x 11 38 NS_SAS0_Z85T GND48 12 37 NS_SAS0_Z85C GND96 13 36 GNDNS DOT96_Z85T14 35 VDDNS DOT96_Z85C15 34 NS_SRC1_Z85T AVDD96 16 33 NS_SRC1_Z85C 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32TEST_MODE CKPWRGD#/PD VDDSRC SRC0_Z85T SRC0_Z85C GNDSRC SRC1_Z85C SRC1_Z85T SRC2_Z85C SRC2_Z85T VDDSRC AVDD_SRC GNDSRC NC NS_SRC0_Z85C NS_SRC0_Z85T Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown 64-Pin VFQFPN 932SQL456 epad = pin 65, connect to GND

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 2 REVISION B 09/29/15 932SQL456 DATASHEET 64TSSOP Pin Descriptions PIN # PIN NAME TYPE DESCRIPTION

1 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant

2 GND14 PWR Ground pin for 14MHz output and logic.

3 AVDD14 PWR Analog power pin for 14MHz PLL

4 VDD14 PWR Power pin for 14MHz output and logic

5 vREF14_2x/TEST_SELLV I/O

14.318 MHz reference clock capable of driving 2 loads/ TEST_SEL latched input to enable test

mode. The TEST_SEL input is a low threshold input. See the Electrical Tables and the Test Clarification Table. This pin has a weak (~120Kohm) internal pull down. 6 GND14 PWR Ground pin for 14MHz output and logic. 7 GNDXTAL PWR Ground pin for Crystal Oscillator. 8 X1_25 IN Crystal input, Nominally 25.00MHz. 9 X2_25 OUT Crystal output, Nominally 25.00MHz. 10 VDDXTAL PWR 3.3V power for the crystal oscillator. 11 GNDPCI PWR Ground pin for PCI outputs and logic. 12 VDDPCI PWR 3.3V power for the PCI outputs and logic 13 PCI4_2x OUT 3.3V PCI clock output 14 PCI3_2x OUT 3.3V PCI clock output 15 PCI2_2x OUT 3.3V PCI clock output 16 PCI1_2x OUT 3.3V PCI clock output 17 PCI0_2x OUT 3.3V PCI clock output 18 GNDPCI PWR Ground pin for PCI outputs and logic. 19 VDDPCI PWR 3.3V power for the PCI outputs and logic 20 VDD48 PWR 3.3V power for the 48MHz output and logic 21 48M_2x OUT 3.3V 48MHz output 22 GND48 PWR Ground pin for 48MHz output and logic. 23 GND96 PWR Ground pin for DOT96 output and logic. 24 DOT96_Z85T OUT True clock of low-power push-pull differential 96MHz output. Internally terminated to drive 85ohm transmission lines with no external components. 25 DOT96_Z85C OUT Complementary clock of low-power push-pull differential 96MHz output. Internally terminated to drive 85ohm transmission lines with no external components. 26 AVDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic 27 TEST_MODE IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.

28 CKPWRGD#/PD IN

CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs are stopped. 29 VDDSRC PWR 3.3V power for the SRC outputs and logic 30 SRC0_Z85T OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 31 SRC0_Z85C OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 32 GNDSRC PWR Ground pin for SRC outputs and logic. 33 SRC1_Z85C OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 34 SRC1_Z85T OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 35 SRC2_Z85C OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 36 SRC2_Z85T OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 37 VDDSRC PWR 3.3V power for the SRC outputs and logic 38 AVDD_SRC PWR 3.3V power for the SRC PLL analog circuits 39 GNDSRC PWR Ground pin for SRC outputs and logic. 40 NC N/A No Connection.

REVISION B 09/29/15 3 LOW- POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET 64TSSOP Pin Descriptions (cont.) PIN # PIN NAME TYPE DESCRIPTION 41 NS_SRC0_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 42 NS_SRC0_Z85T OUT True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 43 NS_SRC1_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 44 NS_SRC1_Z85T OUT True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 45 VDDNS PWR 3.3V power for the Non-Spr eading differential outputs outputs and logic 46 GNDNS PWR Gr ound pin for non-spreading differential outputs and logic. 47 NS_SAS0_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 48 NS_SAS0_Z85T OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 49 NS_SAS1_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 50 NS_SAS1_Z85T OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 51 AVDD_NS_SAS PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits. 52 GNDNS PWR Gr ound pin for non-spreading differential outputs and logic. 53 CPU0_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 54 CPU0_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 55 CPU1_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 56 CPU1_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 57 VDDCPU PWR 3.3V power for the CPU outputs and logic 58 GNDCPU PWR Gr ound pin for CPU outputs and logic. 59 CPU2_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 60 CPU2_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 61 CPU3_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 62 CPU3_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 63 VDDCPU PWR 3.3V power for the CPU outputs and logic

64 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 4 REVISION B 09/29/15 932SQL456 DATASHEET 64VFQFPN Pin Descriptions PIN # PIN NAME TYPE DESCRIPTION 1 GNDPCI PWR Ground pin for PCI outputs and logic. 2 VDDPCI PWR 3.3V power for the PCI outputs and logic 3 PCI4_2x OUT 3.3V PCI clock output 4 PCI3_2x OUT 3.3V PCI clock output 5 PCI2_2x OUT 3.3V PCI clock output 6 PCI1_2x OUT 3.3V PCI clock output 7 PCI0_2x OUT 3.3V PCI clock output 8 GNDPCI PWR Ground pin for PCI outputs and logic. 9 VDDPCI PWR 3.3V power for the PCI outputs and logic 10 VDD48 PWR 3.3V power for the 48MHz output and logic 11 48M_2x OUT 3.3V 48MHz output 12 GND48 PWR Ground pin for 48MHz output and logic. 13 GND96 PWR Ground pin for DOT96 output and logic. 14 DOT96_Z85T OUT True clock of low-power push-pull differential 96MHz output. Internally terminated to drive 85ohm transmission lines with no external components. 15 DOT96_Z85C OUT Complementary clock of low-power push-pull differential 96MHz output. Internally terminated to drive 85ohm transmission lines with no external components. 16 AVDD96 PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic 17 TEST_MODE IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.

18 CKPWRGD#/PD IN

CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs are stopped. 19 VDDSRC PWR 3.3V power for the SRC outputs and logic 20 SRC0_Z85T OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 21 SRC0_Z85C OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 22 GNDSRC PWR Ground pin for SRC outputs and logic. 23 SRC1_Z85C OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 24 SRC1_Z85T OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 25 SRC2_Z85C OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 26 SRC2_Z85T OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 27 VDDSRC PWR 3.3V power for the SRC outputs and logic 28 AVDD_SRC PWR 3.3V power for the SRC PLL analog circuits 29 GNDSRC PWR Ground pin for SRC outputs and logic. 30 NC N/A No Connection. 31 NS_SRC0_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 32 NS_SRC0_Z85T OUT True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 33 NS_SRC1_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 34 NS_SRC1_Z85T OUT True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to drive 85ohm transmission lines with no external components. 35 VDDNS PWR 3.3V power for the Non-Spr eading differential outputs outputs and logic 36 GNDNS PWR Gr ound pin for non-spreading differential outputs and logic. 37 NS_SAS0_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 38 NS_SAS0_Z85T OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components.

REVISION B 09/29/15 5 LOW- POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET 64VFQFPN Pin Descriptions (cont.) PIN # PIN NAME TYPE DESCRIPTION 39 NS_SAS1_Z85C OUT Complementary clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 40 NS_SAS1_Z85T OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to drive 85ohm transmission lines with no external components. 41 AVDD_NS_SAS PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits. 42 GNDNS PWR Gr ound pin for non-spreading differential outputs and logic. 43 CPU0_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 44 CPU0_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 45 CPU1_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 46 CPU1_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 47 VDDCPU PWR 3.3V power for the CPU outputs and logic 48 GNDCPU PWR Gr ound pin for CPU outputs and logic. 49 CPU2_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 50 CPU2_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 51 CPU3_Z85C OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 52 CPU3_Z85T OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm transmission lines with no external components. 53 VDDCPU PWR 3.3V power for the CPU outputs and logic

54 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant

55 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant

56 GND14 PWR Ground pin for 14MHz output and logic.

57 AVDD14 PWR Analog power pin for 14MHz PLL

58 VDD14 PWR Power pin for 14MHz output and logic

59 vREF14_2x/TEST_SELLV I/O mode. The TEST_SEL input is a low threshold input. See the Electrical Tables and the Test Clarification Table. This pin has a weak (~120Kohm) internal pull down. 60 GND14 PWR Ground pin for 14MHz output and logic. 61 GNDXTAL PWR Ground pin for Crystal Osc illator. 62 X1_25 IN Crystal input, Nominally 25.00MHz. 63 X2_25 OUT Crystal output, Nominally 25.00MHz. 64 VDDXTAL PWR 3.3V power for the crystal oscillator. 65 EPAD GND E pad should be connected to ground.

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 6 REVISION B 09/29/15 932SQL456 DATASHEET Block Diagram Logic SRC_Z85(2:0) SMBDAT SMBCLK CKPWRGD#/PD CPU_Z85(3:0) Non-spreading PCIe PLL NS_SAS_Z85(1:0) NS_SRC_Z85(1:0) DOT96_Z85 48M_2x PCI_2x(4:0) 14.31818MHz Non-SS PLL REF14_2x Test_Mode Test_Sel Non-SS PLL IDT 603-25-150JA4C or 603-25-150JA4I 25M X1_25

REVISION B 09/29/15 7 LOW- POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Power Supply and Test Loads Alternate Terminations The 932SQL456 can also drive other logic levels such as LVPECL, LVDS, and CML. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's "Universal" Low-Power HCSL Outputs” for details. Power Group Pin Numbers VDD GND VDD GND 57 56 3 2 14MHz PLL Analog 58 60 4 6 REF14M Output and Logic 64 61 10 7 25MHz XTAL 2, 9 1, 8 12, 19 11, 18 PCI Outputs and Logic 10 12 20 22 48MHz Output and Logic 16 13 26 23 96MHz PLL Analog, Output and Logic 19, 27 22 29, 37 32 SRC Outputs and Logic 28 29 38 39 SRC PLL Analog 35 36 45 46 Non-Spreading Differential Outputs & Logic 41 42 51 52 NS-SAS/SRC PLL Analog 47, 53 48 57,63 58 CPU Outputs and Logic VFQFPN DescriptionTSSOP Low-Power Differential Output (w/Integrated Rs) Test Load 2pF 10 inches Zo = 85 2pF Rs=27 CL=5pF 10 inches Zo = 50 Single-ended Output Test Load Rs=29and 20 inches for REF Alternate termination for driving 100 transmission lines 2pF Zo = 100 2pF Rs=7.5 Rs=7.5 Rs=16 Zo = 50 CL=5pF Rs=16 Zo = 50 CL=5pF Alternate termination for driving 2 50 loads

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 8 REVISION B 09/29/15 932SQL456 DATASHEET Functionality Tables Clock AC Tolerances Clock Periods–Outputs 932SQL456 Functionality CPU SRC PCI REF NS_SAS NS_SRC DOT96 USB 932SQL456 Power Down Functionality CKPWRGD#/PD Differential Outputs Single- ended Outputs Single- ended Outputs w/Latch 1L o w / L o w Low Low1 1. Single-ended outputs with a Latch will be Hi-Z until the first application of CKPWRGD#. Running CPU, SRC NS_SAS, NS_SRC PCI DOT96 48MHz REF 100 100 100 100 100 100 ppm 50 50 250 50 250 250 ps PPM tolerance Cycle to Cycle Jitter Spread 1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock -c2c jitter AbsPer Min -SSC Short-Term Average Min - ppm Long-Term Average Min 0 ppm Period Nominal + ppm Long-Term Average Max +SSC Short-Term Average Max +c2c jitter AbsPer Max CPU, SRC, NS_SAS, NS_SRC 1,2 1Guaranteed by design and characterization, not 100% tested in production. Notes 2 All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to exactly 14.31818MHz. Measurement Window UnitsSSC OFF Center Freq. MHz

REVISION B 09/29/15 9 LOW- POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 932SQL456. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Electrical Characteristics–Current Consumption Outputs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 3.3V Core Supply Voltage VDDA 4.6 V 1,2 3.3V Logic Supply Voltage VDD 4.6 V 1,2 Input Low Voltage V IL GND-0.5 V 1 Input High Voltage V IH Except for SMBus interface V DD+0.5V V 1 Input High Voltage V IHSMB SMBus clock and data pins 5.5V V 1 Storage Temperature Ts -65 150 °C 1 Junction Temperature Tj 125 °C 1 Case Temperature Tc 110 °C 1 Input ESD protection ESD prot Human Body Model 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Supply Current I DD3.3OP All outputs active @100MHz, CL = Full load; 217 250 mA 1 Powerdown Current IDD3.3PDZ 4.3 8 mA 1 1Guaranteed by design and characterization, not 100% tested in production. TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Duty Cycle t DC Measured differentially, PLL Mode 45 49.6% 55 % Skew, Output to Output t sk3SRC Across all SRC outputs, VT = 50% 23 50 ps 1 Skew, Output to Output t sk3CPU Across all CPU outputs, VT = 50% 24 50 ps 1 CPU, SRC, NS_SAS outputs 6 50 ps 1,3 DOT96 output 5 50 ps 1,3 1Guaranteed by design and characterization, not 100% tested in production. 2 Zo=85Ω (differential impedance).

3 Measured from differential waveform

Jitter, Cycle to cycle t jcyc-cyc

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 10 REVISION B 09/29/15 932SQL456 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Voltage V 3.135 3.3 3.465 V Commmercial range 0 70 °C Industrial range -40 85 °C Input High Voltage V IH Single-ended inputs, except SMBus, low threshold and tri- level inputs 2V DD + 0.3 V Input Low Voltage V IL Single-ended inputs, except SMBus, low threshold and tri- level inputs GND - 0.3 0.8 V IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA IINP Single-ended inputs. VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA Low Threshold Input- High Voltage VIH_FS 3.3 V +/-5% 0.7 V DD + 0.3 V Low Threshold Input- Low Voltage VIL_FS 3.3 V +/-5% V SS - 0.3 0.35 V Input Frequency F i 25.00 MHz 2 Pin Inductance L pin 7n H 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 5 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization T STAB From VDD Power-Up and after input clock stabilization or de- assertion of PD# to 1st clock 1.8 ms 2 Tdrive_PD# t DRVPD Differential output enable after PD# de-assertion 300 us 1,3 Tfall t F Fall time of control inputs 5 ns 1,2 Trise t R Rise time of control inputs 5 ns 1,2 SMBus Input Low Voltage VILSMB 0.8 V SMBus Input High Voltage VIHSMB 2.1 V DDSMB V SMBus Output Low Voltage VOLSMB @ IPULLUP 0.4 V SMBus Sink Current I PULLUP @ VOL 4m A Nominal Bus Voltage V DDSMB 3V to 5V +/- 10% 2.7 5.5 V 1 SCLK/SDATA Rise Time t RSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time t FSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 SMBus Operating Frequency fSMB SMBus operating frequency 400 kHz 1Guaranteed by design and characterization, not 100% tested in production. 2Control input must be monotonic from 20% to 80% of input swing. Input Current Capacitance TAMB Ambient Operating Temperature 3Time from deassertion until outputs are >200 mV

REVISION B 09/29/15 11 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Outputs Electrical Characteristics–48MHz TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate dV/dt Scope averaging on 2 3.3 4.5 V/ns 1, 2, 3 Slew rate matching ∆dV/dt Slew rate matching, Scope averaging on 11.1 20 % 1, 2, 4 Rise/Fall Time Matching ∆Trf Rise/fall matching, Scope averaging off 9.0 125 ps 1, 8, 9 Voltage High VHigh 660 845 850 Voltage Low VLow -150 122 150 Max Voltage Vmax 1026 1150 1, 7 Min Voltage Vmin -300 -22 1, 7 Crossing Voltage (abs) Vcross_abs Scope averaging off 250 482 550 mV 1, 5 Crossing Voltage (var) ∆-Vcross Scope averaging off 22 140 mV 1, 6

2 Measured from differential waveform

7 Includes overshoot and undershoot.

8 Measured from single-ended waveform

9 Measured with scope averaging off, using statistics function. Variation is difference between min and max. 4 Matching applies to rising edge rate for Clock and fa lling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) mV Measurement on single ended signal using absolute value. mV 1Guaranteed by design and characterization, not 100% tested in production. Z O=85Ω (differential impedance). 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output High Voltage V OH IOH = -1 mA 2.4 V Output Low Voltage V OL IOL = 1 mA 0.55 V Clock High Time T HIGH 1.5V 8.094 10.036 ns 1 Clock Low Time T LOW 1.5V 7.694 9.836 ns 1 Edge Rate t slewr/f_USB Rising/Falling edge rate 1 1.7 2 V/ns 1,2 Duty Cycle d t1 VT = 1.5 V 45 50.4 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 29 250 ps 1 See "Power Supply and Test Loads" page for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. 2 Measured between 0.8V and 2.0V

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 12 REVISION B 09/29/15 932SQL456 DATASHEET Electrical Characteristics–PCI Electrical Characteristics–Phase Jitter Parameters TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Output High Voltage V OH IOH = -1 mA 2.4 V Output Low Voltage V OL IOL = 1 mA 0.55 V Clock High Time T HIGH 1.5V 12 ns 1 Clock Low Time T LOW 1.5V 12 ns 1 Edge Rate t slewr/f Rising/Falling edge rate 1 1.7 4 V/ns 1,2 Duty Cycle d t1 VT = 1.5 V 45 50.6 55 % 1 Group Skew t skew VT = 1.5 V 496 550 ps 1 Jitter, Cycle to cycle t jcyc-cyc VT = 1.5 V 23 250 ps 1 See "Power Supply and Test Loads" page for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. 2 Measured between 0.8V and 2.0V TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX IND. LIMIT UNITS Notes tjphPCIeG1 PCIe Gen 1 24.8 30 86 ps (p-p) 1,2,3, PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 0.54 0.7 3 ps (rms) 1,2,6 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 2.2 2.6/3 3.1 ps (rms) 1,2,6 tjphPCIeG3Com PCIe Gen 3 Common Clock (PLL BW of 2-4MHz. CDR = 10MHz) 0.46 0.6 1 ps (rms) 1,2,4, tjphPCIeG3SRn S PCIe Gen 3 Separate Reference no Spread (SRnS) (PLL BW of 2-4MHz. CDR = 10MHz) 0.46 0.6 0.7 ps (rms) 1,2,4, QPI & SMI (100MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.24 0.4 0.5 ps (rms) 1,5,6 QPI & SMI (100MHz, 8.0Gb/s, 12UI) 0.13 0.15 0.3 ps (rms) 1,5,6 QPI & SMI (100MHz, 9.6Gb/s, 12UI) 0.11 0.13 0.2 ps (rms) 1,5,6 tjphSAS12G SAS 12G 0.84 1.1/1.2 1.3 ps (rms) 1,5,6 1 Guaranteed by design and characterization, not 100% tested in production. 6 Applied to SRC, CPU and NS_SRC, NS_SAS outputs, second figure if present applies to -40C. tjphPCIeG2 tjphQPI_SMI 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.6 Phase Jitter

REVISION B 09/29/15 13 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Test Clarification Table TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Output High Voltage V OH IOH = -1 mA 2.4 V Output Low Voltage V OL IOL = 1 mA 0.55 V Clock High Time T HIGH 1.5V 27.5 ns 1 Clock Low Time T LOW 1.5V 27.5 ns 1 Edge Rate t slewr/f Rising/Falling edge rate 1 1.9 4 V/ns 1,2 Duty Cycle d t1 VT = 1.5 V 45 50.2 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 19 250 ps 1 See "Power Supply and Test Loads" page for termination circuits 1Guaranteed by design and characterization, not 100% tested in production. 2 Measured between 0.8V and 2.0V Comments TEST_SEL HW PIN TEST_MOD E HW PIN TEST ENTRY BIT B6b6 REF/N or HI-Z B6b7 OUTPUT

0 X 0 X NORMAL

B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z) HW SW Power-up w/ TEST_SEL = 1 (>0.7V) to enter test mode. TEST_SEL is low threshold input. Cycle power to disable test mode. If TEST_SEL HW pin is 0 during power-up, test mode can be selected through B6b6. If test mode is selected by B6b6, then B6b7 is used to select HI-Z or REF/N FS_B/TEST_Mode pin is not used. Cycle power to disable test mode.

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 14 REVISION B 09/29/15 932SQL456 DATASHEET General SMBus Serial Interface Information for 932SQL456 How to Write

• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit Index Block Write Operation Controller (Host) ID T (Slave/Receiver) Ts t a r T b i t Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N X Byte ACK O OO OO O Byte N + X - 1 ACK Ps t o P b i t Read Address Write Address D3(H) D2(H) Index Block Read Operation Controller (Host) IDT (Slave/Receiver) Ts t a r T b i t Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count=X ACK X Byte Beginning Byte N ACK O OO OO O Byte N + X - 1 N Not acknowledge Ps t o P b i t

REVISION B 09/29/15 15 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET NOTE: Pin numbers refer to TSSOP SMBus Table: Output Enable Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 DOT96 Enable Output Enable RW Disable-Low/Low Enable 1 Bit 6 NS_SAS1 Enable Output Enable RW Disable-Low/Low Enable 1 Bit 5 NS_SAS0 Enable Output Enable RW Disable-Low/Low Enable 1 Bit 4 NS_SRC1 Enable Output Enable RW Disable-Low/Low Enable 1 Bit 3 NS_SRC0 Enable Output Enable RW Disable-Low/Low Enable 1 Bit 2 SRC2 Enable Output Enable RW Disable-Low/Low Enable 1 Bit 1 SRC1 Enable Output Enable RW Disable-Low/Low Enable 1 Bit 0 SRC0 Enable Output Enable RW Disable-Low/Low Enable 1 SMBus Table: Output Enable Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 REF14_2x Enable Output Enable RW Disable-Low Enable 1 Bit 6 0 Bit 5 0 Bit 4 CPU3 Output Enable RW Disable-Low/Low Enable 1 Bit 3 CPU2 Output Enable RW Disable-Low/Low Enable 1 Bit 2 CPU1 Output Enable RW Disable-Low/Low Enable 1 Bit 1 CPU0 Output Enable RW Disable-Low/Low Enable 1 Bit 0 0 SMBus Table: Output Enable Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 PCI4 Enable Output Enable RW Disable-Low Enable 1 Bit 4 PCI3 Enable Output Enable RW Disable-Low Enable 1 Bit 3 PCI2 Enable Output Enable RW Disable-Low Enable 1 Bit 2 PCI1 Enable Output Enable RW Disable-Low Enable 1 Bit 1 PCI0 Enable Output Enable RW Disable-Low Enable 1 Bit 0 48MHz Enable Output Enable RW Disable-Low Enable 1 SMBus Table: Differential Amplitude Control Pin # Name Control Function T ype 0 1 Defaul t Bit 7 CPU AMPLITUDE 1 RW 00 = 700mV 01 = 800mV 0 Bit 6 CPU AMPLITUDE 0 RW 10 = 900mV 11 = 1000mV 1 Bit 5 SRC AMPLITUDE 1 RW 00 = 700mV 01 = 800mV 0 Bit 4 SRC AMPLITUDE 0 RW 10 = 900mV 11 = 1000mV 1 Bit 3 DOT96 AMPLITUDE 1 RW 00 = 700mV 01 = 800mV 0 Bit 2 DOT96 AMPLITUDE 0 RW 10 = 900mV 11 = 1000mV 1 Bit 1 NS-SAS/SRC AMPLITUDE 1 RW 00 = 700mV 01 = 800mV 0 Bit 0 NS-SAS/SRC AMPLITUDE 0 RW 10 = 900mV 11 = 1000mV 1 SMBus Table: Reserved Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 1 Bit 0 1 RESERVED Byte 3 RESERVED Byte 0 Byte 2 Byte 4 RESERVED RESERVED CPU Vhigh SRC Vhigh DOT96 Vhigh NS-SAS/SRC Vhigh Byte 1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 16 REVISION B 09/29/15 932SQL456 DATASHEET SMBus Table: Reserved Pin # Name Control Function T ype 0 1 Defaul t Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 1 SMBus Table: Test Mode and CPU/SRC/PCI Frequency Select Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 Test Mode Test Mode Type RW Hi-Z REF/N 0 Bit 6 Test Select Select Test Mode RW Disable Enable 0 Bit 5 0 Bit 4 1 Bit 3 0 Bit 2 0 Bit 1 1 Bit 0 1 SMBus Table: Vendor & Revision ID Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 RID3 R 0 Bit 6 RID2 R 0 Bit 5 RID1 R 0 Bit 4 RID0 R 0 Bit 3 VID3 R 0 Bit 2 VID2 R 0 Bit 1 VID1 R 0 Bit 0 VID0 R 1 SMBus Table: Byte Count Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 0 Bit 2 BC2 RW 0 Bit 1 BC1 RW 0 Bit 0 BC0 RW 1 SMBus Table: Device ID Register Pin # Name Control Function T ype 0 1 Defaul t Bit 7 DID7 R -- 0 Bit 6 DID6 R -- 1 Bit 5 DID5 R -- 0 Bit 4 DID4 R -- 0 Bit 3 DID3 R -- 0 Bit 2 DID2 R -- 1 Bit 1 DID1 R -- 1 Bit 0 DID0 R -- 0 RESERVED Device ID (46 hex) Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back, default is A bytes. (0 to 9 VENDOR ID RESERVED Byte 5 RESERVED RESERVED REVISION ID (10h for A rev) RESERVED RESERVED Byte 7 Byte 8 Byte 6 0001 for ICS/IDT RESERVED RESERVED 0 for A rev Byte 9 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

REVISION B 09/29/15 17 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET Recommended Crystal Characteristics (3225 package) Marking Diagrams Notes: 1. “L” denotes Pb-free, RoHS compliant. 2. “LOT” denotes the lot number. 3. “YYWW” denotes the last two digits and week the part was assembled. 4. “COO” denotes the country of origin. 5. “A” denotes the device revision designator. 6. Bottom marking (TSSOP only): country of origin. PARAMETER VALUE UNITS NOTES Frequency 25 MHz 1 Resonance Mode Fundamental - 1 Frequency Tolerance @ 25°C ±20 PPM Max 1 Frequency Stability, ref @ 25°C Over Operating Temperature Range ±20 PPM Max 1 Temperature Range (commerical) 0~70 ° C 1 Temperature Range (industrial) -40~85 ° C 2 Equivalent Series Resistance (ESR) 50 Ω Max 1 Shunt Capacitance (CO)7 p F M a x 1 Load Capacitance (CL)8 p F M a x 1 Drive Level 0.3 mW Max 1 Aging per year ±5 PPM Max 1 Notes: 1. IDT 603-25-150JA4C or 603-25-150JA4I 64TSSOP ICS LOT YYWW 932SQL456AGL 64VFQFPN ICS 932SQL456AL LOT COO YYWW 64TSSOP ICS LOT YYWW 932SQL456AIL 64VFQFPN ICS 32SQL456AIL LOT COO YYWW

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 18 REVISION B 09/29/15 932SQL456 DATASHEET Package Outline and Package Dimensions (64-pin TSSOP) INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* S y m b o l M i nM a xM i nM a x A – 1.20 – .047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 0.32 0.41 b0 . 1 7 0 . 2 7 . 0 0 7 . 0 1 1 c 0.09 0.20 .0035 .008 D 16.90 17.10 .665 .673 E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC aaa – 0.10 – .004 L 0 . 4 50 . 7 5. 0 1 8. 0 3 0 a0  8 0 8

REVISION B 09/29/15 19 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 20 REVISION B 09/29/15 932SQL456 DATASHEET

REVISION B 09/29/15 21 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 932SQL456 DATASHEET

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES 22 REVISION B 09/29/15 932SQL456 DATASHEET

Ordering Information

"LF" suffix to the part number denotes Pb-Free configuration, RoHS6.6 compliant. “A” is the device revision designator (will not correlate with the datasheet revision).

Revision History

Part / Order Number Shipping Packaging Package Temperature 932SQL456AGLF Tubes 64-pin TSSOP 0 to +70° C 932SQL456AGLFT Tape and Reel 64-pin TSSOP 0 to +70° C 932SQL456AKLF Tray 64-pin VFQFPN 0 to +70° C 932SQL456AKLFT Tape and Reel 64-pin VFQFPN 0 to +70° C 932SQL456AGILF Tubes 64-pin TSSOP -40 to +85° C 932SQL456AGILFT Tape and Reel 64-pin TSSOP -40 to +85° C 932SQL456AKILF Tray 64-pin VFQFPN -40 to +85° C 932SQL456AKILFT Tape and Reel 64-pin VFQFPN -40 to +85° C Rev. Issue Date Who Description Page # A 8/5/2015 RDW 1. Updated front page text and data sheet title. 2. Updated REF14 pin name to reflect 2x drive. 3. Update pin description for REF14 pin. 4. Moved block diagram to page 1 and pinouts to page 2. 5. Updated block diagram to incorporate crystal recommendations. 6. Updated Clock AC tolerance to reflected tightened c2c jitter specs on single ended outputs. 7. Updated Clock periods table accordingly. 8. Updated AC/DC Electrical tables with char data. 9. Updated package drawing to latest format for NLG64. 10. Move to final and release. 1-14,20 B 9/29/2015 RDW 1. Added I-temp device to data sheet 2. Changed max power down current from 6mA to 8mA 3. Slight updates to PCIe Gen2 Hi-band and SAS12G for -40C 4. Corrected typo in bit name of Byte 1, bit 7. 5. Updated marking diagrams to include I-temp devices 6. Updated ordering information to include I-temp devices. 1,9,12, 15,17,

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